Showing papers on "MOSFET published in 2000"

FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

Abstract: MOSFETs with gate length down to 17 nm are reported To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed By using boron-doped Si/sub 04/Ge/sub 06/ as a gate material, the desired threshold voltage was achieved for the ultrathin body device The quasiplanar nature of this new variant of the vertical double-gate MOSFETs can be fabricated relatively easily using the conventional planar MOSFET process technologies

Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture

Abstract: A FinFET device is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity. In one embodiment two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

Abstract: Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.

AlGaN/GaN metal oxide semiconductor heterostructure field effect transistor

Abstract: We report on the AlGaN/GaN metal oxide semiconductor heterostructure field effect transistor (MOS-HFET) and present the results of the comparative studies of this device and a base line AlGaN/GaN heterostructure field effect transistor (HFET). For a 5-/spl mu/ source-to-drain opening, the maximum current was close to 600 mA/mm for both devices. The gate leakage current for the MOS-HFET was more than six orders of magnitude smaller than for the HFET.

Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs

Abstract: Short-channel effects in fully-depleted double-gate (DG) and cylindrical, surrounding-gate (Cyl) MOSFETs are governed by the electrostatic potential as confined by the gates, and thus by the device dimensions. The simple but powerful evanescent-mode analysis shows that the length /spl lambda/, over which the source and drain perturb the channel potential, is 1//spl pi/ of the effective device thickness in the double-gate case, and 1/4.810 of the effective diameter in the cylindrical case, in excellent agreement with PADRE device simulations. Thus for equivalent silicon and gate oxide thicknesses, evanescent-mode analysis indicates that Cyl-MOSFETs can be scaled to 35% shorter channel lengths than DG-MOSFETs.

An analytical solution to a double-gate MOSFET with undoped body

Abstract: A one-dimensional (1-D) analytical solution is derived for an undoped (or lightly-doped) double-gate MOSFET by incorporating only the mobile charge term in Poisson's equation. The solution gives closed forms of band bending and volume inversion as a function of silicon thickness and gate voltage. A threshold criterion is derived which serves to quantify the gate work function requirements for a double-gate CMOS.

Electron and hole mobility enhancement in strained-Si MOSFET's on SiGe-on-insulator substrates fabricated by SIMOX technology

Abstract: We have newly developed strained-Si MOSFET's on a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology. Their electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFET's. Using an epitaxial regrowth technique of a strained-Si film on a relaxed-Si/sub 0.9/Ge/sub 0.1/ layer and the conventional SIMOX process, strained-Si (20 nm thickness) layer on fully relaxed-SiGe (340 nm thickness)-on-buried oxide (100 nm thickness) was formed, and n-and p-channel strained-Si MOSFET's were successfully fabricated. For the first time, the good FET characteristics were obtained in both n-and p-strained-SOI devices. It was found that both electron and hole mobilities in strained-SOI MOSFET's were enhanced, compared to those of control SOI MOSFET's and the universal mobility in Si inversion layer.

Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design

Abstract: This paper, focusing on the effect of a plasma-enhanced CVD (PECVD) nitride contact-etch-stop layer, reports that process-induced mechanical stress affects the performance of short-channel CMOSFETs. We argue that the internal stress in the nitride layer changes transconductance (G/sub m/), thereby degrading NMOSFET performance by up to 8% and improving PMOSFET performance up to 7%. These performance changes are caused by changes of the electron and hole mobilities, so a precise transistor model considering this mobility change is necessary for deep-submicron transistor design.

On the performance limits for Si MOSFETs: a theoretical study

Abstract: Performance limits of silicon MOSFETs are examined by a simple analytical theory augmented by self-consistent Schrodinger-Poisson simulations. The on-current, transconductance, and drain-to-source resistance in the ballistic limit (which corresponds to the channel length approaching zero) are examined. The ballistic transconductance in the limit that the oxide thickness approaches zero is also examined. The results show that as the channel length approaches zero (which corresponds to the ballistic limit), the on-current and transconductance approach finite limiting values and the channel resistance approaches a finite minimum value. The source velocity can be as high as about 1.5/spl times/10/sup 7/ cm/s. The limiting on-current and transconductance are considerably higher than those deduced experimentally by a previous study of MOSFETs with channel lengths greater than 0.2 /spl mu/m. At the same time, the transconductance to current ratio is substantially lower than that of a bipolar transistor.

BSIM4 gate leakage model including source-drain partition

Abstract: Gate dielectric leakage current becomes a serious concern as sub-20 /spl Aring/ gate oxide prevails in advanced CMOS processes Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed This model has been implemented in BSIM4

A review of the pseudo-MOS transistor in SOI wafers: operation, parameter extraction, and applications

Abstract: The pseudo-MOS transistor (/spl Psi/-MOSFET) is a surprising and useful technique for the rapid evaluation of SOI wafers, prior to any CMOS processing. We review the static and dynamic modes of operation as well as the main models and methods for electrical parameter extraction. Selected numerical simulations are presented in order to clarify the optimal conditions of operation. Finally, practical applications are exemplified which illustrate the efficiency of the /spl Psi/-MOSFET technique for in situ characterization of SOI technologies and processes.

Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors

Abstract: Summary form only given. We investigate scaling challenges and outline device design requirements needed to support high performance-low power planar CMOS transistor structures with physical gate lengths (L/sub GATE/) below 50 nm. This work uses a combination of simulation results, experimental data and critical analysis of published data. A realistic assessment of gate oxide thickness scaling and maximum tolerable oxide leakage is provided. We conclude that the commonly accepted upper limit of 1 A/cm/sup 2/ for gate leakage is overly pessimistic and that leakage values of up to 100 A/cm/sup 2/ are deemed acceptable for future logic technology generations. Unique channel mobility and junction edge leakage degradation mechanisms, which become prominent at 50 nm L/sub GATE/ dimensions, are highlighted using quantitative analysis. Source-drain extension (SDE) profile design requirements to simultaneously minimize short channel effects (SCE) and achieve low parasitic resistance for sub-50 nm L/sub GATE/ transistors are described for the first time.

Monolithically integrated trench mosfet and schottky diode

Abstract: A monolithically integrated Schottky diode together with a high performance trenched gate MOSFET. A MOS enhanced Schottky diode structure (210) is interspersed throughout the trench MOSFET cell array (206, 212) to enhance the performance characteristics of the MOSFET switch. The forward voltage drop is reduced by taking advantage of the low barrier height of the Schottky structure. In a specific embodiment, the width of the trench is adjusted such that depletion in the drift region of the Schottky is influenced and controlled by the adjacent MOS structure to increase the reverse voltage capability of the Schottky diode.

Gate length scaling and threshold voltage control of double-gate MOSFETs

Abstract: In the nanoscale regime, the double-gate MOSFET can provide superior short-channel behavior. For this structure, device scaling issues are explored. Gate length scaling will be limited by the ability to control off-state leakage current due to quantum tunneling and thermionic emission between the source and drain as well as band-to-band tunneling between the body and drain. Lateral S/D doping abruptness requirements for gate length scaling are examined. V/sub T/ control will be challenging as a single gate material for both NMOS and PMOS devices cannot provide low yet symmetrical V/sub T/'s. CMOS integration will thus require dual gate workfunction tuning, channel doping, or asymmetrical double-gates to adjust V/sub T/. Advantages of using alternative channel materials to facilitate scaling are investigated.

Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric

Abstract: We present a study on the characterization and modeling of direct tunneling gate leakage current in both N- and P-type MOSFETs with ultrathin silicon nitride (Si/sub 3/N/sub 4/) gate dielectric formed by the jet-vapor deposition (JVD) technique. The tunneling mechanisms in the N- and PMOSFETs were clarified. The electron and hole tunneling masses and barrier potentials for the different tunneling mechanisms mere extracted from measured data using a new semi-empirical model. This model was used to project the scaling limits of the JVD Si/sub 3/N/sub 4/ gate dielectric based on the supply voltages for the various technology nodes and the maximum tolerable direct tunneling gate current for high-performance and low-power applications.

A new linearization technique for MOSFET RF amplifier using multiple gated transistors

Abstract: A simple linearization technique using multiple gated common source transistors is proposed where gate width and gate drive (V/sub gs/-V/sub th/) of each transistor are chosen to compensate for the nonlinear characteristics of the main transistor. To demonstrate the feasibility of this approach, a prototype double-gated RF amplifier using two MOSFETs is implemented and its RF characteristics are compared with those of a single one. The results show that, compared with a conventional single-gate transistor amplifier, the third order intermodulation (IMD/sub 3/) is improved by 6 dB with similar gain, fundamental output power, and DC power consumption. Because the auxiliary transistor is smaller than the main one and biased at subthreshold, adding this does not affect amplifier characteristics appreciably other than the nonlinearity. With further optimization using multiple gated transistors, much better nonlinear performance per power consumption would be expected.

Interface trap profile near the band edges at the 4H-SiC/SiO2 interface

Abstract: The transconductance of SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) is typically much lower in devices fabricated on the 4H-SiC polytype compared to 6H. It is believed that this behavior is caused by extreme trapping of inversion electrons due to a higher density of traps Dit at the SiC/SiO2 interface in 4H-SiC. Here we present an approach for profiling Dit versus energy in the band gap using a modified capacitance–voltage technique on large-area MOSFETs. We find that Dit increases towards the conduction band edge Ec in both polytypes, and that Dit is much higher in 4H- compared to 6H-SiC for devices fabricated in the same process lot.

High hole mobility in Si0.17Ge0.83 channel metal–oxide–semiconductor field-effect transistors grown by plasma-enhanced chemical vapor deposition

Abstract: We report on effective hole mobility in SiGe-based metal–oxide–semiconductor (MOS) field-effect transistors grown by low-energy plasma-enhanced chemical vapor deposition The heterostructure layer stack consists of a strained Si017Ge083 alloy channel on a thick compositionally-graded Si052Ge048 buffer Structural assessment was done by high resolution x-ray diffraction Maximum effective hole mobilities of 760 and 4400 cm2/Vs have been measured at 300 and 77 K, respectively These values exceed the hole mobility in a conventional Si p-MOS device by a factor of 4 and reach the mobility data of conventional Si n-MOS transistors

Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method

Abstract: High performance super TFTs with different channel widths and lengths, formed by a novel grain enhancement method, are reported. High temperature annealing has been utilized to enhance the polysilicon grain and improve the quality of silicon crystal after low temperature MILC treatment on amorphous silicon. With device scaling, it is possible to fabricate the entire transistor on a single grain, thus giving the performance of single crystal SOI MOSFET. The effects of grain boundaries on device performance have been studied, indicating the existence of extra leakage current paths caused by the grain boundaries traversing the channel, which induced subthreshold hump and early punchthrough of wide devices. The probability for the channel region of a TFT to cover multiple grains decreases significantly when the device is scaled down, resulting in better device performance and higher uniformity.

Worst-case bias during total dose irradiation of SOI transistors

Abstract: The worst case bias during total dose irradiation of partially depleted SOI transistors from two technologies is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide.

Modeling of 10-nm-scale ballistic MOSFET's

Abstract: We have performed numerical modeling of nanoscale dual-gate ballistic n-MOSFET's with ultrathin undoped channel, taking into account the effects of quantum tunneling along the channel and through the gate oxide. The results show that transistors with channel length as small as 8 nm can exhibit either a transconductance up to 4000 mS/mm or gate modulation of current by more than 8 orders of magnitude, depending on the gate oxide thickness. These characteristics make the sub-10-nm devices potentially suitable for logic and memory applications, though their parameters are rather sensitive to size variations.

30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays

Abstract: Planar CMOS transistors have been fabricated to evaluate the 70 nm technology node using conventional transistor design methodologies Conventional CMOS transistors with 30 nm physical gate length were fabricated using aggressively scaled junctions, polysilicon gate electrode, gate oxide and Ni silicide These devices have inversion Cox exceeding 19 /spl mu/F/cm2, n-MOS gate delay (CV/I) of 094 ps and p-MOS gate delay of 17 ps at V/sub cc/=085 V These are the smallest CV/I values ever reported for Si CMOS devices The transistors also show good short channel control and subthreshold swings The n-MOS and p-MOS have drive currents equal to 514 /spl mu/A//spl mu/m and 285 /spl mu/A//spl mu/m respectively with I/sub off/ at or below 100 nA//spl mu/m at Vcc=085 V The saturation gm is equal to 1200 mS/mm for n-MOS and 640 mS/mm for p-MOS These are among the highest gm values ever reported The junction edge leakage is reasonably low with less than 1 nA//spl mu/m at 10 V and 100 C for both n-MOS and p-MOS These encouraging results suggest that the 70 nm technology node is achievable using conventional planar transistor design and process flow

Highly suppressed short-channel effects in ultrathin SOI n-MOSFETs

Abstract: We have investigated short-channel effects of ultrathin (4-18-nm thick) silicon-on-insulator (SOI) n-channel MOSFET's in the 40-135 nm gate length regime. It is experimentally and systematically found that the threshold voltage (V/sub th/) roll-off and subthreshold slope (S-slope) are highly suppressed as the channel SOI thickness is reduced. The experimental 40-nm gate length, 4-nm thick ultrathin SOI n-MOSFET shows the S-slope of only 75 mV and the /spl Delta/V/sub th/ of only 0.07 V as compared to the value in the case of the long gate-length (135 nm) device. Based on these experimental results, the remarkable advantage of an ultrathin SOI channel in suppressing the short-channel effects is confirmed for future MOS devices.

MOS field-effect transistor with auxiliary electrode

Abstract: A MOS field-effect transistor is disclosed having a low on resistance Ron, in which auxiliary electrodes composed of polycrystalline silicon surrounded by an insulating layer are provided in the drift path between semiconductor regions of one conduction type. A MOSFET according to the invention may be fabricated in a simple manner compared to conventional MOSFETs using, for example, trench processing technology.

Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance

Abstract: Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/μm or below) and a channel length (sub-lithographic, e.g., 0.1 μm or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.

Understanding semiconductor devices

Abstract: Part 1 Resistors: introduction to semiconductors the basics - resistor structure and drift current insight into conducitivity ingredients - chemical-bond model making a semiconductor resistor - lithography and diffusion carrier mobility energy-band model capacitors - reverse-biased P-N junction and MOS structure. Part 2 Basic applications: reverse-biased P-N junction $C$--$V$ dependence of the reverse-biased P-N junction - solving the Poisson equation SPICE parameters and their measurement metal-oxide-semiconductor (MOS) capacitor and thermal oxide. Part 3 Diodes: forward-biased P-N junction and metal-semiconductor contact rectifying diodes - fundamental effects and models SPICE models and parameters, stored charge capacitance, and temperature effects reference diodes - breakdown phenomena Schottky diodes - metal-semiconductor contact. Part 4 Basics of transistor applications: analog circuits digital circuits. Part 5 MOSFET: MOSFET principles MOSFET technologies MOSFET modelling SPICE parameters and parasitic elements. Part 6 BJT: BJT principles bipolar IC technologies BJT modelling SPICE parameters parasitic elements not included in device models. Part 7 advanced and specific IC devices and technologies: deep sub-micron MOSFET memory devices silicon-on-insulator (SOI) technology BICMOS technolgoy. Part 8 Photographic devices: light emitting diodes (LED) - carrier recombination photodetectors and solar cells - external carrier generation lasers. Part 9 Microwave FETs and diodes: gallium-arsenide versus silicon JFET MESFET HEMT negative resistance diodes. Part 10 Power devices: power devices in switch-mode power circuits power diodes power MOSFET IGBT thyristor. Part 11 Semiconductor device reliability basic reliability concepts failure mechanisms reliability screening reliability measurement. Part 12 Quantum mechanics: wave function Heisenberg uncertainty principle Schrodinger equation. Appendixes: basic integrated circuit concepts and economics crystal lattices, planes, and directions Hall effect and summary of kinetic phenomena summary of equations and key points list of Selected symbols answers to selected problems.

The ballistic nanotransistor: a simulation study

Abstract: The device design and physics issues of ballistic double-gate (DG) MOSFETs are explored using semiclassical and quantum simulations. We find that tunneling from source-to-drain increases the off-current but decreases the on-current for an L=10 nm model transistor. We also show that source-to-drain tunneling sets a scaling limit at less than about L=10 nm, but to achieve this limit, ultra-thin bodies are necessary to control classical two-dimensional short-channel effects. Finally, we show that to meet performance targets at low voltages, near-ballistic performance is necessary, and we estimate the mobility that will be required for these ultra-thin silicon films.

Simulation of Schottky barrier MOSFETs with a coupled quantum injection/Monte Carlo technique

Abstract: A full-band Monte Carlo device simulator has been used to analyze the performance of sub-0.1 /spl mu/m Schottky barrier MOSFETs. In these devices, the source and drain contacts are realized with metal silicide, and the injection of carriers is controlled by gate voltage modulation of tunneling through the source barrier. A simple model treating the silicide regions as metals, coupled with an Airy function approach for tunneling through the barrier, provides injecting boundary conditions for the Monte Carlo procedure. Simulations were carried out considering a p-channel device with 270 /spl Aring/ gate length for which measurements are available. Our results show that in these structures there is not a strong interaction with the oxide interface as in conventional MOS devices and carriers are injected at fairly wide angles from the source into the bulk of the device. The Monte Carlo simulations not only give good agreement with current-voltage (I-V) curves, but also easily reproduce the subthreshold behavior since all the computational power is devoted to simulation of channel particles. The simulations also clarify why these structures exhibit a large amount of leakage in subthreshold regime, due to both thermionic and tunneling emission. Computational experiments suggest ways to modify the doping profile to reduce to some extent the leakage.

MOSFET channel length: extraction and interpretation

Abstract: This paper focuses on MOSFET channel length: its definition, extraction, and physical interpretation. After a brief review of the objectives of channel length extraction and previous extraction methods, the principle and the algorithm of the latest "shift and ratio" (S&R) method are described. The S&R method allows the channel mobility to be an arbitrary function of gate voltage and, at the same time, provides a way to determine the threshold voltage of short-channel devices independent of their parasitic resistances. Accurate and consistent results are obtained from nMOSFET and pMOSFET data down to 0.05 /spl mu/m channel length. By applying the S&R method to model generated current-voltage (I-V) curves, it is shown that the extracted channel length should be interpreted in terms of the injection points where the MOSFET current spreads from the surface layer into the bulk source-drain region. This implies significant degradation of short-channel effects (SCE's) if the lateral source-drain doping gradient is not abrupt enough. Several remaining issues, including errors due to channel-length-dependent mobilities, difficulties with lightly-doped drain (LDD) MOSFET's, and interpretation of capacitance-voltage (C-V) extracted channel lengths, are discussed.