Showing papers on "MOSFET published in 2007"

Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking

Abstract: This paper presents a complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) as an extension to Part 1 of this two-part paper. For the first time, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE. In addition to the nonidealities included in the companion paper, this paper includes the elastic scattering in the channel region, the resistive source/drain (S/D), the Schottky-barrier resistance, and the parasitic gate capacitances. More than one nanotube per device can be modeled. Compared to silicon technology, the CNFETs show much better device performance based on the intrinsic gate-delay metric (six times for nFET and 14 times for pFET) than the MOSFET device at the 32-nm node, even with device nonidealities. This large speed improvement is significantly degraded (by a factor of five to eight) by interconnect capacitance in a real circuit environment. We performed circuit-performance comparison with all the standard digital library cells between CMOS random logic and CNFET random logic with HSPICE simulation. Compared to CMOS circuits, the CNFET circuits with one to ten carbon nanotubes per device is about two to ten times faster, the energy consumption per cycle is about seven to two times lower, and the energy-delay product is about 15-20 times lower, considering the realistic layout pattern and the interconnect wiring capacitance.

Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology

Abstract: Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current Isub, which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this paper, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65-nm technology. By benchmarking the prediction of circuit performance degradation with the measured ring oscillator data and simulations of an amplifier, we demonstrate that the proposed method very well predicts the degradation. For 65-nm technology, NBTI is the dominant reliability concern, and the impact of CHC on circuit performance is relatively small.

Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric

Abstract: In this paper, the length scaling of the silicon Double Gate Tunnel Field Effect Transistor (DG Tunnel FET) is studied. It is found that scaling limits are reached sooner by Tunnel FETs with an SiO 2 gate dielectric, while those with a high-K dielectric can be scaled further before threshold voltage, and average and point subthreshold swing are affected. It is demonstrated that the scaling of the high-K Tunnel FET is completely different than that of conventional MOS transistors. An outstanding feature of the Tunnel FET switch is that length scaling has a much weaker impact on device characteristics than does gate control (e.g. the use of a high-K dielectric), which primarily dictates the tunneling barrier width and consequently, device conduction. This paper demonstrates that while some improvements are observed, the length scaling does not dramatically affect switch figures of merit such as subthreshold slope, Ion and I off down to about 20 nm, and an optimized device design can be extended over a much larger window of sub-micron dimensions, compared to the MOSFET. A discussion of the length dependence of the transconductance, g m , and output conductance, g ds of the Tunnel FET is presented for the first time.

Performance Projections for Ballistic Graphene Nanoribbon Field-Effect Transistors

Abstract: The upper limit performance potential of ballistic carbon nanoribbon MOSFETs (CNR MOSFETs) is examined. Calculation of the bandstructure of nanoribbons using a single pz-orbital tight-binding method and evaluation of the current-voltage characteristics of a nanoribbon MOSFET were used in a semiclassical ballistic model. The authors find that semiconducting ribbons a few nanometers in width behave electronically in a manner similar to carbon nanotubes, achieving similar ON-current performance. The calculations show that semiconducting CNR transistors can be candidates for high-mobility digital switches, with the potential to outperform the silicon MOSFET. Although wide ribbons have small bandgaps, which would increase subthreshold leakage due to band to band tunneling, their ON-current capabilities could still be attractive for certain applications

A New Degradation Mechanism in High-Voltage SiC Power MOSFETs

Abstract: The phenomenon of recombination-induced stacking faults in high-voltage p-n diodes in SiC has been previously shown to increase the forward voltage drop due to reduction of minority carrier lifetime. In this paper, it has been shown that, for the first time, this effect is equally important in unipolar devices such as high-voltage MOSFETs. If the internal body diode is allowed to be forward biased during the operation of these devices, then the recombination-induced SFs will reduce the majority carrier conduction current and increase the leakage current in blocking mode. The effect is more noticeable in high-voltage devices where the drift layer is thick and is not expected to impact 600-1200-V devices.

Design of ion-implanted MOSFET's with very small physical dimensions

Abstract: This paper considers the design, fabrication, and characterization of very small MOSFET switching devices suitable for digital integrated circuits using dimensions of the order of 1μ. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation to proVide shallow source and drain regions and a nonuniform substrate doping profile. Onedimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFETs with channel lengths as short as 0.5μ were fabricated, and the device characteristics measured and compared with predicted values. Ibe performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected. Reprintedfrom the IEEE Journal of Solid-State Circuits, Vol. SC-9, October 1974, pp. 256-268.]

Suppression of Dynamic On-Resistance Increase and Gate Charge Measurements in High-Voltage GaN-HEMTs With Optimized Field-Plate Structure

Abstract: The dynamic on-resistance increase associated with the current collapse phenomena in high-voltage GaN high-electron-mobility transistors (HEMTs) has been suppressed by employing an optimized field-plate (FP) structure. The fabricated GaN-HEMTs of 600 V/4.7 A and 940 V/4.4 A for power-electronics applications employ a dual-FP structure consisting of a short-gate FP underneath a long-source FP. The measured on-resistance shows minimal increase during high-voltage switching due to increased electric-field uniformity between the gate and drain as a result of using the dual FP. The gate-drain charge Q gd for the fabricated devices has also been measured to provide a basis for discussion of the ability of high-speed switching operation. Although Q gd /A (A: active device area) was almost the same as that of the conventional Si-power MOSFETs, R on A was dramatically reduced to about a seventh of the reported 600-V Si-MOSFET value. Therefore, R on Q gd for 600-V device was reduced to 0.32 OmeganC, which was approximately a sixth of that for the Si-power MOSFETs. The high-voltage GaN-HEMTs have significant advantages over silicon-power MOSFETs in terms of both the reduced on-resistance and the high-speed switching capability.

NBTI-aware synthesis of digital circuits

Abstract: Negative bias temperature instability (NBTI) in PMOS transistors has become a major reliability concern in nanometer scale design, causing the temporal degradation of the threshold voltage of the PMOS transistors, and the delay of digital circuits. A novel method to characterize the delay of every gate in the standard cell library, as a function of the signal probability of each of its inputs, is developed. Accordingly, a technology mapping technique that incorporates the NBTI stress and recovery effects, in order to ensure optimal performance of the circuit, during its entire lifetime, is presented. Our technique, demonstrated over 65 nm benchmarks shows an average of 10 % area recovery, and 12 % power savings, as against a pessimistic method that assumes constant stress on all PMOS transistors in the design.

Silicon Carbide Power MOSFET Model and Parameter Extraction Sequence

Abstract: A compact circuit simulator model is used to describe the performance of a 2-kV, 5-A 4-H silicon carbide (SiC) power DiMOSFET and to perform a detailed comparison with the performance of a widely used 400-V, 5-A Si power MOSFET. The model's channel current expressions are unique in that they include the channel regions at the corners of the square or hexagonal cells that turn on at lower gate voltages and the enhanced linear region transconductance due to diffusion in the nonuniformly doped channel. It is shown that the model accurately describes the static and dynamic performance of both the Si and SiC devices and that the diffusion-enhanced channel conductance is essential to describe the SiC DiMOSFET on-state characteristics. The detailed device comparisons reveal that both the on-state performance and switching performance at 25degC are similar between the 400-V Si and 2-kV SiC MOSFETs, with the exception that the SiC device requires twice the gate drive voltage. The main difference between the devices is that the SiC has a five times higher voltage rating without an increase in the specific on-resistance. At higher temperatures (above 100degC), the Si device has a severe reduction in conduction capability, whereas the SiC on-resistance is only minimally affected

Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric

Abstract: In this paper, the length scaling of the silicon Double Gate Tunnel Field Effect Transistor (DG Tunnel FET) is studied. It is found that scaling limits are reached sooner by Tunnel FETs with an SiO2 gate dielectric, while those with a high-K dielectric can be scaled further before threshold voltage, and average and point subthreshold swing are affected. It is demonstrated that the scaling of the high-K Tunnel FET is completely different than that of conventional MOS transistors. An outstanding feature of the Tunnel FET switch is that length scaling has a much weaker impact on device characteristics than does gate control (e.g. the use of a high-K dielectric), which primarily dictates the tunneling barrier width and consequently, device conduction. This paper demonstrates that while some improvements are observed, the length scaling does not dramatically affect switch figures of merit such as subthreshold slope, Ion and Ioff down to about 20 nm, and an optimized device design can be extended over a much larger window of sub-micron dimensions, compared to the MOSFET. A discussion of the length dependence of the transconductance, gm, and output conductance, gds of the Tunnel FET is presented for the first time.

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited $\hbox{Al}_{2}\hbox{O}_{3}$ as Gate Dielectric

Abstract: High-performance inversion-type enhancement-mode n-channel In053Ga047As MOSFETs with atomic-layer-deposited (ALD) Al2O3 as gate dielectric are demonstrated The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general A 05-mum gate-length MOSFET with an Al2O3 gate oxide thickness of 8 nm shows a gate leakage current less than 10-4 A/cm2 at 3-V gate bias, a threshold voltage of 025 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V The midgap interface trap density of regrown Al2O3 on In053Ga047As is ~14 x 1012/cm2 ldr eV which is determined by low-and high-frequency capacitance-voltage method The peak effective mobility is ~1100 cm2 / V ldr s from dc measurement, ~2200 cm2/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 05-10-MV/cm effective electric field

Selective Formation of Silicon Carbon Epitaxial Layer

Abstract: Methods for formation of epitaxial layers containing n-doped silicon are disclosed, including methods for the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. Formation of the n-doped epitaxial layer involves exposing a substrate in a process chamber to deposition gases including a silicon source, a carbon source and an n-dopant source at a first temperature and pressure and then exposing the substrate to an etchant at a second higher temperature and a higher pressure than during deposition.

Enhancement-Mode GaAs MOSFETs With an $\hbox{In}_{0.3} \hbox{Ga}_{0.7}\hbox{As}$ Channel, a Mobility of Over 5000 $ \hbox{cm}^{2}/\hbox{V} \cdot \hbox{s}$ , and Transconductance of Over 475 $\mu\hbox{S}/\mu\hbox{m}$

Abstract: We present metal-gate high-k-dielectric enhancement-mode (e-mode) III-V MOSFETs with the highest reported effective mobility and transconductance to date. The devices employ a GaGdO high-k (k = 20) gate stack, a Pt gate, and a delta-doped InGaAs/AlGaAs/GaAs hetero-structure. Typical 1-mum gate length device figures of merit are given as follows: saturation drive current, Id,sat = 407 muA/mum; threshold voltage, Vt = +0.26 V; maximum extrinsic transconductance, gm = 477 muS/mum (the highest reported to date for a III-V MOSFET); gate leakage current, Ig = 30 pA; subthreshold swing, S = 102 mV/dec; on resistance, Ron = 1920 Omega-mum; Ion/Ioff ratio = 6.3 x 104; and output conductance, gd = 11 mS/mm. A peak electron mobility of 5230 cm2/V. s was extracted from low-drain-bias measurements of 20 mum long-channel devices, which, to the authors' best knowledge, is the highest mobility extracted from any e-mode MOSFET. These transport and device data are highly encouraging for future high-performance n-channel complementary metal-oxide-semiconductor solutions based on III-V MOSFETs.

Modeling of Surface-Roughness Scattering in Ultrathin-Body SOI MOSFETs

Abstract: A rigorous surface-roughness scattering model for ultrathin-body silicon-on-insulator (SOI) MOSFETs is derived, which reduces to Ando's model in the limit of bulk MOSFETs. The matrix element of the scattering potential reflects the fluctuations of both the wavefunction and the potential energy. The matrix element reflecting the fluctuation of the wavefunction is expressed in an integral form which can be considered as a generalized Prange-Nee term-to which it is equivalent in the limit of an infinitely high insulator-semiconductor barrier-giving more accurate results in the case of a finite barrier height. The matrix element reflecting the fluctuation of the potential energy is due to the Coulomb interactions originating from the roughness-induced fluctuation of the electron charge density, the interface polarization charge, and the image-charge density. The roughness-limited low-field electron mobility in thin-body SOI MOSFETs is obtained using the matrix elements that we have derived. We study its dependence on the silicon body thickness, effective field, and dielectric constant of the insulator.

Mosfet modeling for vlsi simulation: theory and practice

Abstract: Overview Review of Basic Semiconductor and pn Junction Theory MOS Transistor Structure and Operation MOS Capacitor Threshold Voltage MOSFET DC Model Dynamic Model Modeling Hot-Carrier Effects Data Acquisition and Model Parameter Measurements Model Parameter Extraction Using Optimization Method SPICE Diode and MOSFET Models and Their Parameters Statistical Modeling and Worst-Case Design Parameters

Scaling Behaviors of Graphene Nanoribbon FETs: A Three-Dimensional Quantum Simulation Study

Abstract: The scaling behaviors of graphene nanoribbon (GNR) Schottky barrier field-effect transistors (SBFETs) are studied by self-consistently solving the nonequilibrium Green's function transport equation in an atomistic basis set with a 3-D Poisson equation. The armchair edge GNR channel shares similarities with a zigzag carbon nanotube; however, it has a different geometry and quantum confinement boundary condition in the transverse direction. The results indicate that the I-V characteristics are ambipolar and strongly depend on the GNR width because the bandgap of the GNR is approximately inversely proportional to its width, which agrees with recent experiments. A multiple gate geometry improves immunity to short channel effects; however, it offers smaller improvement than it does for Si MOSFETs in terms of the on-current and transconductance. Reducing the oxide thickness is more useful for improving transistor performance than using a high-k gate insulator. Significant increase of the minimal leakage current is observed when the channel length is scaled below 10 nm because the small effective mass facilitates strong source-drain tunneling. The GNRFET, therefore, does not promise to extend the ultimate scaling limit of Si MOSFETs. The intrinsic switching speed of a GNR SBFET, however, is several times faster than that of Si MOSFETs, which could lead to promising high-speed electronics applications, where the large leakage of GNR SBFETs is of less concern.

Ballistic graphene nanoribbon metal-oxide-semiconductor field-effect transistors: A full real-space quantum transport simulation

Abstract: A real-space quantum transport simulator for graphene nanoribbon (GNR) metal-oxide-semiconductor field-effect transistors (MOSFETs) has been developed and used to examine the ballistic performance of GNR MOSFETs. This study focuses on the impact of quantum effects on these devices and on the effect of different type of contacts. We found that two-dimensional (2D) semi-infinite graphene contacts produce metal-induced-gap states (MIGS) in the GNR channel. These states enhance quantum tunneling, particularly in short channel devices, they cause Fermi level pinning and degrade the device performance in both the ON-state and OFF-state. Devices with infinitely long contacts having the same width as the channel do not indicate MIGS. Even without MIGS quantum tunneling effects such as band-to-band tunneling still play an important role in the device characteristics and dominate the OFF-state current. This is accurately captured in our nonequilibrium Greens’ function quantum simulations. We show that both narrow (...

CMOS logic design with independent-gate FinFETs

Abstract: Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano-scale circuits. In this paper, it is observed that in spite of improved device characteristics, high active leakage may remain a problem for FinFET logic circuits. Leakage is found to contribute 31.3% of total power consumption in power-optimized FinFET logic circuits. Various FinFET logic design styles, based on independent control of FinFET gates, are studied. A new low-leakage logic style is presented. Leakage (total) power savings of 64.7% (14.5%) under tight delay constraints and 91.2% (37.2%) under relaxed delay constraints, through the judicious use of FinFET logic styles, are demonstrated.

Poly-Si-Gate-Related Variability in Decananometer MOSFETs With Conventional Architecture

Abstract: In this paper, we present a comprehensive statistical 3-D simulation study of the effect of polysilicon (poly-Si) gate granularity on the threshold voltage variability in decananometer MOSFETs with conventional (bulk) architecture. Initially, the effect of both the pinning of the Fermi level and the doping nonuniformity at the poly-Si grain boundaries are studied and compared considering a single grain boundary crossing through the middle of the channel for different pinning positions and doping concentrations at the boundary. This is followed by systematic simulation results for the impact of the grain-size distribution on the standard deviation of the threshold voltage in a simple 30 30 nm MOSFET with uniform channel doping for different pinning positions and doping levels at the grain boundaries. Finally, simulation results for the magnitude of the threshold voltage variations induced by the poly-Si granularity are presented for a set of carefully scaled ldquorealisticrdquo bulk MOSFETs with gate lengths of 35, 25, 18, 13, and 9 nm and are compared with the variations introduced by random discrete dopants and line-edge roughness.

Analytical Model of the Threshold Voltage and Subthreshold Swing of Undoped Cylindrical Gate-All-Around-Based MOSFETs

Abstract: Analytical physically based models for the threshold voltage, subthreshold swing, and drain-induced barrier lowering (DIBL) of undoped cylindrical gate-all-around MOSFETs have been derived based on an analytical solution of 2-D Poisson's equation (in cylindrical coordinates) in which the mobile charge term has been included. Using the new model, threshold voltage, DIBL and subthreshold swing sensitivities to channel length, and channel thickness have been investigated. The models for DIBL, subthreshold swing, and threshold voltage rolloff parameters have been verified by comparison with 3-D numerical simulations; close agreement with the numerical simulations has been observed

Effect of Edge Roughness on Electronic Transport in Graphene Nanoribbon Channel Metal Oxide Semiconductor Field-Effect Transistors

Abstract: Results of quantum mechanical simulations of the influence of edge disorder on transport in graphene nanoribbon metal oxide semiconductor field-effect transistors (MOSFETs) are reported. The addition of edge disorder significantly reduces ON-state currents and increases OFF-state currents, and introduces wide variability across devices. These effects decrease as ribbon widths increase and as edges become smoother. However the bandgap decreases with increasing width, thereby increasing the band-to-band tunneling mediated subthreshold leakage current even with perfect nanoribbons. These results suggest that without atomically precise edge control during fabrication, MOSFET performance gains through use of graphene will be difficult to achieve.

Ultra-Compact High-Linearity High-Power Fully Integrated DC–20-GHz 0.18- $\mu{\hbox {m}}$ CMOS T/R Switch

Abstract: A fully integrated ultra-broadband transmit/receive (T/R) switch has been developed using nMOS transistors with a deep n-well in a standard 0.18-mum CMOS process, and demonstrates unprecedented insertion loss, isolation, power handling, and linearity. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET's parasitic capacitances to synthesize artificial transmission lines, which result in low insertion loss over an extremely wide bandwidth. Negative bias to the bulk or positive bias to the drain of the MOSFET devices with floating bulk is used to reduce effects of the parasitic diodes, leading to enhanced linearity and power handling for the switch. Within dc-10, 10-18, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0, and 2.5 dB and isolation between 32-60, 25-32, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. The new CMOS T/R switch has a die area of only 230 mumtimes250 mum. The achieved ultra-broadband performance and high power-handling capability, approaching those achieved in GaAs-based T/R switches, along with the full-integration ability confirm the usefulness of switches in CMOS technology, and demonstrate their great potential for many broadband CMOS radar and communication applications

Ultra-thin fully-depleted SOI MOSFETs: Special charge properties and coupling effects

Abstract: A standard characterization method in fully depleted SOI devices consists in biasing the back interface in the accumulation regime, and measuring the front-channel properties. In ultra thin body device however, it is sometimes no longer possible to achieve such an accumulation regime at the back interface. This unusual effect is investigated by detailed simulations and analytical modelling of the potential and electron/hole concentrations. The enhancement of the interface coupling effect in ultra thin body devices, called super-coupling, can explain previously published experimental data [Pretet J, Ohata A, Dieudonne F, Allibert F, Bresson N, Matsumoto T, et al. Scaling issues for advanced SOI devices: gate oxide tunneling, thin buried oxide, and ultra-thin films. In: 7th International symposium silicon nitride and silicon dioxide thin insulating films, Paris, France, 2003. Electrochemical Society Proceedings, vol. 2003-02, Pennington (USA); 2003. p. 476–87], and reveals new challenges in the characterization of advanced SOI devices.

A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs

Abstract: In this paper, we review the compact-modeling framework for undoped double-gate (DG) silicon-on-insulator (SOI) MOSFETs. The use of multiple gates has emerged as a new technology to possibly replace the conventional planar MOSFET when its feature size is scaled to the sub-50-nm regime. MOSFET technology has been the choice for mainstream digital circuits for very large scale integration as well as for other high-frequency applications in the low-gigahertz range. But the continuing scaling of MOSFET presents many challenges, and multiple-gate, particularly DG, SOI devices seem to be attractive alternatives as they can effectively reduce the short-channel effects and yield higher current drive. Core compact models, including the analysis for surface potential and drain-current, for both the symmetric and asymmetric DG SOI MOSFETs, are discussed and compared. Numerical simulations are also included in order to assess the validity of the models reviewed

MOS-Based Spin Devices for Reconfigurable Logic

Abstract: Semiconductor-based spin transistors are expected to give a new spin degree of freedom in future electronics. While many different spin transistors have been proposed and studied, the spin MOSFET is one of the most promising devices, because it can have spin-dependent output characteristics, transistor functions, and good compatibility with existing silicon technology. The device concept, structures of various types of spin MOSFETs, operation principles, calculated output characteristics, and applications was reviewed. It is shown that the output characteristics of the spin MOSFETs depend on the relative magnetization configuration of the two ferromagnetic layers in the device, that is, high current-drive capability in parallel magnetization and low current-drive capability in antiparallel magnetization. Furthermore, nonvolatile memory and reconfigurable logic gates was presented using spin MOSFETs, where the logic functions can be changed by switching their magnetization configurations. Circuit design and numerical simulations of reconfigurable gates for NAND/NOR, AND/OR, and all symmetric Boolean functions was shown

A New Resonant Gate Drive Circuit for Synchronous Buck Converter

Abstract: This paper proposes a new resonant gate drive circuit for driving both the control metal oxide semiconductor field effect transistor (MOSFET) and synchronous MOSFET in a synchronous buck converter. The circuit can recover more than 70% of the conventional gate drive loss. More importantly, the driving circuit can also reduce the switching loss. It charges and discharges the gate of MOSFET at a constant current during switching interval. Other advantages of the proposed circuit include better noise immunity for dv/dt turn on, less sensitive to parasitic track inductance. The experimental prototype shows that the loss reduction is 10% of the output power for 12 V input, 1.5 V/15 A output with switching frequency of 1 MHz.

Device design guidelines for nano-scale MuGFETs

Abstract: The short-channel properties of multi-gate SOI MOSFETs (MuGFETs) are studied by numerical simulation. The evolution of characteristics such as DIBL, subthreshold slope, and threshold voltage roll-off is analyzed as a function of channel length, silicon film or fin thickness, gate dielectric thickness and dielectric constant, and as a function of the radius of curvature of the corners. The notion of an equivalent gate number is introduced. This number ranges from 2 for a double-gate device to 4 in a gate-all-around transistor. The equivalent gate number can be used in general equations to predict the absence or presence of short-channel effects. As a general rule, increasing the equivalent gate number improves the short-channel behavior of the devices. Similarly, increasing the radius of curvature of the corners improves the control of the channel region by the gate.