Showing papers on "MOSFET published in 2008"
TL;DR: In this article, the authors reviewed the recent approaches in realizing carrier-transport-enhanced CMOS, and the critical issues, fabrication techniques, and device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented.
Abstract: An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.
337 citations
TL;DR: In this article, a 20-kHz 370-W dc/dc boost converter based on a 10-kV 4H-SiC DMOSFET and diodes is designed and experimentally demonstrated.
Abstract: Ten-kilovolt SiC MOSFETs are currently under development by a number of organizations in the United States, with the aim of enabling their applications in high-voltage high-frequency power conversions. The aim of this paper is to obtain the key device characteristics of SiC MOSFETs so that their realistic application prospect can be provided. In particular, the emphasis is on obtaining their losses in various operation conditions from the extensive characterization study and a proposed behavioral SPICE model. Using the validated MOSFET SPICE model, a 20-kHz 370-W dc/dc boost converter based on a 10-kV 4H-SiC DMOSFET and diodes is designed and experimentally demonstrated. In the steady state of the boost converter, the total power loss in the 15.45-mm2 SiC MOSFET is 23.6 W for the input power of 428 W. The characterization study of the experimental SiC MOSFET and the experiment of the SiC MOSFET-based boost converter indicate that the turn-on losses of SiC MOSFETs are the dominant factors in determining their maximum operation frequency in hard-switched circuits with conventional thermal management. Replacing a 10-kV SiC PiN diode with a 10-kV SiC JBS diode as a boost diode and using a small external gate resistor, the turn-on loss of the SiC MOSFET can be reduced, and the 10-kV 5-A SiC MOSFET-based boost converter is predicted to be capable of a 20-kHz operation with a 5-kV dc output voltage and a 1.25-kW output power by the PSpice simulation with the MOSFET model. The low losses and fast switching speed of 10-kV SiC MOSFETs shown in the characterization study and the preliminary demonstration of the boost converter make them attractive in high-frequency high-voltage power-conversion applications.
329 citations
TL;DR: In this article, a 0.4mum gate-length MOSFET with an Al2O3 gate oxide thickness of 10 nm shows a gate leakage current that is less than 5 times 10-6 A/cm2 at 4.0 V.
Abstract: High-performance inversion-type enhancement- mode (E-mode) n-channel In0.65Ga0.35As MOSFETs with atomic-layer-deposited Al2O3 as gate dielectric are demonstrated. A 0.4-mum gate-length MOSFET with an Al2O3 gate oxide thickness of 10 nm shows a gate leakage current that is less than 5 times 10-6 A/cm2 at 4.0-V gate bias, a threshold voltage of 0.4 V, a maximum drain current of 1.05 A/mm, and a transconductance of 350 mS/mm at drain voltage of 2.0 V. The maximum drain current and transconductance scale linearly from 40 mum to 0.7 mum. The peak effective mobility is ~1550 cm2/V ldr s at 0.3 MV/cm and decreases to ~650 cm2/V ldr s at 0.9 MV/cm. The obtained maximum drain current and transconductance are all record-high values in 40 years of E-mode III-V MOSFET research.
305 citations
TL;DR: In this article, the authors proposed a novel tunnel source (PNPN) n-MOSFET based on the principle of band-to-band tunneling, which has the potential of steep subthreshold swing and improved Ion in addition to immunities against SCEs.
Abstract: As MOSFET is scaled below 90 nm, many daunting challenges arise. Short-channel effects (SCEs; drain-induced barrier lowering and VTHmiddotrolloff), off-state leakage, parasitic capacitance, and resistance severely limit the performance of these transistors. New device innovations are essential to overcome these difficulties. In this paper, we propose the concept of a novel tunnel source (PNPN) n-MOSFET based on the principle of band-to- band tunneling. It is found that the PNPN n-MOSFET has the potential of steep subthreshold swing and improved Ion in addition to immunities against SCEs. Therefore, such a PNPN n-MOSFET can overcome the ever-degrading on-off characteristics of the deeply scaled conventional MOSFET. The design of the PNPN n-MOSFET was extensively examined using simulations. Devices with source-side tunneling junctions were fabricated on bulk substrates using spike anneal, and the experimental data is presented.
299 citations
TL;DR: In this article, the authors observed significant instability in the threshold voltage of 4H-SiC metal-oxide-semiconductor field effect transistors due to gate-bias stressing.
Abstract: We have observed significant instability in the threshold voltage of 4H-SiC metal-oxide-semiconductor field-effect transistors due to gate-bias stressing. This effect has a strong measurement time dependence. For example, a 20-mus-long gate ramp used to measure the I-V characteristic and extract a threshold voltage was found to result in a instability three to four times greater than that measured with a 1-s-long gate ramp. The VT instability was three times greater in devices that did not receive a NO postoxidation anneal compared with those that did. This instability effect is consistent with electrons directly tunneling in and out of near-interfacial oxide traps, which in irradiated Si MOS was attributed to border traps.
285 citations
17 Jun 2008
TL;DR: In this article, two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper.
Abstract: Two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper. The first feature is the integration of stress-enhancement techniques with the dual metal-gate + high-k transistors. The second feature is the extension of 193 nm dry lithography to the 45 nm technology node pitches. Use of these features has enabled industry-leading transistor performance and the first high volume 45 nm high-k + metal gate technology.
266 citations
TL;DR: In this paper, a non-local quantum tunneling model was used to compare the performance of HTFETs to MOSFET with similar technology parameters and the simulations showed that the potential for low-operating-voltage (Vdd < 0.5 V) application and exhibit steep subthreshold swing over many decades while maintaining high ON-state currents.
Abstract: Heterojunction tunneling field-effect transistors (HTFETs) that use strained-silicon/strained-germanium type-II staggered band alignment for band-to-band tunneling (BBT) injection are simulated using a nonlocal quantum tunneling model. The tunneling model is first compared to measurements of gate- controlled BBT in previously fabricated strained SiGe diodes and is shown to produce good agreement with the measurements. The simulation of the gated diode structure is then extended to study HTFETs with an effective energy barrier of 0.25 eV at the strained-Si/strained-Ge heterointerface. As the band alignment, particularly the valence band offset, is critical to modeling HTFET operation, analysis of measured characteristics of MOS capacitors fabricated in strained-Si/strained-Ge/relaxed Si0.5Ge0.5 hetero- junctions is used to extract a valence band offset of 0.64 eV at the strained-Si/strained-Ge heterointerface. Simulations are used to compare HTFETs to MOSFETs with similar technology parameters. The simulations show that HTFETs have potential for low-operating-voltage (Vdd < 0.5 V) application and exhibit steep subthreshold swing over many decades while maintaining high ON-state currents.
262 citations
TL;DR: In this article, thin, strained epi-Si is examined as a passivation of the Ge/gate dielectric interface, with an optimized thickness found at 6 monolayers.
Abstract: 7cm 2 ; however, only a 2 times reduction in junction leakage is observed and no benefit is seen in on-state current. Ge wet etch rates are reported in a variety of acidic, basic, oxidizing, and organic solutions, and modifications of the RCA clean suitable for Ge are discussed. Thin, strained epi-Si is examined as a passivation of the Ge/gate dielectric interface, with an optimized thickness found at 6 monolayers. Dopant species are overviewed. P and As halos are compared, with better short channel control observed for As. Area leakage currents are presented for p/n diodes, with the n-doping level varied over the range relevant for pMOS. Germanide options are discussed, with NiGe showing the most promise. A defect mode for NiGe is reported, along with a fix involving two anneal steps. Finally, the benefit of an end-of-process H2 anneal for device performance is shown.
242 citations
TL;DR: In this article, a graphene nanoribbon (GNR) tunnel field effect transistor (TFET) was proposed and modeled analytically, and it was shown that a 5-nm ribbon width TFET can switch from on to off with only 0.1-V gate swing.
Abstract: A graphene nanoribbon (GNR) tunnel field-effect transistor (TFET) is proposed and modeled analytically. Ribbon widths between 3 and 10 nm are considered to effect energy bandgaps in the range of 0.46 to 0.14 eV. It is shown that a 5-nm ribbon width TFET can switch from on to off with only 0.1-V gate swing. The transistor achieves 800 muA/mum on -state current and 26 pA/mum off-state current, with an effective subthreshold swing of 0.19 mV/dec. Compared to a projected 2009 n MOSFET, the GNR TFET can provide 5times higher speed, 20times lower dynamic power, and 280 000times lower off-state power dissipation. The high performance of GNR TFETs results from their narrow bandgaps and their 1-D nature.
236 citations
Patent•
IBM1
TL;DR: In this article, a high-k gate dielectric/metal gate MOSFET with a reduced parasitic capacitance is presented, where the gate spacer is located upon an upper surface of both the gate and the highk gate.
Abstract: The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) 100 located on a surface of a semiconductor substrate 12. The least one MOSFET 100 includes a gate stack including, from bottom to top, a high-k gate dielectric 28 and a metal-containing gate conductor 30. The metal- containing gate conductor 30 has gate corners 31 located at a base segment of the metal- containing gate conductor. Moreover, the metal-containing gate conductor 30 has vertically sidewalls 102A and 102B devoid of the high-k gate dielectric 28 except at the gate corners 31. A gate dielectric 18 laterally abuts the high-k gate dielectric 28 present at the gate corners 31 and a gate spacer 36 laterally abuts the metal-containing gate conductor 30. The gate spacer 36 is located upon an upper surface of both the gate dielectric 18 and the high-k gate dielectric that is present at the gate corners 31.
231 citations
TL;DR: In this paper, the authors presented a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology, which achieved high aspect ratio (up to 50: 1) vertical nanowires with diameter ~20 nm.
Abstract: This letter presents a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50: 1) vertical nanowires with diameter ~20 nm are achieved from lithography and dry-etch defined Si-pillars with subsequent oxidation. The surrounding gate length is controlled using etch back of the sacrificial oxide. N-MOS devices thus fabricated with gate length ~150 nm showed excellent transistor characteristics with large drive current (1.0 times 103 muA/mum), high Ion/Ioff ratio (~107), good subthreshold slope (~80 mV/dec) and low drain-induced barrier lowering (~10 mV/V). Along with good electrical characteristics, the use of low cost bulk wafers, and simple gate definition process steps could make this device a suitable candidate for next generation technology nodes.
TL;DR: In this article, a novel method for fabricating trench structures on GaN was developed and a smooth non-polar (1100) plane was obtained by wet etching using tetramethylammonium hydroxide (TMAH) as the etchant.
Abstract: A novel method for fabricating trench structures on GaN was developed. A smooth non-polar (1100) plane was obtained by wet etching using tetramethylammonium hydroxide (TMAH) as the etchant. A U-shape trench with the (1100) plane side walls was formed with dry etching and the TMAH wet etching. A U-shape trench gate metal oxide semiconductor field-effect transistor (MOSFET) was also fabricated using the novel etching technology. This device has the excellent normally-off operation of drain current–gate voltage characteristics with the threshold voltage of 10 V. The drain breakdown voltage of 180 V was obtained. The results indicate that the trench gate structure can be applied to GaN-based transistors.
TL;DR: In this paper, complete vertical trench gate metal oxide semiconductor field effect transistors (MOSFETs) have been produced using gallium nitride (GaN) for the first time.
Abstract: Completely vertical trench gate metal oxide semiconductor field-effect transistors (MOSFETs) have been produced using gallium nitride (GaN) for the first time. These MOSFETs exhibited enhancement-mode operation with a threshold voltage of 3.7 V and an on-resistance of 9.3 mΩcm2. The channel mobility was estimated to be 131 cm2/(Vs) when all the resistances except for that of the channel are considered. Such structures, which satisfy the key words "vertical", "trench gate", and "MOSFET", will enable us to fabricate practical GaN-based power switching devices.
01 Dec 2008
TL;DR: In this paper, a high-speed and low-power III-V p-channel QWFET using a compressively strained InSb QW structure is described, achieving peak transconductance (Gm) of 510 muS/mum and cut-off frequency (fT) of 140 GHz at supply voltage of 0.5V.
Abstract: This paper describes for the first time, a high-speed and low-power III-V p-channel QWFET using a compressively strained InSb QW structure. The InSb p-channel QW device structure, grown using solid source MBE, demonstrates a high hole mobility of 1,230 cm2/V-s. The shortest 40 nm gate length (LG) transistors achieve peak transconductance (Gm) of 510 muS/mum and cut-off frequency (fT) of 140 GHz at supply voltage of 0.5V. These represent the highest Gm and fT ever reported for III-V p-channel FETs. In addition, effective hole velocity of this device has been measured and compared to that of the standard strained Si p-channel MOSFET.
TL;DR: In this article, the issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metrics are presented to manage their severe degradation.
Abstract: Minimum energy operation for digital circuits typically requires scaling the power supply below the device threshold voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-Vt circuits, but are plagued by increased variation and reduced ION/IOFF ratios, which degrade the fundamental device characteristics critical to circuit operation by several orders of magnitude. This paper investigates those characteristics and presents design methodologies and circuit topologies to manage their severe degradation. The issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metrics are presented.
TL;DR: In this paper, the InxGa1 - xAs-source silicon-TFET was proposed to boost the on-current of the all-silicon p-FET, a necessity for making an inverter and competing with the MOSFET.
Abstract: As a solution to the low on-current of silicon-based tunnel-FETs (TFETs), the source material of the n-channel TFET is replaced with the small-bandgap material germanium, which results in a current boost up to the same level as the current of MOSFETs. However, no solution has been reported to boost the on-current of the all-silicon p-TFET, a necessity for making an inverter and competing with the MOSFET. We have investigated the heterostructure TFET with respect to complementarity based on our semi-analytical model, and we propose the InxGa1 - xAs-source silicon-TFET as p-TFET. This design is particularly applicable to nanowire-based transistor architectures. We discuss the complementarity of the I-V curves, and we analyze the threshold voltage behavior of the complementary TFETs.
Patent•
17 Apr 2008TL;DR: In this article, a measurement element for a monitor provided in the semiconductor integrated circuit device has a local variation, and the measurement element selects part 103A for the monitor in a monitor circuit 105A.
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which can achieve an increase of an operating speed and a low power consumption even when a measurement element for a monitor provided in the semiconductor integrated circuit device has a local variation. SOLUTION: A MOSFET 101A for the monitor is selected from a MOSFET group 102A by a measurement element select part 103A for the monitor in a monitor circuit 105A. Here, a value of a drain current at an arbitrary gate voltage value in a sub-threshold region or saturated region of each MOSFET of the MOSFET group 102A is measured as a measurement parameter, and the MOSFET in which a value of the drain current is a central value is selected as the MOSFET 101A for the monitor. Thereafter, a board voltage 108 of a board is adjusted by an operating parameter adjusting circuit 107 based on a drain current value 104A of the MOSFET 101A for the monitor selected by the monitor circuit 105A, and the board voltage 108 is supplied to an integrated circuit body 106A. COPYRIGHT: (C)2008,JPO&INPIT
TL;DR: In this article, a single-electron ratchet with an asymmetric potential with a pocket that captures single electrons from the source and ejects them to the drain is presented.
Abstract: Nanoampere single-electron pumping is presented at 20K using a single-electron ratchet comprising silicon nanowire metal-oxide-semiconductor field-effect transistors. The ratchet features an asymmetric potential with a pocket that captures single electrons from the source and ejects them to the drain. Directional single-electron transfer is achieved by applying one ac signal with the frequency up to 2.3GHz. We find anomalous shapes of current steps which can be ascribed to nonadiabatic electron capture.
01 Dec 2008
TL;DR: In this paper, the authors investigated the sources responsible for local and inter-die threshold voltage variability in undoped ultra-thin FDSOI MOSFETs with a high-k/metal gate stack.
Abstract: Sources responsible for local and inter-die threshold voltage (Vt) variability in undoped ultra-thin FDSOI MOSFETs with a high-k/metal gate stack are experimentally discriminated for the first time. Charges in the gate dielectric and/or TiN gate workfunction fluctuations are determined as major contributors to the local Vt variability and it is found that SOI thickness (TSi) variations have a negligible impact down to TSi=7 nm. Moreover, TSi scaling is shown to limit both local and inter-die Vt variability induced by gate length fluctuations. The highest matching performance ever reported for 25 nm gate length MOSFETs is achieved (AVt=0.95 mV.mum), demonstrating the effectiveness of the undoped ultra-thin FDSOI architecture in terms of Vt variability control.
TL;DR: In this article, a comprehensive physical model for the analysis, characterization, and design of 4H-silicon carbide (SiC) MOSFETs has been developed.
Abstract: A comprehensive physical model for the analysis, characterization, and design of 4H-silicon carbide (SiC) MOSFETs has been developed. The model has been verified for an extensive range of bias conditions and temperatures. It incorporates details of interface trap densities, Coulombic interface trap scattering, surface roughness scattering, phonon scattering, velocity saturation, and their dependences on bias and temperature. The physics-based models were implemented into our device simulator that is tailored for 4H-SiC MOSFET analysis. By using a methodology of numerical modeling, simulation, and close correlation with experimental data, values for various physical parameters governing the operation of 4H-SiC MOSFETs, including the temperature-dependent interface trap density of states, the root-mean-square height and correlation length of the surface roughness, and the electron saturation velocity in the channel and its dependence on temperature, have been extracted. Coulomb scattering and surface roughness scattering limit surface mobility for a wide range of temperatures in the subthreshold and linear regions of device operation, whereas the saturation velocity and the high-field mobility limit current in the saturation region.
TL;DR: In this article, an atomistic 3D simulation study of the performance of graphene-nanoribbon (GNR) Schottky-barrier field effect transistors and transistors with doped reservoirs (MOSFETs) was presented.
Abstract: We present an atomistic 3-D simulation study of the performance of graphene-nanoribbon (GNR) Schottky-barrier field-effect transistors (SBFETs) and transistors with doped reservoirs (MOSFETs) by means of the self-consistent solution of the Poisson and Schrodinger equations within the nonequilibrium Green's function (NEGF) formalism Ideal MOSFETs show slightly better electrical performance for both digital and terahertz applications The impact of nonidealities on device performance has been investigated, taking into account the presence of single vacancy, edge roughness, and ionized impurities along the channel In general, MOSFETs show more robust characteristics than SBFETs Edge roughness and single-vacancy defect largely affect the performance of both device types
01 Dec 2008
TL;DR: In this article, it was shown that by integrating a thin ferroelectric layer into a gate stack of a standard MOS transistor one, it is possible to overcome the 60 mV/decade sub-threshold swing limit at room temperature of MOSFETs.
Abstract: This work experimentally demonstrates, for the first time, that by integrating a thin ferroelectric layer into a gate stack of a standard MOS transistor one, it is possible to overcome the 60 mV/decade subthreshold swing limit at room temperature of MOSFET. We find sub-threshold swings as low as 13 mV/decade in Fe-FETs with 40 nm P(VDF-TrFE)/SiO2 gate stack. The mechanism governing the low subthreshold swing in Fe-FET transistors is the negative capacitance of the ferroelectric layer that provides voltage amplification; with our particular ferroelectric gate stack we report for the first time negative capacitance at room temperature.
TL;DR: In this paper, the influence of edge disorder on transport in graphene nanoribbon metal-oxide-semiconductor field effect transistors (MOSFETs) is reported.
Abstract: Results of quantum mechanical simulations of the influence of edge disorder on transport in graphene nanoribbon metal-oxide-semiconductor field-effect transistors (MOSFETs) are reported. The addition of edge disorder significantly reduces ON-state currents and increases OFF-state currents, and introduces wide variability across devices. These effects decrease as ribbon widths increase and as edges become smoother. However, the band gap decreases with increasing width, thereby increasing the band-to-band tunneling mediated subthreshold leakage current even with perfect nanoribbons. These results suggest that without atomically precise edge control during fabrication, MOSFET performance gains through use of graphene will be difficult to achieve in complementary MOS applications.
TL;DR: In this article, a 2-D drift-diffusion electrothermal simulation, using an electron transport model calibrated against Monte Carlo simulations at various temperatures, is employed to analyze the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs.
Abstract: This paper discusses self-heating (SHE) effects in silicon-on-insulator (SOI) CMOS technology and applies device simulation to analyze the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs A 2-D drift-diffusion electrothermal simulation, using an electron transport model calibrated against Monte Carlo simulations at various temperatures, is employed in the analysis We report the effects of device-structure parameters, such as SOI layer thickness, buried-oxide (BOX) thickness, source/drain (S/D) extension length, and thickness of the elevated S/D region, on the SHE of nanoscale MOSFETs The SHE effects become significant due to the adoption of thin silicon layers and to the low thermal conductivity of the BOX, leading to the rise of large temperature under nominal operation conditions for high-performance digital circuits The ac performance of SOI MOSFETs is influenced as well, and in particular, a severe degradation of the cutoff frequency of very short MOSFETs is predicted by numerical electrothermal device simulations Although the effects of SHE on device performance are found to be somewhat modest and might be mitigated through device design, they may result in a degradation of the long-term reliability
TL;DR: In this article, a stack gate HfO2/Al2O3 structure grown by atomic layer deposition was used for high-electron mobility transistors with 1- mum gate lengths.
Abstract: We have developed a novel AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor using a stack gate HfO2/Al2O3 structure grown by atomic layer deposition. The stack gate consists of a thin HfO2 (30-A) gate dielectric and a thin Al2O3 (20- A) interfacial passivation layer (IPL). For the 50-A stack gate, no measurable C-V hysteresis and a smaller threshold voltage shift were observed, indicating that a high-quality interface can be achieved using a Al2O3 IPL on an AlGaN substrate. Good surface passivation effects of the Al2O3 IPL have also been confirmed by pulsed gate measurements. Devices with 1- mum gate lengths exhibit a cutoff frequency (fT) of 12 GHz and a maximum frequency of oscillation (f MAX) of 34 GHz, as well as a maximum drain current of 800 mA/mm and a peak transconductance of 150 mS/mm, whereas the gate leakage current is at least six orders of magnitude lower than that of the reference high-electron mobility transistors at a positive gate bias.
01 Dec 2008
TL;DR: In this paper, a 3D stacked sub-15 nm diameter NanoWire FinFET-like CMOS technology (3D-NWFET) with a new optional independent gate nanowire structure named PhiFET is reported.
Abstract: For the first time, we report a 3D stacked sub-15 nm diameter NanoWire FinFET-like CMOS technology (3D-NWFET) with a new optional independent gate nanowire structure named PhiFET. Extremely high driving currents for 3D-NWFET (6.5 mA/mum for NMOS and 3.3 mA/mum for PMOS) are demonstrated thanks to the 3D configuration using a high-k/metal gate stack. Co-processed reference FinFETs with fin widths down to 6 nm are achieved with record aspect ratios of 23. We show experimentally that the 3D-NWFET, compared to a co-processed FinFET, relaxes by a factor of 2.5 the channel width requirement for a targeted DIBL and improves transport properties. PhiFET exhibits significant performance boosts compared to Independent-Gate FinFET (IG-FinFET): a 2-decade smaller IOFF current and a lower subthreshold slope (82 mV/dec. instead of 95 mV/dec.). This highlights the better scalability of 3D-NWFET and PhiFET compared to FinFET and IG-FinFET, respectively.
TL;DR: In this paper, a self-aligned inversion-channel In0.53Ga0.47 MOSFET with gate dielectric of Al2O3(2nmthick)∕GGO(5 nmthick), a maximum drain current of 1.05A∕mm, a transconductance of 714mS∕m, and a peak mobility of 1300cm2∕Vs have been achieved, the highest ever reported for III-V inversion channel devices of 1μm gate length.
Abstract: Self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effect transistors (MOSFETs) using ultrahigh-vacuum deposited Al2O3∕Ga2O3(Gd2O3) (GGO) dual-layer dielectrics and a TiN metal gate were fabricated. For a In0.53Ga0.47As MOSFET using a gate dielectric of Al2O3(2nmthick)∕GGO(5nmthick), a maximum drain current of 1.05A∕mm, a transconductance of 714mS∕mm, and a peak mobility of 1300cm2∕Vs have been achieved, the highest ever reported for III-V inversion-channel devices of 1μm gate length.
TL;DR: In this article, double-gated field effect transistors manufactured from monolayer graphene are investigated and the carrier mobility of single-and doublegated graphene FETs are compared.
Abstract: In this work, double-gated field effect transistors manufactured from monolayer graphene are investigated. Conventional top–down CMOS-compatible processes are applied except for graphene deposition by manual exfoliation. Carrier mobilities in single- and double-gated graphene field effect transistors are compared. Even in double-gated graphene FETs, the carrier mobility exceeds the universal mobility of silicon over nearly the entire measured range. At comparable dimensions, reported mobilities for ultra-thin body silicon-on-insulator MOSFETs cannot compete with graphene FET values.
TL;DR: In this article, a physical model involving fast transient charge trapping and detrapping at and near the SiC/SiO2 interface is proposed to reveal the full extent of the instability underestimated by dc measurements.
Abstract: Threshold voltage and drain current instabilities in state-of-the-art 4H-SiC MOSFETs with thermal as-grown SiO2 and NO-annealed gate oxides have been studied using fast I-V measurements. These measurements reveal the full extent of the instability underestimated by dc measurements. Furthermore, fast measurements allow the separation of negative and positive bias stress effects. Postoxidation annealing in NO was found to passivate the oxide traps and dramatically reduce the instability. A physical model involving fast transient charge trapping and detrapping at and near the SiC/SiO2 interface is proposed.
16 May 2008
TL;DR: In this article, a dual active bridge, which can transfer 25 kW bidirectionally between a 5 kV and a 700 V dc bus at a switching frequency of 50 kHz, is presented.
Abstract: In the area of power electronics there is a general trend to higher power densities and efficiency. In order to continue this trend new devices, which enable high switching frequencies at higher power levels or show reduced losses at moderate switching frequencies are required. High voltage switches based on a series connection of SiC JFETs and one MOSFET in cascode connection meet these demands. For investigating the performance of the SiC based switch and its influence on the power density/efficiency a dual active bridge, which could transfer 25 kW bidirectionally between a 5 kV and a 700 V dc bus at a switching frequency of 50 kHz, is presented in this paper. There, especially the design of the high voltage/high frequency transformer and the switching as well as the static behaviour of the SiC switch is investigated in detail by simulations and experimental results in this paper.