Showing papers on "MOSFET published in 2009"

Junctionless multigate field-effect transistor

Abstract: This paper describes a metal-oxide-semiconductor MOS transistor concept in which there are no junctions. The channel doping is equal in concentration and type to the source and drain extension doping. The proposed device is a thin and narrow multigate field-effect transistor, which can be fully depleted and turned off by the gate. Since this device has no junctions, it has simpler fabrication process, less variability, and better electrical properties than classical MOS devices with source and drain PN junctions.

High-Efficiency Differential-Drive CMOS Rectifier for UHF RFIDs

Abstract: A high-efficiency CMOS rectifier circuit for UHF RFIDs was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input. A differential-drive active gate bias mechanism simultaneously enables both low ON-resistance and small reverse leakage of diode-connected MOS transistors, resulting in large power conversion efficiency (PCE), especially under small RF input power conditions. A test circuit of the proposed differential-drive rectifier was fabricated with 0.18 mu m CMOS technology, and the measured performance was compared with those of other types of rectifiers. Dependence of the PCE on the input RF signal frequency, output loading conditions and transistor sizing was also evaluated. At the single-stage configuration, 67.5% of PCE was achieved under conditions of 953 MHz, - 12.5 dBm RF input and 10 KOmega output load. This is twice as large as that of the state-of-the-art rectifier circuit. The peak PCE increases with a decrease in operation frequency and with an increase in output load resistance. In addition, experimental results show the existence of an optimum transistor size in accordance with the output loading conditions. The multi-stage configuration for larger output DC voltage is also presented.

Epitaxial-Graphene RF Field-Effect Transistors on Si-Face 6H-SiC Substrates

Abstract: We report dc and the first-ever measured small-signal radio-frequency (RF) performance of epitaxial-graphene RF field-effect transistors (FETs), where the epitaxial-graphene layer is formed by graphitization of 2-in-diameter Si-face semi-insulating 6H-SiC (0001) substrates. The gate is processed with a metal gate on top of a high-k Al2 O3 gate dielectric deposited via an atomic-layer-deposition method. With a gate length (Lg) of 2 mum and an extrinsic transconductance of 148 mS/mm, the extrinsic current-gain cutoff frequency (fT) is measured as 4.4 GHz, yielding an extrinsic fT ldr Lg of 8.8 GHz middot mum. This is comparable to that of Si NMOS. With graphene FETs fabricated in a layout similar to those of Si n-MOSFETs, on-state current density increases dramatically to as high as 1.18 A/mm at Vds = 1 V and 3 A/mm at Vds = 5 V. The current drive level is the highest ever observed in any semiconductor FETs.

Performance Comparison Between p-i-n Tunneling Transistors and Conventional MOSFETs

Abstract: In this paper, we present a detailed performance comparison between conventional n-i-n MOSFET transistors and tunneling field-effect transistors (TFETs) based on the p-i-n geometry, using semiconducting carbon nanotubes as the model channel material. Quantum-transport simulations are performed using the nonequilibrium Green's function formalism considering realistic phonon-scattering and band-to-band tunneling mechanisms. Simulations show that TFETs have a smaller quantum capacitance at most gate biases. Despite lower on-current, they can switch faster in a range of on/off-current ratios. Switching energy for TFETs is observed to be fundamentally smaller than that for MOSFETs, leading to lower dynamic power dissipation. Furthermore, the beneficial features of TFETs are retained with different bandgap materials. These reasons suggest that the p-i-n TFET is well suited for low-power applications.

High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

Abstract: We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I DSAT = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage V DD = 1 V and off-current I OFF = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed.

New Physical Insights on Power MOSFET Switching Losses

Abstract: Realistic estimation of power MOSFET switching losses is critical for predicting the maximum junction temperature and efficiency of power electronics circuits. The purpose of this paper is to investigate the internal physics of MOSFET switching processes using a physically based semiconductor device modeling approach, and subsequently examine the commonly used power loss calculation method in light of the new physical insights. The widely accepted output capacitance loss term is found to be redundant and erroneous based on the new modeling and measurement results. In addition, the existing method of approximating switching times with the power MOSFET gate charge parameters grossly overestimates the switching power loss. This paper recommends a new MOSFET gate charge parameter specification and an effective switching time estimation method to compensate for the power loss calculation error introduced by the two-slope voltage transition waveform of the power MOSFET.

Bilayer PseudoSpin Field-Effect Transistor (BiSFET): A Proposed New Logic Device

Abstract: We propose a new type of graphene-based transistor intended to allow lower voltage, lower power operation than possible with complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Increased energy efficiency is not only important for its own sake, but is also necessary to allow continued device scaling and the resulting increase in computational power in CMOS-like logic circuits. We describe the basic device structure and physics and predicted current-voltage characteristics. Advantages over CMOS in terms of lower voltage and power are discussed.

On Enhanced Miller Capacitance Effect in Interband Tunnel Transistors

Abstract: We compare the transient response of double-gate thin-body-silicon interband tunnel field-effect transistor (TFET) with its metal-oxide-semiconductor field-effect transistor counterpart. Due to the presence of source side tunneling barrier, the silicon TFETs exhibit enhanced Miller capacitance, resulting in large voltage overshoot/undershoot in its large-signal switching characteristics. This adversely impacts the performance of Si TFETs for digital logic applications. It is shown that TFETs based on lower bandgap and lower density of states materials like indium arsenide show significant improvement in switching behavior due to its lower capacitance and higher ON current at reduced voltages.

Fermi level depinning in metal/Ge Schottky junction for metal source/drain Ge metal-oxide-semiconductor field-effect-transistor application

Abstract: Schottky barrier height modulation in metal/Ge Schottky junction was demonstrated by inserting an ultrathin interfacial silicon nitride layer. The SiN interfacial layer suppressed strong Fermi level pinning in metal/Ge Schottky junction, which resulted in effective control of Schottky barrier height. Metal/SiN/Ge Schottky diode was systematically investigated in terms of SiN thickness dependence and metal work function dependence. At an optimal SiN thickness, Ohmic contact between metal and Ge was obtained as a result of Fermi level depinning, and almost ideal Schottky barrier height determined by the work function difference between the metal and Ge was achieved. This technology was finally applied to metal source/drain Ge metal-oxide-semiconductor field-effect-transistors with low source/drain resistance.

Design and Performance of a 200-kHz All-SiC JFET Current DC-Link Back-to-Back Converter

Abstract: Silicon carbide (SiC) switching devices have been widely discussed in power electronics due to their desirable properties and are believed to set new standards in efficiency, switching behavior, and power density for state-of-the-art converter systems. In this paper, the design, construction, and performance of a 3-kVA All-SiC current-source converter (CSC), also known as current dc-link back-to-back converter (CLBBC), is presented. CSC topologies have been successfully used for many years for high-power applications. However, for low-power-range converter systems, they could not compete with voltage-source-converter topologies with capacitors in the dc-link, since the link inductor has always been a physically large and heavy component due to the comparatively low switching frequencies of conventional high-blocking-voltage silicon devices. New SiC switches such as the JFET, which are providing simultaneously high-voltage blocking, low switching losses, and low on-state resistance (three times lower compared with Si MOSFET with similar V- I rating), offer new possibilities and enable the implementation of a high switching frequency CLBBC and, thus, reducing size and weight of the dc-link inductor. The prototype CLBBC has been designed specifically for the latest generation 1200-V 6-A SiC JFETs and a target switching frequency of 200 kHz.

Piezoelectric oxide semiconductor field effect transistor touch sensing devices

Abstract: This work presents piezoelectric oxide semiconductor field effect transistor (POSFET) based touch sensing devices. These devices are fabricated by spin coating thin (∼2.5 μm) piezoelectric polymer film directly on to the gate area of metal oxide semiconductor (MOS) transistor. The polymer film is processed in situ and challenging issues such as in situ poling of piezoelectric polymer film, without damaging or altering the characteristics of underlying MOS devices, are successfully dealt with. The POSFET device represents an integral “sensotronic” unit comprising of transducer and the transistor—thereby sensing as well as conditioning (and processing) the touch signal at “same site.”

Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

Abstract: This letter demonstrates a vertical silicon-nanowire (SiNW)-based tunneling field-effect transistor (TFET) using CMOS-compatible technology. With a Si p+-i- n+ tunneling junction, the TFET with a gate length of ~ 200 nm exhibits good subthreshold swing of ~ 70 mV/dec, superior drain-induced-barrier-lowering of ~ 17 mV/V, and excellent I on - I off ratio of ~ 107 with a low I off ( ~ 7npA/mum). The obtained 53 muA/mum I on can be further enhanced with heterostructures at the tunneling interface. The vertical SiNW-based TFET is proposed to be an excellent candidate for ultralow power and high-density applications.

Characterization and modeling of 1.2 kv, 20 A SiC MOSFETs

Abstract: This paper presents a generic and complete process to characterize and model the newly developed silicon carbide (SiC) MOSFET. The static characteristics, including MOSFET I-V curves, body diode, nonlinear junction capacitances, as well as package stray inductances, have been fully characterized on a prototype 1.2 kV, 20 A SiC MOSFET under varying temperature from 25 °C to 200 °C. Characteristics particular to the SiC MOSFET and its advantages over the silicon counterparts are analyzed and explained. The switching performance of the device, on the other hand, has also been tested under room temperature using a specially designed double-pulse tester with minimized circuit parasitics. The characterization results are then used to build a SiC MOSFET model using the MOSFET modeling tool in Synopsys Saber. Finally, discussions are presented on how to improve the model accuracy in its switching behavior by obtaining static characteristics from switching waveforms.

A Bias-Dependent Single-Event Compact Model Implemented Into BSIM4 and a 90 nm CMOS Process Design Kit

Abstract: A single-event model capable of capturing bias- dependent effects has been developed and integrated into the BSIM4 transistor model and a 90 nm CMOS process design kit. Simulation comparisons with mixed mode TCAD are presented.

Heat Removal in Silicon-on-Insulator Integrated Circuits With Graphene Lateral Heat Spreaders

Abstract: Graphene was recently proposed as a material for heat removal owing to its extremely high thermal conductivity. We simulated heat propagation in silicon-on-insulator (SOI) circuits with and without graphene lateral heat spreaders. Numerical solutions of the heat-propagation equations were obtained using the finite-element method. The analysis was focused on the prototype SOI circuits with the metal-oxide-semiconductor field-effect transistors. It was found that the incorporation of graphene or few-layer graphene (FLG) layers with proper heat sinks can substantially lower the temperature of the localized hot spots. The maximum temperature in the transistor channels was studied as function of graphene's thermal conductivity and the thickness of FLG. The developed model and obtained results are important for the design of graphene heat spreaders and interconnects.

General framework about defect creation at the Si∕SiO2 interface

Abstract: This paper presents a theoretical framework about interface state creation rate from Si–H bonds at the Si∕SiO2 interface. It includes three main ways of bond breaking. In the first case, the bond can be broken, thanks to the bond ground state rising with an electrical field. In two other cases, incident carriers will play the main role either if there are very energetic or very numerous but less energetic. This concept allows one to physically model the reliability of metal oxide semiconductor field effect transistors, and particularly negative bias temperature instability permanent part, and channel hot carrier to cold carrier damage.

Review of FINFET technology

Abstract: Although at single transistor and small circuits level, FINFET technology has been demonstrated to be an attractive option for advanced technology nodes, there are still important challenges to face like reduction of access resistance and the implementation of strain boosters in both NMOS and PMOS FINFET devices. The high performance sensitivity to fin dimensions (width, height, LER) sets up very tight restrictions for the process control which may create a big challenge to demonstrate process manufacturability.

Vertically Stacked Silicon Nanowire Transistors Fabricated by Inductive Plasma Etching and Stress-Limited Oxidation

Abstract: A simple top-down method for realizing an array of vertically stacked nanowires is presented. The process utilizes the nonuniformity in inductively coupled plasma (ICP) etching to form a scallop pattern at the sidewall of a tall silicon ridge that is further trimmed to form stacked nanowires by stress-limited oxidation. The process has been demonstrated to be controllable and repeatable, starting with bulk silicon wafers. Vertically stacked gate-all-around MOSFETs have been fabricated, which show excellent performance with a nearly ideal subthreshold slope of 62 mV/dec, a low leakage current, and a high I on/I off ratio of ~ 108.

Fringing-Induced Drain Current Improvement in the Tunnel Field-Effect Transistor With High- $\kappa$ Gate Dielectrics

Abstract: The tunnel field-effect transistor (tunnel FET) is a promising candidate for future CMOS technology. Its device characteristics have been subject to a variety of experimental and theoretical studies. In this paper, we evaluate the influence of using a high-kappa gate dielectric in the tunnel FET compared to a standard silicon oxide with same equivalent oxide thickness, which exhibits a quite different behavior compared to a conventional MOSFET due to its totally different working principle. It turns out that the fringing field effect, while deteriorating conventional MOSFET characteristics, leads to a much higher on-current comparable with actual conventional MOSFETs, a subthreshold slope of the tunnel FET lower than the theoretical limit for conventional MOSFETs, and a massive improved inverter delay, underlining its prospect for future applications. This leads to the conclusion that high-kappa materials with permittivities > 30 can advantageously be used in CMOS technology, giving rise to further technological development.

Seamless On-Wafer Integration of Si(100) MOSFETs and GaN HEMTs

Abstract: The first on-wafer integration of Si(100) MOSFETs and AlGaN/GaN high electron mobility transistors (HEMTs) is demonstrated. To enable a fully Si-compatible process, we fabricated a novel Si(100)-GaN-Si(100) virtual substrate through a wafer bonding and etch-back technique. The high thermal stability of nitride semiconductors allowed the fabrication of Si MOSFETs on this substrate without degrading the performance of the GaN epilayers. After the Si devices were fabricated, the nitride epilayer is exposed, and the nitride transistors are processed. By using this technology, GaN and Si devices separated by less than 5 mum from each other have been fabricated, which is suitable for building future heterogeneous integrated circuits.

High-Performance $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ -Channel MOSFETs With High- $\kappa$ Gate Dielectrics and $\alpha$ -Si Passivation

Abstract: Long and short buried-channel In0.7Ga0.3As MOSFETs with and without alpha-Si passivation are demonstrated. Devices with alpha-Si passivation show much higher transconductance and an effective peak mobility of 3810 cm2/ V middots. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 muA/mum at Vg - Vt = 1.6 V and peak transconductance of 715 muS/mum. In addition, the virtual source velocity extracted from the short-channel devices is 1.4-1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance In0.7Ga0.3 As-channel MOSFETs passivated by an alpha -Si layer are promising candidates for advanced post-Si CMOS applications.

0.8-V Supply Voltage Deep-Submicrometer Inversion-Mode $\hbox{In}_{0.75}\hbox{Ga}_{0.25}\hbox{As}$ MOSFET

Abstract: We report the experimental demonstration of deep-submicrometer inversion-mode In0.75Ga0.25As MOSFETs with ALD high-k Al2O3 as gate dielectric. In this letter, n-channel MOSFETs with 100-200-nm-long gates have been fabricated. At a supply voltage of 0.8 V, the fabricated devices with 200-130-nm-long gates exhibit drain currents of 232-440 muA/mum and transconductances of 538-705 muS/mum. The 100-nm device has a drain current of 801 muA/mum and a transconductance of 940 muS/mum. However, the device cannot be pinched off due to severe short-channel effect. Important scaling metrics, such as on/off current ratio, subthreshold swing, and drain-induced barrier lowering, are presented, and their relations to the short-channel effect are discussed.

Three level buck converter with control and soft startup

Abstract: The three level buck converter can offer high efficiency and high power density in VR and POL applications. The gains are made possible by adding a flying capacitor that reduces the MOSFET voltage stress by half allowing for the use of low voltage devices, doubles the effective switching frequency, and decreases the inductor size by reducing the volt-second across the inductor. To achieve high efficiency and power density the flying capacitor must be balanced at half of the input voltage and the circuit must be started up without the MOSFETs seeing the full input voltage for protection purposes. This paper provides a new novel control method to balance the flying capacitor with the use of current control and offers a simple startup solution to protect the MOSFETs during start up. Experimental verification shows the efficiency gains and inductance reduction.

$\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ Channel MOSFETs With Self-Aligned InAs Source/Drain Formed by MEE Regrowth

Abstract: -We report Al2O3Zln0.53Ga0.47As MOSFETs having both self-aligned in situ Mo source/drain ohmic contacts and self-aligned InAs source/drain n+ regions formed by MBE regrowth. The device epitaxial dimensions are small, as is required for 22-nm gate length MOSFETs; a 5-nm In0.53Ga0.47As channel with an In0.4sAl0.52As back confinement layer and the n++ source/drain junctions do not extend below the 5-nm channel. A device with 200-nm gate length showed ID = 0.95 mA/mum current density at VGS = 4.0 V and gm = 0.45 mS/mum peak transconductance at VDS = 2.0 V.

A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios

Abstract: The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3sigma) over the temperature range from -22degC to 85degC . Fabricated in a baseline 65 nm CMOS technology, the frequency reference circuit occupies 0.11 mm2 and draws 34 muA from a 1.2 V supply at room temperature.

High-Voltage LDMOS With Charge-Balanced Surface Low On-Resistance Path Layer

Abstract: A high-voltage lateral double-diffusion MOSFET (LDMOS) with a charge-balanced surface low on-resistance path (CBSLOP) layer is proposed and experimentally demonstrated using a modified CMOS process. The CBSLOP layer can not only provide a low on-resistance path in the on-state but also keep the charge balance between the N and P pillars of a surface low on-resistance path in the off-state, which results in improved breakdown voltage (BV). The experimental results show that the CBSLOP-LDMOS with a drift length of 35 mum exhibits a BV of 500 V and specific on-resistance (R on, sp) of 96 mOmega ldr cm2, yielding to a power figure of merit (BV 2/ R on, sp) of 2.6 MW/cm2 . The excellent device performances, coupled with a CMOS-compatible fabrication process, make the proposed CBSLOP-LDMOS a promising candidate for smart power integrated circuit.

Trench-gate ldmos structures

Abstract: MOSFET devices for RF applications that use a trench-gate in place of the lateral gate conventionally used in lateral MOSFET devices. A trench-gate provides devices with a single, short channel for high frequency gain. Embodiments of the present invention provide devices with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Refinements to these TG-LDMOS devices include placing a source-shield conductor below the gate and placing two gates in a trench-gate region. These improve device high-frequency performance by decreasing gate-to-drain capacitance. Further refinements include adding a charge balance region to the LDD region and adding source-to-substrate or drain-to-substrate vias.