Showing papers on "MOSFET published in 2010"
25 Oct 2010
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Abstract: Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.
1,389 citations
TL;DR: In this paper, the authors describe the simulation of the electrical characteristics of a new transistor concept called the junctionless multigate field effect transistor (MuGFET), which has no junctions, a simpler fabrication process, less variability and better electrical properties than classical inversionmode devices with PN junctions at the source and drain.
Abstract: This paper describes the simulation of the electrical characteristics of a new transistor concept called the ‘‘Junctionless Multigate Field-Effect Transistor (MuGFET)”. The proposed device has no junctions, a simpler fabrication process, less variability and better electrical properties than classical inversion-mode devices with PN junctions at the source and drain. The simulation results indicate that the junctionless MuGFET is a very promising candidate for future decananometer MOSFET applications.
508 citations
01 Nov 2010
TL;DR: In this article, a junctionless nanowire transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices using bulk conduction instead of surface channel.
Abstract: Conduction mechanisms in junctionless nanowire transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon.
458 citations
TL;DR: In this paper, the temperature dependence of the main electrical parameters of junctionless (JL) silicon nanowire transistors is investigated and compared to the standard inversion-and accumulation-mode FETs.
Abstract: This paper investigates the temperature dependence of the main electrical parameters of junctionless (JL) silicon nanowire transistors. Direct comparison is made to silicon nanowire (trigate) MOSFETs. Variation of parameters such as threshold voltage and on-off current characteristics is analyzed. The JL silicon nanowire FET has a lager variation of threshold voltage with temperature than the standard inversion- and accumulation-mode FETs. Unlike in classical devices, the drain current of JL FETs increases when temperature is increased.
370 citations
TL;DR: In this article, the authors proposed a hetero-gate-dielectric TFET, which enhances on-current, suppresses ambipolar behavior, and makes abrupt on-off transition by replacing the source-side gate insulator with a high-k material, which induces a local minimum of the conduction band edge at the tunneling junction.
Abstract: A tunneling field-effect transistor (TFET) is considered one of the most promising alternatives to a metal-oxide-semiconductor field-effect transistor due to its immunity to short-channel effects. However, TFETs have suffered from low on-current, severe ambipolar behavior, and gradual transition between on- and off -states. To address those issues, the authors have proposed hetero-gate-dielectric TFETs. The proposed device enhances on-current, suppresses ambipolar behavior, and makes abrupt on-off transition by replacing the source-side gate insulator with a high-k material, which induces a local minimum of the conduction band edge at the tunneling junction.
354 citations
TL;DR: In this article, the electric field perpendicular to the current flow was found to be significantly lower in junctionless transistors than in regular inversion-mode or accumulation-mode field effect transistors.
Abstract: The electric field perpendicular to the current flow is found to be significantly lower in junctionless transistors than in regular inversion-mode or accumulation-mode field-effect transistors. Since inversion channel mobility in metal-oxide-semionductor transistors is reduced by this electric field, the low field in junctionless transistor may give them an advantage in terms of current drive for nanometer-scale complementary metal-oxide semiconductor applications. This observation still applies when quantum confinement is present.
287 citations
TL;DR: In this article, a new technique for fabricating 4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) with high inversion channel mobility was proposed.
Abstract: We propose a new technique for fabricating 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with high inversion channel mobility. P atoms were incorporated into the SiO2/4H-SiC (0001) interface by postoxidation annealing using phosphoryl chloride (POCl3). The interface state density near the conduction band edge of 4H-SiC was reduced significantly, and the peak field-effect mobility of lateral 4H-SiC MOSFETs on (0001) Si face was improved to 89 cm2/V · s by POCl3 annealing at 1000°C.
274 citations
TL;DR: In this article, a single-stage stacked field effect transistor (FET) linear power amplifier (PA) was demonstrated using 0.28-?m 2.5-V standard I/O FETs in a 0.13-?m silicon-on-insulator (SOI) CMOS technology.
Abstract: A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-?m 2.5-V standard I/O FETs in a 0.13-?m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.
232 citations
22 Mar 2010
TL;DR: In this article, the authors present the fundamentals and current status of research of compound semiconductor metal-oxide-semiconductor field effect transistors (MOSFETs) that are envisioned as a future replacement of silicon in digital circuits.
Abstract: Fundamentals of III-V Semiconductor MOSFETs presents the fundamentals and current status of research of compound semiconductor metal-oxide-semiconductor field-effect transistors (MOSFETs) that are envisioned as a future replacement of silicon in digital circuits. The material covered begins with a review of specific properties of III-V semiconductors and available technologies making them attractive to MOSFET technology, such as band-engineered heterostructures, effect of strain, nanoscale control during epitaxial growth. Due to the lack of thermodynamically stable native oxides on III-V's (such as SiO2 on Si), high-k oxides are the natural choice of dielectrics for III-V MOSFETs. The key challenge of the III-V MOSFET technology is a high-quality, thermodynamically stable gate dielectric that passivates the interface states, similar to SiO2 on Si. Several chapters give a detailed description of materials science and electronic behavior of various dielectrics and related interfaces, as well as physics of fabricated devices and MOSFET fabrication technologies. Topics also include recent progress and understanding of various materials systems; specific issues for electrical measurement of gate stacks and FETs with low and wide bandgap channels and high interface trap density; possible paths of integration of different semiconductor materials on Si platform.
223 citations
TL;DR: In this paper, the authors have developed models allowing a direct comparison between the single-gate, double-gate and gate-all-around configuration at high drain voltage, when the drain-voltage dependence is negligible.
Abstract: Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because scaling the supply voltage below 1 V is possible due to the absence of a subthreshold-swing limit of 60 mV/decade. The modeling of the TFET performance, however, is still preliminary. We have developed models allowing a direct comparison between the single-gate, double-gate, and gate-all-around configuration at high drain voltage, when the drain-voltage dependence is negligible, and we provide improved insight in the TFET physics. The dependence of the tunnel current on device parameters is analyzed, in particular, the scaling with gate-dielectric thickness, channel thickness, and dielectric constants of gate dielectric and channel material. We show that scaling the gate-dielectric thickness improves the TFET performance more than scaling the channel thickness and that improvements are often overestimated. There is qualitative agreement between our model and our experimental data.
220 citations
TL;DR: In this article, the improvement of sub-threshold slope due to impact ionization is compared between standard inversion-mode multigate silicon nanowire transistors and junctionless transistors.
Abstract: The improvement of subthreshold slope due to impact ionization is compared between “standard” inversion-mode multigate silicon nanowire transistors and junctionless transistors. The length of the region over which impact ionization takes place, as well as the amplitude of the impact ionization rate are found to be larger in the junctionless devices, which reduces the drain voltage necessary to obtain a sharp subthreshold slope.
19 Jun 2010
TL;DR: In this paper, a spin-torque transfer magnetoresistive RAM (STT-MRAM) based implementation of an eight-core Sun Niagara-like CMT processor is presented.
Abstract: As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations, traditional MOSFET scaling theory prescribes reducing supply and threshold voltages in proportion to device dimensions, a practice that induces an exponential increase in subthreshold leakage. As a result, leakage power has become comparable to dynamic power in current-generation processes, and will soon exceed it in magnitude if voltages are scaled down any further. Beyond this inflection point, multicore processors will not be able to afford keeping more than a small fraction of all cores active at any given moment. Multicore scaling will soon hit a power wall. This paper presents resistive computation, a new technique that aims at avoiding the power wall by migrating most of the functionality of a modern microprocessor from CMOS to spin-torque transfer magnetoresistive RAM (STT-MRAM)---a CMOS-compatible, leakage-resistant, non-volatile resistive memory technology. By implementing much of the on-chip storage and combinational logic using leakage-resistant, scalable RAM blocks and lookup tables, and by carefully re-architecting the pipeline, an STT-MRAM based implementation of an eight-core Sun Niagara-like CMT processor reduces chip-wide power dissipation by 1.7× and leakage power by 2.1× at the 32nm technology node, while maintaining 93% of the system throughput of a CMOS-based design.
TL;DR: In this paper, a quasianalytical modeling approach for graphene metal-oxide-semiconductor field effect transistors (MOSFETs) with gapless large-area graphene channels is presented.
Abstract: A quasianalytical modeling approach for graphene metal-oxide-semiconductor field-effect transistors (MOSFETs) with gapless large-area graphene channels is presented. The model allows the calculation of the I-V characteristics, the small-signal behavior, and the cutoff frequency of graphene MOSFETs. It applies a correct formulation of the density of states in large-area graphene to calculate the carrier-density-dependent quantum capacitance, a steady-state velocity-field characteristics with soft saturation to describe the carrier transport, and takes the source/drain series resistances into account. The modeled drain currents and transconductances show very good agreement with experimental data taken from the literature {Meric et al., [Nat. Nanotechnol. 3, 654 (2008)] and Kedzierski et al., [IEEE Electron Device Lett. 30, 745 (2009)]}. In particular, the model properly reproduces the peculiar saturation behavior of graphene MOSFETs with gapless channels.
TL;DR: In this paper, a numerical simulation study of gate capacitance components in a tunneling field effect transistor (TFET) was performed, showing key differences in the partitioning of gate capacitor between the source and drain as compared with a MOSFET.
Abstract: We report a numerical simulation study of gate capacitance components in a tunneling field-effect transistor (TFET), showing key differences in the partitioning of gate capacitance between the source and drain as compared with a MOSFET. A compact model for TFET capacitance components, including parasitic and inversion capacitances, was built and calibrated with computer-aided design data. This model should be useful for further investigation of performance of circuits containing TFETs. The dependence of gate-drain capacitance Cgd on drain design and gate length was further investigated for reduction of switching delay in TFETs.
Posted Content•
TL;DR: In this paper, the authors presented the unique features exhibited by modified asymmetrical double gate (DG) silicon on insulator (SOI) MOSFET, which exhibits significantly reduced short channel effects.
Abstract: In this paper, we present the unique features exhibited by modified asymmetrical Double Gate (DG) silicon on insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, Dual Material Double Gate (DMDG) SOI MOSFET, exhibits significantly reduced short channel effects when compared with the DG SOI MOSFET. Short channel effects in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, electric field, threshold voltage and drain induced barrier lowering. A model for the drain current, transconductance, drain conductance and voltage gain is also discussed. It is seen that short channel effects in this structure are suppressed because of the perceivable step in the surface potential profile, which screens the drain potential. We further demonstrate that the proposed DMDG structure provides a simultaneous increase in the transconductance and a decrease in the drain conductance when compared with the DG structure. The results predicted by the model are compared with those obtained by two-dimensional simulation to verify the accuracy of the proposed analytical model.
01 Dec 2010
TL;DR: In this paper, the first complete experimental demonstration and investigation of subthreshold swing, SS, smaller than 60 mV/decade, at room temperature, due to internal voltage amplification in FETs with a Metal-Ferroelectric-Metal-Oxide gate stack was reported.
Abstract: This work reports the first complete experimental demonstration and investigation of subthreshold swing, SS, smaller than 60 mV/decade, at room temperature, due to internal voltage amplification in FETs with a Metal-Ferroelectric-Metal-Oxide gate stack. The investigated p-type MOS transistor is a dedicated test structure to explore the negative capacitance effect by probing the internal voltage between the P(VDF-TrFE) and SiO 2 dielectric layers of the gate stack. We find that the region of internal surface potential amplification, dψ S /dV g >1, corresponds to an S-shape of the polarization versus ferroelectric voltage (associated with negative capacitance). In Fe-FETs the internal voltage amplification could significantly lower their SS, even without reaching sub-60mV/dec values. SS min as low as 46 to 58 mV/decade and average swings, SS avg , as small as 51 to 59 mV/dec are observed for the first time in a minor loop hysteretic characteristics of Fe-FETs.
TL;DR: In this article, a normally off GaN MOSFET was proposed by utilizing an extremely high 2D electron-gas density at an AlGaN/GaN heterostructure as source and drain, which can be obtained by controlling the tensile stress accompanied with the growth of GaN on silicon substrate.
Abstract: A normally off GaN MOSFET was proposed by utilizing an extremely high 2-D electron-gas density (> 1014 / cm2) at an AlGaN/GaN heterostructure as source and drain, which can be obtained by controlling the tensile stress accompanied with the growth of GaN on silicon substrate. The fabricated MOSFET with an Al2O3 gate insulator exhibited excellent device performance, such as a threshold voltage of 2 V, drain current of 353 mA/mm, extrinsic transconductance of 98 mS/mm, and field-effect mobility of 225 cm2/V·s.
TL;DR: In this paper, time-dependent dielectric-breakdown measurements are performed on state-of-the-art 4H-SiC MOS capacitors and double-implanted MOS field effect transistors (DMOSFET) with stress temperatures between 225°C and 375°C, and stress electric fields between 6 and 10 MV/cm.
Abstract: The wide-bandgap nature of silicon carbide (SiC) makes it an excellent candidate for applications where high temperature is required. The metal-oxide-semiconductor (MOS)-controlled power devices are the most favorable structure; however, it is widely believed that silicon oxide on SiC is physically limited, particularly at high temperatures. Therefore, experimental measurements of long-term reliability of oxide at high temperatures are necessary. In this paper, time-dependent dielectric-breakdown measurements are performed on state-of-the-art 4H-SiC MOS capacitors and double-implanted MOS field-effect transistors (DMOSFET) with stress temperatures between 225°C and 375°C and stress electric fields between 6 and 10 MV/cm. The field-acceleration factor is around 1.5 dec/(MV/cm) for all of the temperatures. The thermal activation energy is found to be ~ 0.9 eV, independent of the electric field. The area dependence of Weibull slope is discussed and shown to be a possible indication that the oxide quality has not reached the intrinsic regime and further oxide-reliability improvements are possible. Since our reliability data contradict the widely accepted belief that silicon oxide on SiC is fundamentally limited by its smaller conduction-band offset compared with Si, a detailed discussion is provided to examine the arguments of the early predictions.
01 Jan 2010
TL;DR: In this paper, the performance potential of a 1-dimensional TFET with a broken-gap heterojunction source injector using dissipative quantum transport simulations based on the nonequilibrium Green's function formalism, as well as the carbon nanotube band structure was explored.
Abstract: Tunneling field-effect transistors (TFETs) have gained a great deal of interest recently due to their potential to reduce power dissipation in integrated circuits. One major challenge for TFETs so far has been to achieve high drive currents, which is a prerequisite for high-performance operation. In this paper, we explore the performance potential of a 1-D TFET with a broken-gap heterojunction source injector using dissipative quantum transport simulations based on the nonequilibrium Green's function formalism, as well as the carbon nanotube band structure as the model 1-D material system. We provide detailed insights into broken-gap TFET (BG-TFET) operation and show that it can, indeed, produce less than 60 mV/dec subthreshold swing at room temperature, even in the presence of electron-phonon scattering. The 1-D geometry is recognized to be uniquely favorable due to its superior electrostatic control, reduced carrier thermalization rate, and beneficial quantum confinement effects that reduce the off-state leakage below the thermionic limit. Because of higher source injection compared to staggered-gap and homojunction geometries, BG-TFET delivers superior performance that is comparable to MOSFET's. BG-TFET even exceeds the MOSFET performance at lower supply voltages (VDD), showing promise for low-power/high-performance applications.
TL;DR: This paper investigates the influence of both channel and gate engineering on the analog and RF performances of double-gate (DG) MOSFETs for system-on-chip applications and shows improvements in gate- and channel-engineered devices.
Abstract: The design of analog and RF circuits in CMOS technology has become increasingly more difficult as device modeling faces new challenges in the deep-submicrometer regime and emerging circuit applications. In this paper, we investigate the influence of both channel and gate engineering on the analog and RF performances of double-gate (DG) MOSFETs for system-on-chip applications. The gate engineering technique used here is the dual-metal gate technology, and the channel engineering technique is the conventional halo doping process. For analog applications, importance is given to the subthreshold regime as CMOS circuits operated in this regime are very much attractive for ultralow-power high-gain performances. Gate- and channel-engineered devices show an increase of gain by 45% and 35%, respectively, compared with the single-metal DG MOSFET. The gate-engineered device shows an improvement of 21.6% and 20% in the case of fT and fMAX values, whereas the channel-engineered device exhibits a reduction of fT by 2.7% with nearly equal fMAX.
IBM1
TL;DR: In this paper, experimental data from undoped-body gate-all-around (GAA) silicon nanowire (NW) MOSFETs with different sizes demonstrate the universality of short channel effects as a function of LEFF/λ, where LEFF is the effective channel length and λ is the electrostatic scaling length.
Abstract: Experimental data from undoped-body gate-all-around (GAA) silicon nanowire (NW) MOSFETs with different sizes demonstrate the universality of short-channel effects as a function of LEFF/λ, where LEFF is the effective channel length and λ is the electrostatic scaling length. Data from undoped-body single-gate extremely thin SOI (ETSOI) devices additionally show that the universality of short-channel effects is valid for any undoped-body fully depleted SOI MOSFET. Our data indicate that LEFF of undoped GAA NW MOSFETs can be scaled down by ~2.5 times compared with undoped single-gate ETSOI MOSFETs while maintaining equivalent short-channel control.
TL;DR: In this paper, the performance of a tunnel field effect transistor (TFET) with a raised germanium (Ge) source region is investigated via 2D device simulation with a tunneling model calibrated to experimental data.
Abstract: The performance of a tunnel field effect transistor (TFET) with a raised germanium (Ge) source region is investigated via 2-D device simulation with a tunneling model calibrated to experimental data. The comparison of various Ge-source TFET designs shows that a fully elevated Ge-source design provides for the steepest subthreshold swing and, therefore, the largest on-state drive current for low-voltage operation. Mixed-mode (dc and ac) simulations are used to assess the energy-delay performance. In comparison with a MOSFET, an optimized Ge-source TFET is projected to provide for a lower energy per operation for throughput in the frequency range of up to ~1 GHz for sub-0.5-V operation.
IBM1
TL;DR: In this paper, a dual-gate graphene field effect transistor with a cutoff frequency of 50 GHz is presented, which is the highest frequency reported for any graphene transistor, and it also exceeds that of Si MOS field effect transistors at the same gate length.
Abstract: A dual-gate graphene field-effect transistor is presented, which shows improved radio-frequency (RF) performance by reducing the access resistance using electrostatic doping. With a carrier mobility of 2700 cm2/V · s, a cutoff frequency of 50 GHz is demonstrated in a 350-nm-gate-length device. This fT value is the highest frequency reported to date for any graphene transistor, and it also exceeds that of Si MOS field-effect transistors at the same gate length, illustrating the potential of graphene for RF applications.
Book•
26 Jun 2010
TL;DR: D-MOSFET Structure as discussed by the authors, UMOS FET Structure, SC-MFSFET Structures, CC-MMSFET structure, GD-MCSFET, SJ-MSSFET and SiC Planar MFSF Structures.
Abstract: D-MOSFET Structure.- U-MOSFET Structure.- SC-MOSFET Structure.- CC-MOSFET Structure.- GD-MOSFET Structure.- SJ-MOSFET Structure.- Integral Diode.- SiC Planar MOSFET Structures.- Synopsis.
TL;DR: In this article, the most aggressive dimensions reported in Ge-channel transistors are pMOSFETs with 30-nm gate length on ultrathin germanium-on-insulator substrates (TGe = 25 nm).
Abstract: We present in this letter the most aggressive dimensions reported to date in Ge-channel transistors: pMOSFETs with 30-nm gate length on ultrathin germanium-on-insulator substrates (TGe = 25 nm). By improving both the Ge-enrichment technique and the transistor fabrication process, we demonstrate devices with controlled threshold voltage (Vth) and excellent short-channel effects. Moreover, the low defectivity and the very low thickness of the Ge film lead to a record drain OFF-state leakage for Ge-channel devices (< 1 nA/?m at VDS = -1 V) and thus, to the best ON-state to OFF-state current ratio (ION/IOFF ~5 × 105), even at Lg = 55 nm.
TL;DR: In this paper, the influence of the intrinsic parameter fluctuations consisting of metal-gate work-function fluctuation (WKF), process-variation effect (PVE), and random-dopant fluctuation(RDF) on 16-nm-gate planar metal-oxide-semiconductor field effect transistors (MOSFETs) and circuits is investigated.
Abstract: This paper, for the first time, estimates the influences of the intrinsic-parameter fluctuations consisting of metal-gate work-function fluctuation (WKF), process-variation effect (PVE), and random-dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field-effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold-voltage fluctuation (?V th) ; however, the WKF brings less impact on the gate capacitance and the cutoff frequency due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the ?V th and is therefore proportional to the trend of ?V th. The power fluctuation consisting of the dynamic, short-circuit, and static powers is further investigated. The total power fluctuation for the planar MOSFET circuits is 15.2%, which is substantial in the reliability of circuits and systems. The static power is a minor part of the total power; however, its fluctuation is significant because of the serious fluctuation of the leakage current. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3-dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuit characteristic fluctuations due to the significant gate-capacitance fluctuations, and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can, in turn, be used to optimize nanoscale MOSFETs and circuits.
TL;DR: In this paper, an extensive benchmark of their critical electrical figures of merit (FOM) and their limitations is presented. And the authors demonstrate highperforming FinFET ring-oscillators with delays down to 10ps/stage for both SOI and bulk Fin-FETs.
Abstract: The multi-gate architecture is considered as a key enabler for further CMOS scaling thanks to its improved electrostatics and short-channel effect control. FinFETs represent one of the architectures of interest within that family together with Ω-gates, Π-gates, gate-all-around… They can readily be manufactured starting from SOI or bulk substrates even though more efforts have been dedicated to the SOI option so far. We report in this work an extensive benchmark of their critical electrical figures of merit (FOM) and their limitations. Both alternatives show better scalability (threshold voltage – Vt vs. L) than PLANAR CMOS and exhibit similar intrinsic device performance (Ioff vs. Ion). Introducing SOI substrates and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced threshold voltage mismatch. Using an optimized integration to minimize parasitic capacitances and resistances we demonstrate high-performing FinFET ring-oscillators with delays down to 10 ps/stage for both SOI and bulk FinFETs. SRAM cells are also reported to work, scaling similarly with the supply voltage (VDD) for the two FinFET integration schemes.
TL;DR: In this article, the performance potential of a 1D TFET with a broken-gap heterojunction source injector using dissipative quantum transport simulations based on the nonequilibrium Green's function formalism and the carbon nanotube bandstructure was explored.
Abstract: Tunneling field-effect transistors (TFETs) have gained a great deal of recent interest due to their potential to reduce power dissipation in integrated circuits. One major challenge for TFETs so far has been achieving high drive currents, which is a prerequisite for high-performance operation. In this paper we explore the performance potential of a 1D TFET with a broken-gap heterojunction source injector using dissipative quantum transport simulations based on the nonequilibrium Green's function formalism, and the carbon nanotube bandstructure as the model 1D material system. We provide detailed insights into broken-gap TFET (BG-TFET) operation, and show that it can indeed produce less than 60mV/decade subthreshold swing at room temperature even in the presence of electron-phonon scattering. The 1D geometry is recognized to be uniquely favorable due to its superior electrostatic control, reduced carrier thermalization rate, and beneficial quantum confinement effects that reduce the off-state leakage below the thermionic limit. Because of higher source injection compared to staggered-gap and homojunction geometries, BG-TFET delivers superior performance that is comparable to MOSFET's. BG-TFET even exceeds the MOSFET performance at lower supply voltages (VDD), showing promise for low-power/high-performance applications.
TL;DR: High-frequency measurements on vertically standing III-V nanowire wrap-gate MOSFETs (metal-oxide-semiconductor field-effect transistors) demonstrate that this is a viable technique for fabricating high-frequency integrated circuits consisting of vertical nanowires.
Abstract: In this letter we report on high-frequency measurements on vertically standing III-V nanowire wrap-gate MOSFETs (metal-oxide-semiconductor field-effect transistors). The nanowire transistors are fabricated from InAs nanowires that are epitaxially grown on a semi-insulating InP substrate. All three terminals of the MOSFETs are defined by wrap around contacts. This makes it possible to perform high-frequency measurements on the vertical InAs MOSFETs. We present S-parameter measurements performed on a matrix consisting of 70 InAs nanowire MOSFETs, which have a gate length of about 100 nm. The highest unity current gain cutoff frequency, f(t), extracted from these measurements is 7.4 GHz and the maximum frequency of oscillation, f(max), is higher than 20 GHz. This demonstrates that this is a viable technique for fabricating high-frequency integrated circuits consisting of vertical nanowires.