Showing papers on "MOSFET published in 2011"

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

Abstract: For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

MoS2 Dual-Gate MOSFET with Atomic-Layer-Deposited Al2O3 as Top-Gate Dielectric

Abstract: We demonstrate atomic-layer-deposited (ALD) high-k dielectric integration on two-dimensional (2D) layer-structured molybdenum disulfide (MoS2) crystals and MoS2 dual-gate n-channel MOSFETs with ALD Al2O3 as top-gate dielectric. Our C-V study of MOSFET structures shows good interface between 2D MoS2 crystal and ALD Al2O3. Maximum drain currents using back-gates and top-gates are measured to be 7.07mA/mm and 6.42mA/mm at Vds=2V with a channel width of 3 {\mu}m, a channel length of 9 {\mu}m, and a top-gate length of 3 {\mu}m. We achieve the highest field-effect mobility of electrons using back-gate control to be 517 cm^2/Vs. The highest current on/off ratio is over 10^8.

Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation

Abstract: A design methodology of ferroelectric (FE) negative capacitance FETs (NCFETs) based on the concept of capacitance matching is presented. A new mode of NCFET operation, called the “antiferroelectric mode” is proposed, which, besides achieving sub-60mV/dec subthreshold swing, can significantly boost the on-current in exchange for a nominal hysteresis. Design considerations for different device parameters (FE thickness, EOT, source/drain overlap & gate length) are explored. It is suggested that relative improvement in device performance due to FE negative capacitance becomes more significant in very short channel length devices because of the increased drain-to-channel coupling.

Junctionless Multiple-Gate Transistors for Analog Applications

Abstract: This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width Wfin and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage VEA and larger intrinsic voltage gain AV than IM devices of similar dimensions. In addition, VEA and AV are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.

Charge-Based Modeling of Junctionless Double-Gate Field-Effect Transistors

Abstract: We derived an analytical model for the junctionless double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) device, the principle of which has been recently demonstrated. Despite some similarities with classical junction-based DG MOSFETs, the charge-potential relationships are quite different and cannot be merely mapped on existing multigate formalisms. This is particularly true for the technological parameters of interest where reported doping densities exceed 1019 cm-3 for 10- and 20-nm silicon channel thicknesses. Assessment of the model with numerical simulations confirms its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation.

Totem-Pole Boost Bridgeless PFC Rectifier With Simple Zero-Current Detection and Full-Range ZVS Operating at the Boundary of DCM/CCM

Abstract: A totem-pole boost bridgeless power-factor-correction rectifier with simple zero-current detection and full-range zero-voltage switching (ZVS) is proposed, which operates at the boundary of discontinuous-conduction mode and continuous-conduction mode. Comparing with the boundary dual boost bridgeless rectifier, the required number of power components is reduced by one third and two current transducers can be eliminated. The zero-current detection is achieved by sampling the diode current through a single current transducer. Besides, a soft-transition method is proposed to suppress the current spike at the line-voltage zero-crossing point. Furthermore, a ZVS range extension operation is proposed to achieve ZVS in the MOSFETs within the full range of line input, which needs no additional MOSFETs. This also makes it possible to reduce MOSFET turn-OFF losses by paralleling external capacitors. Hence, a high-efficiency and low common-mode noise-interference bridgeless rectifier is achieved. This rectifier is also a candidate for interleaving operation to upgrade the power level. The experimental results show that ZVS is achieved within the full range of universal line input. The efficiency is above 96% at full load under 90 V and the maximum efficiency is above 98.4%. The ZVS range extension operation improves the efficiency by 0.5%.

10 kV, 120 A SiC half H-bridge power MOSFET modules suitable for high frequency, medium voltage applications

Abstract: The majority carrier domain of power semiconductor devices has been extended to 10 kV with the advent of SiC MOSFETs and Schottky diodes. The devices exhibit excellent static and dynamic properties with encouraging preliminary reliability. Twenty-four MOSFETs and twelve Schottky diodes have been assembled in a 10 kV half H-bridge power module to increase the current handling capability to 120 A per switch without compromising the die-level characteristics. For the first time, a custom designed system (13.8 kV to 465/√3 V solid state power substation) has been successfully demonstrated with these state of the art SiC modules up to 855 kVA operation and 97% efficiency. Soft-switching at 20 kHz, the SiC enabled SSPS represents a 70% reduction in weight and 50% reduction in size when compared to a 60 Hz conventional, analog transformer.

Efficiency Impact of Silicon Carbide Power Electronics for Modern Wind Turbine Full Scale Frequency Converter

Abstract: Power electronics is an enabling technology found in most renewable energy generation systems. Because of its superior voltage blocking capabilities and fast switching speeds, silicon carbide (SiC) power electronics are considered for use in power conversion units in wind generation systems in this paper. The potential efficiency gains from the use of SiC devices in a wind generation system are explored by simulations, with the system modeling explained in detail. The performance of the SiC converter is analyzed and compared to its silicon counterpart at different wind speeds, temperatures, and switching frequencies. The quantitative results are based on SiC metal-oxide-semiconductor field-effect transistor (MOSFET) prototypes from Cree and modern Si insulated-gate bipolar transistor (IGBT) products. A conclusion is drawn that the SiC converters can improve the wind system power conversion efficiency and can reduce the system's size and cost due to the low-loss, high-frequency, and high-temperature properties of SiC devices, even for one-for-one replacement for Si devices.

RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs

Abstract: This paper presents a radio-frequency (RF) model and extracted model parameters for junctionless silicon nanowire (JLSNW) metal-oxide-semiconductor field-effect transistors (MOSFETs) using a 3-D device simulator. JLSNW MOSFETs are evaluated for various RF parameters such as cutoff frequency fT, gate input capacitance, distributed channel resistances, transport time delay, and capacitance by the drain-induced barrier lowering effect. Direct comparisons of high-frequency performances and extracted parameters are made with conventional silicon nanowire MOSFETs. A non-quasi-static RF model has been used, along with SPICE to simulate JLSNW MOSFETs with RF parameters extracted from 3-D-simulated Y-parameters. The results show excellent agreements with the 3-D-simulated results up to the high frequency of fT.

Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors

Abstract: A bulk current model is formulated for long-channel double-gate junctionless (DGJL) transistors. Using a depletion approximation, an analytical expression is derived from the Poisson equation to find channel potential, which expresses the dependence of depletion width under an applied gate voltage. The depletion width equation is further simplified by the unique characteristic of junctionless transistors, i.e., a high channel doping concentration. From the depletion width formula, the bulk current model is constructed using Ohm's law. In addition, an analytical expression for subthreshold current is derived. The proposed model is compared with simulation data, revealing good agreement. The simplicity of the model gives a fast and easy way to understand, analyze, and design DGJL transistors comprehensively.

Graphene field-effect transistors

Abstract: Owing in part to scaling challenges for metal oxide semiconductor field-effect transistors (MOSFETs) and complementary metal oxide semiconductor (CMOS) logic, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide improved MOSFET performance beyond the 22 nm node, or provide novel functionality for, e.g. 'beyond CMOS' devices. Graphene, with its novel and electron–hole symmetric band structure and its high carrier mobilities and thermal velocities, is one such material that has garnered a great deal of interest for both purposes. Single and few layer carbon sheets have been fabricated by a variety of techniques including mechanical exfoliation and chemical vapour deposition, and field-effect transistors have been demonstrated with room-temperature mobilities as high as 10 000 cm2 V−1 s−1. But graphene is a gapless semiconductor and gate control of current is challenging, off-state leakage currents are high, and current does not readily saturate with drain voltage. However, various ways to overcome, adapt to, or even embrace this property are now being considered for device applications. In this work we explore through illustrative examples the potential of and challenges to graphene use for conventional and novel device applications.

Study of Random Dopant Fluctuation Effects in Germanium-Source Tunnel FETs

Abstract: The effects of random dopant fluctuations (RDFs) on the performance of Germanium-source tunnel field-effect transistors (TFETs) is studied using 3-D device simulation. The RDF in the source region is found to have the most impact on threshold voltage variation (σVTH) if the source is moderately doped (1019 cm-3) such that vertical tunneling within the source is dominant. If the source is heavily doped (1020 cm-3) such that lateral tunneling from the source to the channel is dominant, the impact of RDF in the channel region is also significant. RDF-induced threshold voltage variation (σVTH) for an optimally designed Ge-source TFET is relatively modest (σVTH <; 20 mV at Lg = 30 nm), compared with a MOSFET of similar gate length. Supply voltage scaling is not beneficial for reducing TFET σVTH.

Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits.

Abstract: We introduce the concept of a silicon nanotube field effect transistor whose unique core–shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core–shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow.

Enhanced Electrostatic Integrity of Short-Channel Junctionless Transistor With High- $\kappa$ Spacers

Abstract: We propose the use of a high-κ spacer to improve the electrostatic integrity and, thereby, the scalability of silicon junctionless transistors (JLTs) for the first time. Using extensive simulations of n-channel JLTs, we demonstrate that the high-κ spacers improve the electrostatic integrity of JLTs at sub-22-nm gate lengths. Electric field that fringes through the high-κ spacer to the device layer on either sides of the gate results in an effective increase in electrical gate length in the off-state. However, the effective gate length is unaffected in the on-state. Hence, the off-state leakage current is reduced by several orders of magnitude with the use of a high-κ spacer with concomitent improvements in the subthreshold swing and drain-induced barrier lowering. A marginal improvement in the on-state current is observed with the use of the high-κ spacer, and this is related to the reduction in parasitic resistance in the silicon under the spacer due to fringe fields.

Junctionless Transistors: Physics and Properties

Abstract: Junctionless transistors are variable resistors controlled by a gate electrode. The silicon channel is a heavily doped nanowire that can be fully depleted to turn the device off. The electrical characteristics are identical to those of normal MOSFETs, but the physics is quite different. This paper compares the conduction mechanisms in three types of MOS devices: inversion-mode, accumulation-mode and junctionless MOSFET.

Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic

Abstract: A detailed circuit assessment of Tunneling Field Effect Transistors (TFET) versus MOSFET operating near device threshold supply voltage, including the consideration of process variations, is reported. The analysis incorporates simulated 20nm TFET and MOSFET device characteristics combined with detailed circuit simulation. For very low power logic applications requiring near device threshold supply voltage, the results show that TFET logic can operate at equal standby power and switching energy to MOSFET, but with a ∼8x performance advantage. The study also shows that device parameter variation is not a significant factor for differentiation between MOSFET and TFET.

Scaling Between Channel Mobility and Interface State Density in SiC MOSFETs

Abstract: The direct impact of the SiO2/4H-SiC interface state density (Dit) on the channel mobility of lateral field-effect transistors is studied by tailoring the trap distribution via nitridation of the thermal gate oxide. We observe that mobility scales like the inverse of the charged state density, which is consistent with Coulomb-scattering-limited transport at the interface. We also conclude that the Dit further impacts even the best devices by screening the gate potential, yielding small subthreshold swings and poor turn-ON characteristics.

Evaluation of a 1200-V, 800-A All-SiC Dual Module

Abstract: Enhanced material properties of silicon carbide (SiC) offer improved performance capabilities for power electronic devices compared to traditional silicon (Si) components. This paper reports on the experimental characterization of a 1200-V, 800-A all-SiC dual power module that incorporates twenty 80-A SiC MOSFETs and twenty 50-A SiC junction barrier Schottky diodes. Forward and reverse conduction characteristics were measured at multiple gate voltages, current sharing was examined between the MOSFETs, and switching energies were calculated for various currents. Additionally, this module has operated in a full-bridge circuit with a peak loading of 900 Adc, a 600 Vdc bus, and a junction temperatures of 153°C. From the experimental data, a model of the module was created and used in a dc-ac inverter simulation study to demonstrate the possible benefits of SiC compared to Si technology. The use of an all-SiC module was shown to reduce inverter losses by 40% or more for most operating conditions. Furthermore, for similar output current levels, the all-SiC module can operate at switching frequencies four times higher than that of the Si module. This advanced dual power module demonstrates the ability to produce a high-current high-power switch using SiC technology.

First experimental demonstration of gate-all-around III–V MOSFETs by top-down approach

Abstract: The first inversion-mode gate-all-around (GAA) III–V MOSFETs are experimentally demonstrated with a high mobility In 0.53 Ga 0.47 As channel and atomic-layer-deposited (ALD) Al 2 O 3 /WN gate stacks by a top-down approach. A well-controlled InGaAs nanowire release process and a novel ALD high-k/metal gate process has been developed to enable the fabrication of III–V GAA MOSFETs. Well-behaved on-state and off-state performance has been achieved with channel length (L ch ) down to 50nm. A detailed scaling metrics study (S.S., DIBL, V T ) with L ch of 50nm – 110nm and fin width (W Fin ) of 30nm – 50nm are carried out, showing the immunity to short channel effects with the advanced 3D structure. The GAA structure has provided a viable path towards ultimate scaling of III–V MOSFETs.

Tunneling FETs on SOI: Suppression of ambipolar leakage, low-frequency noise behavior, and modeling

Abstract: We report on thin-body tunneling field-effect transistors (TFETs) built on SOI substrates with both SiO 2 and HfO 2 gate dielectrics. The source–drain leakage current is suppressed by the introduction of an intrinsic region adjacent to the drain, reducing the electric field at the tunnel junction in the off state. We also investigate the temperature dependence of the TFET characteristics and demonstrate that the temperature-induced change in the Si bandgap is the main mechanism that determines the tunneling barrier and hence the drain current I D . We present a model of the TFET as a combination of a gated diode and a MOSFET, which can be solved analytically and can predict the experimentally measured I D over a wide range of drain and gate bias. Finally we report on the low frequency noise (LFN) behavior of TFETs, which unlike conventional MOSFETs exhibits 1/ f 2 frequency dependence even for large gate areas. This dependence indicates less trapping due to the much smaller effective gate length over the tunneling junction.

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Abstract: Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH ) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with T inv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

A critical re-evaluation of the usefulness of R-D framework in predicting NBTI stress and recovery

Abstract: Reaction-Diffusion (R-D) framework for interface trap generation along with hole trapping in pre-existing and generated bulk oxide traps are used to model Negative Bias Temperature Instability (NBTI) in differently processed SiON p-MOSFETs. Time, temperature and bias dependent degradation and recovery transients are predicted. Long-time power law exponent of DC degradation and uniquely renormalized duty cycle and frequency dependent AC degradation data from a wide range of sources are shown to have universal features and a broad consensus across industry/academia. These universal features can also be predicted using the classical R-D framework.

Compact Virtual-Source Current–Voltage Model for Top- and Back-Gated Graphene Field-Effect Transistors

Abstract: This paper presents a compact model for the current-voltage characteristics of graphene field-effect transistors (GFETs), which is based on an extension of the “virtual-source” model previously proposed for Si MOSFETs and is valid for both saturation and nonsaturation regions of device operation. This GFET virtual-source model provides a simple and intuitive understanding of carrier transport in GFETs, allowing extraction of the virtual-source injection velocity vVS, which is a physical parameter with great technological significance for short-channel graphene transistors. The derived I-V characteristics account for the combined effects of the drain-source voltage VDS, the top-gate voltage VTGS, and the back-gate voltage VBGS. With only a small set of fitting parameters, the model shows excellent agreement with experimental data. It is also shown that the extracted virtual-source carrier injection velocity for graphene devices is much higher than in Si MOSFETs and state-of-the-art III-V heterostructure FETs with similar gate length, demonstrating the great potential of GFETs for high-frequency applications. Comparison with experimental data for chemical-vapor-deposited GFETs from our group and epitaxial GFETs in the literature confirms the validity and flexibility of the model for a wide range of existing GFET devices.

A tunneling field effect transistor model combining interband tunneling with channel transport

Abstract: We present a model for the tunneling field-effect transistor (TFET) comprising a series connection of a metal-oxide-semiconductor FET (MOSFET) with a gate-controllable tunneling diode. Through the introduction of MOSFET in the model, both operational regimes of TFET are handled correctly, with the tunneling diode dominating at low interband tunneling current and the MOSFET component dominating at high tunneling current. The comparison between our model, TCAD simulations and experimental data on TFETs with different gate oxide and channel thicknesses over the full range of gate and drain bias confirms the model’s reliability and accuracy. At low tunneling current, the model further simplifies to a compact analytical model. With minor modifications, our model can also be applied to multi-gate TFET architectures.

Work-Function-Tuned TiN Metal Gate FDSOI Transistors for Subthreshold Operation

Abstract: The effective work function of a reactively sputtered TiN metal gate is shown to be tunable from 4.30 to 4.65 eV. The effective work function decreases with nitrogen flow during reactive sputter deposition. Nitrogen annealing increases the effective work function and reduces Dit. Thinner TiN improves the variation in effective work function and reduces gate dielectric charge. Doping of the polysilicon above the TiN metal gate with B or P has negligible effect on the effective work function. The work-function-tuned TiN is integrated into ultralow-power fully depleted silicon-on-insulator CMOS transistors optimized for subthreshold operation at 0.3 V. The following performance metrics are achieved: 64-80-mV/dec subthreshold swing, PMOS/NMOS on-current ratio near 1, 71% reduction in Cgd, and 55% reduction in Vt variation when compared with conventional transistors, although significant short-channel effects are observed.

Low-Power and Highly Reliable Multilevel Operation in $ \hbox{ZrO}_{2}$ 1T1R RRAM

Abstract: The Ti/ZrO2/Pt resistive memory devices with one transistor and one resistor (1T1R) architecture are successfully fabricated in this letter. The tested devices show low operation current (20 μA), low switching voltage (set/reset, 0.8/-1 V), and reliable data retention for low-resistance state (LRS) with a 20-μA set current at 80°C (over ten years) via an excellent current limiter, namely, a metal-oxide-semiconductor field-effect transistor (MOSFET). In addition, multilevel storage characteristics are also demonstrated by modulating the amplitude of the MOSFET gate voltage. The various LRS levels obtained are possibly attributed to the formation of different numbers and sizes of conducting filaments consisting of oxygen vacancies caused by an external electric field. Moreover, reproducible resistive switching characteristics up to 2000 switching cycles are achieved in the same device. Our 1T1R ZrO2-based resistive switching access memory with low-power and highly reliable multilevel operation has high potential for practical applications.

High-Mobility Ge N-MOSFETs and Mobility Degradation Mechanisms

Abstract: Ge N-MOSFETs have exhibited poor drive currents and low mobility, as reported by several different research groups in the past. The major mechanisms behind poor Ge NMOS performance have not been completely understood yet. In this paper, mechanisms responsible for poor Ge NMOS performance in the past are investigated with detailed gate dielectric stack characterizations and Hall mobility analysis. High source/drain (S/D) parasitic resistance, inversion charge loss due to trapping in the high-K gate dielectric, and high interface trap density are identified as the mechanisms responsible for Ge NMOS performance degradation. After eliminating the degradation mechanisms, the highest electron mobility in Ge NMOS to date, which is, to the best of our knowledge, ~1.5 times the universal Si mobility, is experimentally demonstrated for the Ge N-MOSFETs fabricated with ozone-oxidation surface passivation and low temperature S/D activation processes.

Optimization of the $\hbox{Al}_{2}\hbox{O}_{3}/ \hbox{GaSb}$ Interface and a High-Mobility GaSb pMOSFET

Abstract: While there have been many demonstrations on n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) in III-V semiconductors showing excellent electron mobility and high drive currents, hole mobility in III-V p-channel MOSFETs (pMOSFETs) has traditionally lagged in comparison to silicon. GaSb is an attractive candidate for high-performance III-V pMOSFETs due to its high bulk hole mobility. We fabricate and study GaSb pMOSFETs with an atomic layer deposition Al2O3 gate dielectric and a self-aligned source/drain formed by ion implantation. The band offsets of Al2O3 on GaSb were measured using synchrotron radiation photoemission spectroscopy. The use of a forming gas anneal to passivate the dangling bonds in the bulk of the dielectric was demonstrated. The density of interface states Dit was measured across the GaSb band gap using conductance measurements, and a midband-gap Dit of 3 × 1011/cm2 eV was achieved. This enabled pMOSFETs with a peak hole mobility value of 290 cm2/Vs.

Dual- $V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits

Abstract: This paper describes the electrode work-function, oxide thickness, gate-source/drain underlap, and silicon thick ness optimization required to realize dual-Vth independent-gate FinFETs. Optimum values for these FinFET design parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-Vth FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional CMOS gates, e.g., implementing 12 unique Boolean functions using only four transistors. Circuit designs that balance and improve the performance of the novel gates are described. The gates are designed and calibrated using the University of Florida double-gate model into conventional and enhanced technology libraries. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2 GHz, the enhanced library reduces total power and the number of fins by 36% and 37%, respectively, over a conventional library designed using shorted-gate FinFETs in 32 nm technology.

Graphene: Its Fundamentals to Future Applications

Abstract: Currently, graphene is a topic of very active research fields from science to potential applications. For various RF circuit applications, including low-noise amplifiers, the unique ambipolar nature of graphene field-effect-transistors can be utilized for high-performance frequency multipliers, mixers, and high-speed radiometers. Potential integration of graphene on silicon substrates with CMOS compatibility would also benefit future RF systems. The future success of the RF circuit applications depends on vertical and lateral scaling of graphene MOSFETs to minimize parasitics and improve gate modulation efficiency in the channel with zero or a small bandgap. In this paper, we highlight recent progress in graphene materials, devices, and circuits for RF applications. For passive RF applications, we show its transparent electromagnetic shielding in Ku-band and transparent antennas, where its success depends on the quality of materials. We also attempt to discuss future applications and challenges of graphene.