Showing papers on "MOSFET published in 2013"

Depletion-mode Ga2O3 metal-oxide-semiconductor field-effect transistors on β-Ga2O3 (010) substrates and temperature dependence of their device characteristics

Abstract: Single-crystal gallium oxide (Ga2O3) metal-oxide-semiconductor field-effect transistors were fabricated on a semi-insulating β-Ga2O3 (010) substrate. A Sn-doped n-Ga2O3 channel layer was grown by molecular-beam epitaxy. Si-ion implantation doping was performed to source and drain electrode regions for obtaining low-resistance ohmic contacts. An Al2O3 gate dielectric film formed by atomic layer deposition passivated the device surface and significantly reduced gate leakage. The device with a gate length of 2 μm showed effective gate modulation of the drain current with an extremely low off-state drain leakage of less than a few pA/mm, leading to a high drain current on/off ratio of over ten orders of magnitude. A three-terminal off-state breakdown voltage of 370 V was achieved. Stable transistor operation was sustained at temperatures up to 250 °C.

High-Performance Normally-Off ${\rm Al}_{2}{\rm O}_{3}/{\rm GaN}$ MOSFET Using a Wet Etching-Based Gate Recess Technique

Abstract: This letter reports a normally-OFF Al2O3/GaN gate-recessed MOSFET using a low-damage digital recess technique featuring multiple cycles of plasma oxidation and wet oxide removal process. The wet etching process eliminates the damage induced by plasma bombardment induced in conventional inductively coupled plasma dry etching process so that good surface morphology and high interface quality could be achieved. The fully recessed Al2O3/GaN MOSFET delivers true enhancement-mode operation with a threshold voltage of +1.7 V. The maximum output current density is 528 mA/mm at a positive gate bias of 8 V. A peak field-effect mobility of 251 cm2/V·s is obtained, indicating high-quality Al2O3/GaN interface.

Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime

Abstract: In this paper, we propose an approximate solution to solve the two dimensional potential distribution in ultra-thin body junctionless double gate MOSFET (JL DG MOSFET) operating in the subthreshold regime. Basically, we solved the 2D-Poisson equation along the channel, while assuming a parabolic potential across the silicon thickness, which in turn leads to some explicit relationships of the subthreshold current, subthreshold slope (SS) and drain induced barrier lowering (DIBL). This approach has been assessed with Technology Computer Aided Design (TCAD) simulations, confirming that this represents an interesting solution for further implementation in generic JL DG MOSFETs compact models.

A 16nm FinFET CMOS technology for mobile SoC and computing applications

Abstract: For the first time, we present a state-of-the-art energy-efficient 16nm technology integrated with FinFET transistors, 0.07um2 high density (HD) SRAM, Cu/low-k interconnect and high density MiM for mobile SoC and computing applications. This technology provides 2X logic density and >35% speed gain or >55% power reduction over our 28nm HK/MG planar technology. To our knowledge, this is the smallest fully functional 128Mb HD FinFET SRAM (with single fin) test-chip demonstrated with low Vccmin for 16nm node. Low leakage (SVt) FinFET transistors achieve excellent short channel control with DIBL of <;30 mV/V and superior Idsat of 520/525 uA/um at 0.75V and Ioff of 30 pA/um for NMOS and PMOS, respectively.

Short-circuit capability of 1200V SiC MOSFET and JFET for fault protection

Abstract: The short-circuit capability of power switches is crucial for the fault protection. In this paper, 1200V SiC MOSFET and normally-off SiC JFET have been characterized and their short-circuit capabilities have been studied and analyzed at 400V DC bus voltage. Due to different physics in the channels, SiC MOSFET and SiC JFET show different types of temperature coefficient. During the short-circuit operation, the saturation current, Isat, of SiC MOSFET increases for several microseconds before the gentle decreasing while that of SiC JFET decreases drastically from the very beginning. The SiC MOSFETs failed after short-circuit operations of 80μs and 50μs at 10V and 15V gate bias respectively while the SiC JFET could survive a short-circuit time more than 1.4msec.

Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors

Abstract: The aim of this review paper is to describe in a comprehensive manner the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies. Total Ionizing Dose (TID) response, heavy-ion microdose effects and single-event effects (SEEs) will be discussed. It is shown that a very high TID tolerance can be achieved by narrow-fin SOI FinFET architectures, while bulk FinFETs may exhibit similar TID response to the planar devices. Due to the vertical nature of FinFETs, a specific heavy-ion response can be obtained, whereby the angle of incidence becomes highly important with respect to the vertical sidewall gates. With respect to SEE, the buried oxide in the SOI FinFETs suppresses the diffusion tails from the charge collection in the substrate compared to the planar bulk FinFET devices. Channel lengths and fin widths are now comparable to, or smaller than the dimensions of the region affected by the single ionizing ions or lasers used in testing. This gives rise to a high degree of sensitivity to individual device parameters and source-drain shunting during ion-beam or laser-beam SEE testing. Simulations are used to illuminate the mechanisms observed in radiation testing and the progress and needs for the numerical modeling/simulation of the radiation response of advanced SOI and FinFET transistors are highlighted.

Analytical loss model of high voltage GaN HEMT in cascode configuration

Abstract: This paper presents an accurate analytical model to calculate the power loss of a high voltage Gallium Nitride high electron mobility transistor (GaN HEMT) in cascode configuration. The proposed model considers the package and PCB parasitic inductances, the nonlinearity of the junction capacitors and the transconductance of the cascode GaN transistor. The switching process is illustrated in detail, including the interaction of the low voltage Si MOSFET and high voltage GaN HEMT in cascode configuration. The switching loss is obtained by solving the equivalent circuits during the switching transition. The analytical results show that the turn on loss dominates in hard-switching conditions while the turn off loss is negligible, due to the intrinsic current source driving mechanism. The accuracy of the proposed model is validated by numerous experimental results. The results of both the analytical model and experiments suggest that soft-switching is critical for high voltage GaN in high frequency high efficiency applications.

Evaluation and application of 600V GaN HEMT in cascode structure

Abstract: Gallium nitride high electron mobility transistor (GaN HEMT) has matured dramatically over the last few years. More and more devices have been manufactured and field in applications ranging from low power voltage regulator to high power infrastructure base-stations. Compared to the state of art silicon MOSFET, GaN HEMT has much better figure of merit and is potential for high frequency application. In general, 600V GaN HEMT is intrinsically normally-on device. To easily apply depletion mode GaN HEMT in circuit design, a low voltage silicon MOSFET is in series to drive the GaN HEMT, which is well known as cascode structure. This paper studies the characteristics and operation principles of 600V cascode GaN HEMT. Evaluations of GaN HEMT performance based on Buck converter under hard-switching and soft-switching conditions are presented. Experimental results illustrate that GaN HEMT is superior than silicon MOSFET but still needs soft-switching in high frequency operation due to considerable package and layout parasitic inductors and capacitors. Then GaN HEMT is applied to a 1MHz 300W 400V/12V LLC converter. Comparison of experimental results with state of art silicon MOSFET is provided to validate the advantages of GaN HEMT.

Heterojunction TFET Scaling and resonant-TFET for steep subthreshold slope at sub-9nm gate-length

Abstract: The Tunneling Field Effect Transistor (TFET) is of interest for future low-power technologies due to its steep subthreshold-slope (SS) [1, 2]. In addition to understanding TFET's prospects for future technology nodes [3], we also need to assess if it enables continued scaling required for increasing transistor density. GaSb/InAs heterojunction TFET (Het-j TFET) is one of the leading TFET options due to its high drive-current [4]. In this paper, double-gate (DG) and nanowire (NW) Het-j TFETs (Fig. 1) are atomisticly modeled and compared to a MOSFET down to Lg~9nm, i.e. ITRS 2022 node [5]. To achieve TFET characteristics superior to a MOSFET, its DG body has to be extremely thin, so a NW TFET is therefore preferred due to its more relaxed thickness and better transistor characteristics. A new device - the Resonant-TFET (R-TFET), is proposed, with SS~25mV/dec over ~3.5 decades of current, enabling the scaling of tunneling transistors to sub-9nm gate-lengths (Lg).

Dielectric-Modulated Impact-Ionization MOS Transistor as a Label-Free Biosensor

Abstract: In this letter, we propose a dielectric-modulated impact-ionization MOS (DIMOS) transistor-based sensor for application in label-free detection of biomolecules. Numerous reports exist on the experimental demonstration of nanogap-embedded field effect transistor-based biosensors, but an impact-ionization MOS (I-MOS)-based biosensor has not been reported previously. The concept of a dielectric-modulated I-MOS-based biosensor is presented in this letter based on technology computer-aided design simulation study. The results show a high sensitivity to the presence of biomolecules even at small channel lengths. In addition, a low variability of the sensitivity to the charges on the biomolecule is observed. The high sensitivity, dominance of dielectric-modulation effects, and operation at even small channel lengths make the DIMOS biosensor a promising alternative for CMOS-based sensor applications.

Threshold voltage control by gate oxide thickness in fluorinated GaN metal-oxide-semiconductor high-electron-mobility transistors

Abstract: This paper demonstrates the compensation of the intrinsic positive charges in Al2O3 gate dielectric by fluorine ions in GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs). Negatively-charged fluorine ions diffused into the oxide from the AlGaN barrier during the 250 °C atomic layer deposition compensate the intrinsic positive charge present in the Al2O3. This compensation is key to control the threshold voltage (Vth) of enhancement-mode (E-mode) transistors. A comprehensive analytical model for the Vth of fluorinated MOS-HEMTs was established and verified by experimental data. This model allows the calculation of the different charge components in order to optimize the transistor structure for E-mode operation. Using the proposed charge compensation, the Vth increases with gate dielectric thickness, exceeding 3.5 V for gate dielectrics 25 nm thick.

Active current balancing for parallel-connected silicon carbide MOSFETs

Abstract: In high power applications of silicon carbide (SiC) MOSFETs where parallelism is employed, current unbalance can occur and affect the performance and reliability of the power devices. In this paper, factors which cause current unbalance in these devices are analyzed. Among them, the threshold voltage mismatch is identified as a major factor for dynamic current unbalance. The threshold distribution of SiC MOSFETs is investigated, and its effect on current balance is studied in experiments. Based on these analyses, an active current balancing scheme is proposed. It is able to sense the unbalanced current and eliminate it by actively controlling the gate drive signal to each device. The features of fine time resolution and low complexity make this scheme attractive to a wide variety of wide-band-gap device applications. Experimental and simulation results verify the feasibility and effectiveness of the proposed scheme.

Performance comparison of 1200V 100A SiC MOSFET and 1200V 100A silicon IGBT

Abstract: This paper presents the characteristics of the first commercial 1200V 100A SiC MOSFET module and compares it with state-of-the-art silicon IGBT with the same rating. The results show that the 1200V SiC MOSFET has faster switching speed and much lower loss compared with silicon IGBT. Moreover, the silicon IGBT switching loss will increase significantly for higher operation temperature, while the SiC MOSFET switching loss is almost the same for different temperature. A loss model has been implemented in PLECs in order to simulation the losses. An 11kW singlephase inverter prototype with 600V dc bus and 380Vac output voltage has been built for evaluating and comparing the SiC MOSFET and Si IGBT performance. The test results match with the simulation very well and show that with 40 kHz switching frequency the inverter efficiency can be increased to 98.5% from 96.5% if replacing the Si IGBT with the SiC MOSFET module.

Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond

Abstract: We present results from gate-all-around (GAA) silicon nanowire (SiNW) MOSFETs fabricated using a process flow capable of achieving a nanowire pitch of 30 nm and a scaled gate pitch of 60 nm. We demonstrate for the first time that GAA SiNW devices can be integrated to density targets commensurate with CMOS scaling needs of the 10 nm node and beyond. In addition, this work achieves the highest performance for GAA SiNW NFETs at a gate pitch below 100 nm.

Fabrication of Normally Off AlGaN/GaN MOSFET Using a Self-Terminating Gate Recess Etching Technique

Abstract: A self-terminating gate recess etching technique is first proposed to fabricate normally off AlGaN/GaN MOSFET. The gate recess process includes a thermal oxidation of the AlGaN barrier layer for 40 min at 615°C followed by 45-min etching in potassium hydroxide solution at 70°C, which is found to be self-terminated at the AlGaN/GaN interface with negligible effect on the underlying GaN layer, manifesting itself easy to control, highly repeatable, and promising for industrialization. The fabricated device based on this technique with atomic layer deposition Al2O3 as gate insulator exhibits a threshold voltage as high as 3.2 V with a maximum drain current over 200 mA/mm and a 60% increased breakdown voltage than that of the conventional high electron mobility transistors.

Comprehensive Analysis of Short-Channel Effects in Ultrathin SOI MOSFETs

Abstract: This paper analyzes the 2-D short-channel effect in ultrathin SOI MOSFETs. An empirical, channel length-dependent scale length is extracted from the lateral field slope of a series of numerically simulated devices. We show how this scale length is related to the short-channel threshold voltage roll-off and minimum channel length with and without a substrate bias. The benefit of a reverse substrate bias is investigated and understood in terms of the field and distribution of inversion charge in the silicon film. In particular, how a bulk-like short-channel effect is achieved when an accumulation layer is formed at the back surface. Furthermore, the effect of a high-κ gate insulator is studied and scaling implications discussed.

Subthreshold Behavior Models for Nanoscale Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs

Abstract: With the exact solution of the 2-D Poisson's equation in cylindrical coordinates, analytical subthreshold behavior models for junctionless cylindrical surrounding-gate (JLCSG) MOSFETs are developed. Using these analytical models, subthreshold characteristics of JLCSG MOSFETs are investigated in terms of channel electrostatic potential distribution, subthreshold current, and subthreshold slope (SS). It is shown that the electrostatic potential distribution, subthreshold current, and SS predicted by the analytical models are in close agreement with 3-D numerical simulation results without the need of any fitting parameters. These analytical models not only provide useful physical insight into the subthreshold behaviors, but also offer basic design guideline for the nanoscale JLCSG MOSFETs.

D $v$ /D $t$ -Control Methods for the SiC JFET/Si MOSFET Cascode

Abstract: Switching devices based on SiC offer outstanding performance with respect to operating frequency, junction temperature, and conduction losses enabling significant improvement of the performance of converter systems. There, the cascode consisting of a MOSFET and a JFET has additionally the advantage of being a normally off device and offering a simple control via the gate of the MOSFET. Without dv /dt-control, however, the transients for hard commutation reach values of up to 45kV/μs, which could lead to electromagnetic interference problems. Especially in drive systems, problems could occur, which are related to earth currents (bearing currents) due to parasitic capacitances. Therefore, new dv/d t-control methods for the SiC JFET/Si MOSFET cascode as well as measurement results are presented in this paper. Based on this new concepts, the outstanding performance of the SiC devices can be fully utilized without impairing electromagnetic compatibility.

Energy efficiency comparison of nanowire heterojunction TFET and Si MOSFET at L g =13nm, including P-TFET and variation considerations

Abstract: Reducing supply voltage (Vdd) while keeping leakage current low is critical for minimizing energy consumption and improving mobile device battery life. The thermal limit of MOSFET subthreshold slope (SS) restricts lowering threshold voltage (Vt), causing significant performance degradation at low Vdd. A Tunneling Field Effect Transistor (TFET) is not limited by this thermal tail and may perform better at low Vdd [1,2]. In this paper, a leading N-TFET option - GaSb/InAs heterojunction - is atomistically modeled [3,4] and circuit simulation models are developed to predict 64% average energy savings against Si CMOS at Lg=13nm for a nanowire. Energy savings diminish to 21% without a good P-TFET option. Both MOSFET and TFET device variations are dominated by work-function variation, and TFET energy savings are slightly reduced when variations are considered.

Device and Circuit Performance Estimation of Junctionless Bulk FinFETs

Abstract: The design and characteristics of junctionless (JL) bulk FinFET devices and circuits are compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum transport device simulation. The JL bulk FinFET shows better short channel characteristics, including drain-induced barrier lowering, subthreshold slope, and threshold voltage (Vth) roll-off characteristics at supply voltage (VDD) 1 V. Analyses of electron density and electricfield distributions in on-state and off-state also show that the JL devices have better on-off current ratios. Regarding design aspects, the effects of channel doping concentration (Nch) and Fin height (H)/width (W) on device Vth are also compared. In addition, the Vth of the proposed JL bulk FinFET can be easily tuned by an additional parameter, substrate doping concentration (Nsub). Inverter performance and static random access memory (SRAM) circuit performance are also compared using a coupled device-circuit simulation. The high-to-low delay time (tHL) and low-to-high delay time (tLH) of the inverter with JL bulk FinFET are smaller than the inverter with IM bulk FinFET. The JL bulk FinFET SRAM cell also provides a similar static transfer characteristic to those of IM bulk FinFET SRAM cell, which show large potential in digital circuit application.

A Push–Pull Class-C CMOS VCO

Abstract: A CMOS oscillator employing differential transistor pairs working in Class-C in push-pull configuration is presented. The oscillator exhibits the same advantages enjoyed by complementary topologies on oscillators based on a single differential pair, while yielding a substantial power consumption reduction thanks to the Class-C operation. The phase-noise performance and the fundamental conditions required to keep the transistors working in Class-C are analyzed in detail. It is shown that, for an optimal performance, both nMOS and pMOS transistors should not be pushed into the deep triode region by the instantaneous resonator voltage, and a simple circuit solution is proposed to accommodate a large oscillation swing. A 0.18- μm CMOS prototype of the (voltage-controlled) oscillator displays an oscillation frequency from 6.09 to 7.50 GHz. The phase noise at 2-MHz offset is below -120 dBc/Hz with a power dissipation of 2.2 mW, for a state-of-the-art figure-of-merit ranging from 189 to 191 dBc/Hz.

Performance Comparison Between Bulk and SOI Junctionless Transistors

Abstract: The design and characteristics of a junctionless (JL) bulk FinFET were compared with the silicon-on-insulator (SOI) JL nanowire transistor (JNT) using 3-D quantum transport device simulation The JL bulk FinFET exhibits a favorable on/offcurrent ratio and short-channel characteristics by reducing the effective channel thickness that is caused by the channel/substrate junction The drain-induced barrier lowering and the subthreshold slope are about 40 mV and 73 mV/dec, respectively, with an on/offcurrent ratio of 105 at W = 10 nm The JL bulk FinFET is less sensitive to the channel thickness than the SOI JNT Furthermore, the threshold voltage Vth of the JL bulk FinFET can be easily tuned by varying substrate doping concentration Nsub The modulation range of Vth as Nsub changes from 1018 to 1019 cm-3, which is around 30%

High mobility CMOS technologies using III–V/Ge channels on Si platform

Abstract: MOSFETs using channel materials with high mobility and low effective mass have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime. From this viewpoint, attentions have recently been paid to Ge and III–V channels. In this paper, possible solutions for realizing III–V/Ge MOSFETs on the Si platform are presented. The high quality III–V channel formation on Si substrates can be realized through direct wafer bonding. The gate stack formation is constructed on a basis of atomic layer deposition (ALD) Al 2 O 3 gate insulators for both InGaAs and Ge MOSFETs. As the source/drain (S/D) formation, Ni-based metal S/D is implemented for both InGaAs and Ge MOSFETs. By combining these technologies, we demonstrate successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on a same wafer and their superior device performance.

A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme

Abstract: A 1 Mb nonvolatile embedded memory using a four transistor and two spin-transfer-torque (STT) magnetic tunnel junction (MTJ) cell is designed and fabricated to demonstrate its zero standby power and high performance. The power supply voltages of 32 cells along a word line (WL) are controlled simultaneously by a power line (PL) driver to eliminate the standby power without impact on the access time. This fine-grained power gating scheme also optimizes the trade-off between macro size and operation power. The butterfly curve for the cell is measured to be asymmetric as predicted, enhancing the cell's static noise margin (SNM) for data retention. The scaling of 1 Mb macro size is compared with that of the 6T SRAM counterpart, indicating that the former will become smaller than the latter at 45 nm technology node and beyond by moderately thinning its tunnel dielectrics (MgO) in accordance with the shrink of the MTJ's cross sectional area. The operation current of the macro is also shown to be almost unchanged over generations, while that of the 6T SRAM increases exponentially due to the degradation of MOSFET off-current as the device scales.

Impact of Temperature Variations on the Device and Circuit Performance of Tunnel FET: A Simulation Study

Abstract: The paper presents a comprehensive comparison study of p-i-n and p-n-p-n tunnel field-effect transistor (TFET) architectures and the impact of temperature on their dc and circuit performance. The impact of a hetero-gate (HG) dielectric on the circuit performance also forms the part of the study. The device performance of p-i-n and p-n-p-n TFET with high-k dielectric and HG dielectric and the effect of temperature on the drain current characteristics, Ion/Ioff, and threshold voltage has been investigated and compared with MOSFET. Furthermore, the variations in the inverter (n-TFET with resistive load) transient characteristics and the fall delay due to temperature variations are studied using mixed mode simulations carried out with ATLAS device simulation software. Results reveal that TFET exhibits weak temperature dependence when the current conduction is band-to-band tunneling dominated, while the temperature dependence increases in the off-state regime, and the fall delay of resistive load n-TFET inverter decreases with increasing temperature.

Interfacial band configuration and electrical properties of LaAlO3/Al2O3/hydrogenated-diamond metal-oxide-semiconductor field effect transistors

Abstract: In order to search a gate dielectric with high permittivity on hydrogenated-diamond (H-diamond), LaAlO3 films with thin Al2O3 buffer layers are fabricated on the H-diamond epilayers by sputtering-deposition (SD) and atomic layer deposition (ALD) techniques, respectively. Interfacial band configuration and electrical properties of the SD-LaAlO3/ALD-Al2O3/H-diamond metal-oxide-semiconductor field effect transistors (MOSFETs) with gate lengths of 10, 20, and 30 μm have been investigated. The valence and conduction band offsets of the SD-LaAlO3/ALD-Al2O3 structure are measured by X-ray photoelectron spectroscopy to be 1.1 ± 0.2 and 1.6 ± 0.2 eV, respectively. The valence band discontinuity between H-diamond and LaAlO3 is evaluated to be 4.0 ± 0.2 eV, showing that the MOS structure acts as the gate which controls a hole carrier density. The leakage current density of the SD-LaAlO3/ALD-Al2O3/H-diamond MOS diode is smaller than 10−8 A cm−2 at gate bias from −4 to 2 V. The capacitance-voltage curve in the depletion mode shows sharp dependence, small flat band voltage, and small hysteresis shift, which implies low positive and trapped charge densities. The MOSFETs show p-type channel and complete normally off characteristics with threshold voltages changing from −3.6 ± 0.1 to −5.0 ± 0.1 V dependent on the gate length. The drain current maximum and the extrinsic transconductance of the MOSFET with gate length of 10 μm are −7.5 mA mm−1 and 2.3 ± 0.1 mS mm−1, respectively. The enhancement mode SD-LaAlO3/ALD-Al2O3/H-diamond MOSFET is concluded to be suitable for the applications of high power and high frequency electrical devices.

Border Traps in Ge/III–V Channel Devices: Analysis and Reliability Aspects

Abstract: The aim of this review paper is to describe the impact of so-called border traps (BTs) in high- k gate oxides on the operation and reliability of high-mobility channel transistors. First, a brief summary of the physics of BTs will be given, describing the charge trapping and release in terms of the elastic tunneling model. It will be also pointed out how information on the BT properties can be extracted from popular measurement techniques such as low-frequency (1/f) noise and variable-frequency charge pumping. In the next two parts, the impact of BTs on metal-oxide-semiconductor structures fabricated on Ge or III-V channel materials is outlined, with particular emphasis on the development of novel or adapted measurement techniques such as AC transconductance dispersion or trap spectroscopy by charge injection and sensing. Finally, the effect of BTs on the operation and reliability of high-mobility channel MOSFETs is discussed. It is also shown that the density of BTs is closely linked to the quality or defectivity of the high- k gate stack, indicating room for improvement by optimization of processing or by implementation of a suitable bulk-oxide defect passivation step.

Study of gate oxide traps in HfO2/AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors by use of ac transconductance method

Abstract: We introduce an ac-transconductance method to profile the gate oxide traps in a HfO2 gated AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors (MOS-HEMTs) that can exchange carriers with metal gates, which in turn causes changes in analog and pulsed channel currents. The method extracts energy and spacial distributions of the oxide and interface traps under the gate from the frequency dependence of ac transconductance. We demonstrate the method using MOS-HEMTs with gate oxides that were annealed at different temperatures.

Cryogenic and high temperature performance of 4H-SiC power MOSFETs

Abstract: The electrical performance of 4H-SiC Power MOSFETs is studied at temperatures from 93K to 473K. With the decrease of operation temperature, the threshold voltage is found to increase linearly whereas the on-resistance shows a minimum value within the whole temperature range. The rapid increase of on-resistance at lower temperature is ascribed to the presence of large densities of interface traps at the SiC/SiO2 interface. In addition, the breakdown voltage is also measured down to 93K and found to increase monotonously with temperature. A set of parameters, determining the breakdown voltage of 4H-SiC MOSFET at different temperatures, is put forward in this paper, by fitting the experimental data.

Stochastic Variability in Silicon Double-Gate Lateral Tunnel Field-Effect Transistors

Abstract: Device-level variability in silicon double-gate lateral tunnel field-effect transistors (TFETs) due to line-edge roughness (LER) and random dopant fluctuation (RDF) is investigated for designs with a 20-nm gate length and body widths of 5 or 10 nm (“20/5” and “20/10,” respectively). Variability in TFET threshold voltage (VT), on-state drive current (Ion), off-state leakage current (Ioff), and subthreshold swing is examined by means of statistical technology computer-aided design simulations with consideration of body LER up to 1 nm in amplitude as well as RDF for body heights ranging from 10 to 40 nm. The effects of body LER and RDF are found to be similar in magnitude and also comparable to those in similarly designed fin FETs, with the exception of Ion variability which is roughly three times higher for TFETs. Arguments are presented to explain these findings based on the operating principle of TFETs compared to standard metal-oxide-semiconductor-FET-based technology.