Showing papers on "MOSFET published in 2014"

Evaluation and Application of 600 V GaN HEMT in Cascode Structure

Abstract: Gallium nitride high electron mobility transistor (GaN HEMT) has matured dramatically over the last few years. A progressively larger number of GaN devices have been manufactured for in field applications ranging from low power voltage regulators to high power infrastructure base-stations. Compared to the state-of-the-art silicon MOSFET, GaN HEMT has a much better figure of merit and shows potential for high-frequency applications. The first generation of 600 V GaN HEMT is intrinsically normally on device. To easily apply normally on GaN HEMT in circuit design, a low-voltage silicon MOSFET is in series to drive the GaN HEMT, which is well known as cascode structure. This paper studies the characteristics and operation principles of a 600 V cascode GaN HEMT. Evaluations of the cascode GaN HEMT performance based on buck converter at hard-switching and soft-switching conditions are presented in detail. Experimental results prove that the cascode GaN HEMT is superior to the silicon MOSFET, but it still needs soft-switching in high-frequency operation due to considerable package and layout parasitic inductors and capacitors. The cascode GaN HEMT is then applied to a 1 MHz 300 W 400 V/12 V LLC converter. A comparison of experimental results with a state-of-the-art silicon MOSFET is provided to validate the advantages of the GaN HEMT.

A 1200-V, 60-A SiC MOSFET Multichip Phase-Leg Module for High-Temperature, High-Frequency Applications

Abstract: In this paper, a high-temperature, high-frequency, wire-bond-based multichip phase-leg module was designed, fabricated, and fully tested. Using paralleled Silicon Carbide (SiC) MOSFETs, the module was rated at 1200 V and 60 A, and was designed for a 25-kW three-phase inverter operating at a switching frequency of 70 kHz, and in a harsh environment up to 200 °C, for aircraft applications. To this end, the temperature-dependent characteristics of the SiC MOSFET were first evaluated. The results demonstrated the superiority of the SiC MOSFET in both static and switching performances compared to Si devices, but meanwhile did reveal the design tradeoff in terms of the device's gate oxide stability. Various high-temperature packaging materials were then extensively surveyed and carefully selected for the module to sustain the harsh environment. The electrical layout of the module was also optimized using a modeling and simulation approach, in order to minimize the device parasitic ringing during high-speed switching. Finally, the static and switching performances of the fabricated module were tested, and the 200 °C continuous operation of the SiC MOSFETs was verified.

Analytical Loss Model of High Voltage GaN HEMT in Cascode Configuration

Abstract: This paper presents an accurate analytical model to calculate the power loss of a high voltage Gallium Nitride high electron mobility transistor (GaN HEMT) in cascode configuration. The proposed model considers the package and PCB parasitic inductances, the nonlinearity of the junction capacitors, and the transconductance of the cascode GaN transistor. The switching process is illustrated in detail, including the interaction of the low voltage Si MOSFET and the high voltage GaN HEMT in cascode configuration. The switching loss is obtained by solving the equivalent circuits during the switching transition. The analytical results show that the turn-on loss dominates in hard-switching conditions while the turn-off loss is negligible, due to the intrinsic current source driving mechanism. The accuracy of the proposed model is validated by numerous experimental results. The results of both the analytical model and experiments suggest that soft-switching is critical for high voltage GaN in high-frequency high-efficiency applications.

Investigations of 600-V GaN HEMT and GaN Diode for Power Converter Applications

Abstract: Power switching devices based on wide bandgap semiconductor materials, such as silicon carbide (SiC) and gallium nitride (GaN) offer superior performance such as low switching and conduction losses, high voltage, high frequency, and high temperature operation. In this paper, a 600-V GaN switch and a 600-V GaN diode were tested in detail to understand the GaN device capabilities with respect to equivalent silicon-based devices such as IGBT and MOSFET. Detailed experimental loss models are developed and compared with datasheet models. Experimental setup of different power converters such as boost, buck-boost, and half-bridge inverter and associated comparative experimental results are presented. This paper also presents the investigations into the effectiveness of using GaN devices and higher switching frequencies in reducing the total size and cost of power conversion equipment such as an online UPS system.

On the mobility and contact resistance evaluation for transistors based on MoS2 or two-dimensional semiconducting atomic crystals

Abstract: Contact resistance (Rc) can substantially obscure the extracted mobility based on standard transconductance or two-point conductance measurements of field-effect devices especially for low density of states materials such as MoS2 or similar atomic crystals. Currently, there exists a pressing need for a routine technique that can decouple mobility extraction from Rc. By combining experiments and analysis, we show that the Y-function method offers a robust route for evaluating the low-field mobility, threshold voltage and Rc even when the contact is a Schottky-barrier as is common in two-dimensional transistors. In addition, an independent modified transfer length method evaluation corroborates the Y-function analysis.

C-H surface diamond field effect transistors for high temperature (400 °C) and high voltage (500 V) operation

Abstract: By forming a highly stable Al2O3 gate oxide on a C-H bonded channel of diamond, high-temperature, and high-voltage metal-oxide-semiconductor field-effect transistor (MOSFET) has been realized. From room temperature to 400 °C (673 K), the variation of maximum drain-current is within 30% at a given gate bias. The maximum breakdown voltage (VB) of the MOSFET without a field plate is 600 V at a gate-drain distance (LGD) of 7 μm. We fabricated some MOSFETs for which VB/LGD > 100 V/μm. These values are comparable to those of lateral SiC or GaN FETs. The Al2O3 was deposited on the C-H surface by atomic layer deposition (ALD) at 450 °C using H2O as an oxidant. The ALD at relatively high temperature results in stable p-type conduction and FET operation at 400 °C in vacuum. The drain current density and transconductance normalized by the gate width are almost constant from room temperature to 400 °C in vacuum and are about 10 times higher than those of boron-doped diamond FETs.

13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-V MIN applications

Abstract: FinFET technology has become a mainstream technology solution for post-20nm CMOS technology [1], since it has superior short-channel effects, better sub-threshold slope and reduced random dopant fluctuation. Therefore, it is expected to achieve better performance with lower SRAM VDDMIN. However, the quantized sizing of the channel width and length has drawbacks for conventional 6T-SRAM bitcell scaling. To minimize the bitcell area of the high-density SRAM bitcell, the number of fins (setting the channel width, W) of the pull-up PMOS (PU), passgate NMOS (PG) and pull-down NMOS (PD) transistors must be selected as 1:1:1. Since PU, PG, and PD have the same channel length (L), the ratio in geometry between the PU transistor and the PG transistor is equal to one. With the process variations, the strength of PU transistor can be much stronger than the PG transistor. A stronger PU transistor increases read stability of the SRAM bitcell but it degrades the write margin significantly and results in worse write-VDDMIN issue. Figure 13.5.1(a) shows a contention condition between PU and PG transistors of a 6T-SRAM bitcell for the write operation. During the write operation, the PU transistor impedes the ability of the PG transistor to pull the storage node (S) from VDD to ground. The bitcell may suffer a write failure at the stronger PU with weaker PG condition caused by the device variations. Two techniques have been proposed to improve the high density SRAM bitcell write VDDMIN: 1) negative bit-line voltage (NBL) to increase the strength of PG transistor and 2) lower cell VDD (LCV) to weaken PU transistor strength [1-5]. Compared to the conventional techniques, this work develops a suppressed-coupling-signal negative bitline (SCS-NBL) scheme and a write-recovery-enhancement lower-cell-VDD (WRE-LCV) scheme for write assist without the concern of reliability at higher VDD operating region. A comparison of the effectiveness of the two design techniques is also performed. Figure 13.5.1(b) shows the layout view of the high-density 6T-SRAM bit-cell with 0.07μm2 area in a 16nm high-k metal-gate FinFET technology. To minimize area, we set the geometric ratio of PU, PG, and PD transistors all equal to one. With the two developed write-assist circuits, the overall VDDMIN improvement can be over 300mV in a 128Mb SRAM test-chip.

Instability in Half-Bridge Circuits Switched With Wide Band-Gap Transistors

Abstract: Wide band-gap (WBG) field-effect devices are known to provide a system-level performance benefit compared to silicon devices when integrated into power electronics applications. However, the near-ideal features of these switching devices can also introduce unexpected behavior in practical systems due to the presence of parasitic elements. The occurrence of self-sustained oscillation is one such behavior that has not received adequate study in the literature. This paper provides an analytical treatment of this phenomenon by casting the switching circuit as an unintentional negative resistance oscillator. This treatment utilizes an established procedure from the oscillator design literature and applies it to the problem of power circuit oscillation. A simulation study is provided to identify the sensitivity of the model to various parameters, and the predictive value of the model is confirmed by experiment involving two exemplary WBG devices: a SiC vertical-channel JFET and a SiC lateral-channel MOSFET. The results of this study suggest that susceptibility to self-sustained oscillation is correlated to the available power density of the device relative to the parasitic elements in the circuit, for which wide band-gap devices, to include SiC and GaN transistors, are in a class approaching that of the radio frequency domain.

Dynamic and static behavior of packaged silicon carbide MOSFETs in paralleled applications

Abstract: There is little work done to study the nuances related to paralleling the higher speed SiC Mosfet devices when compared to Si devices. This paper deals with the parallel operation of packaged silicon carbide (SiC) MOSFETs. The parameters that affect the static and dynamic current sharing behavior of the devices have been studied. We also investigate the sensitivity of those parameters to the junction temperature of the devices. The case temperature difference for paralleled MOSFETs has been experimentally measured on a SEPIC converter for different gate driver resistance and different switching frequency, the results show the current and temperature can be well balanced for the latest generation of SiC MOSFETs with low gate driver resistance.

Experimental and Analytical Performance Evaluation of SiC Power Devices in the Matrix Converter

Abstract: With the commercial availability of SiC power devices, their acceptance is expected to grow in consideration of the excellent low switching loss, high-temperature operation, and high-voltage rating capabilities of these devices. This paper presents the comparative performance evaluation of different SiC power devices in the matrix converter at various temperatures and switching frequencies. To this end, first, gate or base drive circuits for normally-off SiC JFET, SiC MOSFET, and SiC BJT by taking into account the special demands for these devices are presented. Then, four two-phase to one-phase matrix converters are built with different Si and SiC power devices to measure the switching waveforms and power losses for them at different temperatures and switching frequencies. Based on the measured data, four different SiC and Si power devices are compared in terms of switching times, conduction and switching losses, and efficiency at different temperatures and switching frequencies. Furthermore, a theoretical investigation of the power losses of the three-phase matrix converter with normally-off SiC JFET, SiC MOSFET, SiC BJT, and Si IGBT is described. The power losses estimation indicates that a 7-kW matrix converter would potentially have an efficiency of approximately 94% in high switching frequency if equipped with SiC devices.

Low-Voltage Steep Turn-On pMOSFET Using Ferroelectric High- $\kappa$ Gate Dielectric

Abstract: Power consumption is the most difficult challenge for CMOS integrated circuits. Here, we demonstrate experimentally a novel steep turn-on pMOSFET for low-voltage operation for the first time, which exhibits 5-60 mV/decade SS, wide voltage range for , sturdy SS at 85°C, faster transistor turn-on at above threshold voltage, and lower off-state leakage by greater than three orders of magnitude. Such improved leakage current is crucial to decrease the OFF-state leakage current in sub-1X nm CMOS. This was achieved using ferroelectric high-κ ZrHfO gate dielectric pMOSFET.

High Temperature Stability and the Performance Degradation of SiC MOSFETs

Abstract: SiC MOSFET devices have great potentials in future high temperature power electronics applications due to their possible higher thermal runaway temperature compared with other SiC power semiconductor devices. In this paper, the high temperature stability of SiC MOSFETs is investigated by experiments and Saber simulations. The maximum steady-state junction temperature of the SiC MOSFET is measured to exceed 250 °C and saber simulations based on experimental model estimate that the thermal runaway temperatures are close to 300 °C. In addition, performance degradation of SiC MOSFETs during high-temperature operation is observed and discussed. Experimental results show that the degradation happens during both the high temperature storage (maximum 5% RON increment) and high temperature operation process (maximum 15% RON increment). The degradations are found to recover to a close-to-initial level after 1 h recovery time at the room temperature.

Low-Leakage-Current DRAM-Like Memory Using a One-Transistor Ferroelectric MOSFET With a Hf-Based Gate Dielectric

Abstract: The power consumption of capacitor leakage current, increase of the capacitor aspect ratio, and lack of higher dielectric constant (κ) material are the difficult challenges to downscaling dynamic random access memory (DRAM). This letter reports a new one-transistor ferroelectric-MOSFET (1T FeMOS) device that displays DRAM functions of a 5 ns switching time, 1012 on/off endurance cycles, and 30 times on/off retention windows at 5 s and 85 °C. A simple 1T process and a considerably low OFF-state leakage of 3×10-12 A/μm were achieved. This novel device was achieved by applying ferroelectric ZrHfO gate dielectric to a p-MOSFET, which is fully compatible with existing high-κ CMOS processing.

Gate Oxide Degradation of SiC MOSFET in Switching Conditions

Abstract: Under realistic switching conditions, SiC MOSFETs reliability issues remain as a challenge that requires further investigation. In this letter, a specific aging test has been developed to monitor and characterize the electrical parameters of the SiC MOSFET. This allows estimations of the health state and predictions of the remaining lifetime prior to its failure. The gate leakage current seems to be a relevant runaway parameter just before failure. This leakage indicates deterioration of the gate structure. This hypothesis has been validated through analysis of scanning electron microscopy pictures, with a focused ion beam cut showing cracks within the polysilicon.

Improved Modeling of Medium Voltage SiC MOSFET Within Wide Temperature Range

Abstract: An improved model of medium voltage (1200 V) silicon carbide (SiC) MOSFET based on PSpice is proposed in this paper, which is suitable for wide temperature range applications especially at low temperature. The static characteristics of SiC MOSFET are described by introducing temperature-dependent voltage source and current source. The effect of negative turn-off gate drive voltage is also taken into account in the modeling. In order to reflect the low-temperature characteristics of SiC MOSFET accurately, low temperature (-25 °C) measurements are carried out, which provide the modeling basis. The determinations of key parameters in the model are analyzed in detail, including the on-state resistor, internal gate resistor, temperature dependent sources, and some capacitors. The proposed model is verified by the experimental tests on a buck converter prototype at different input voltages, input currents, and temperatures. Simulation results on the proposed model coincide well with the experimental test results, in terms of switching waveforms and power losses even at low temperature (-25 °C). These results demonstrate that the proposed model exhibits high accuracy within wide temperature range.

Challenges for energy efficient wide band gap semiconductor power devices

Abstract: Wide band gap semiconductors, and in particular silicon carbide (4H-SiC) and gallium nitride (GaN), are very promising materials for the next generation of power electronics, to guarantee an improved energy efficiency of devices and modules. As a matter of fact, in the last decade intensive academic and industrial research efforts have resulted in the demonstration of both 4H-SiC MOSFETs and GaN HEMTs exhibiting VB2/Ron performances well beyond the silicon limits. In this paper, some of the present scientific challenges for SiC and GaN power devices technology are reviewed. In particular, the topics selected in this work will be the SiO2/SiC interface passivation processes to improve the channel mobility in 4H-SiC MOSFETs, the current trends for gate dielectrics in GaN technology and the viable routes to obtain normally-off HEMTs.

Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells

Abstract: The emergence of spin-transfer torque magnetic RAM (STT-MRAM) as a leading candidate for future high-performance nonvolatile memory has led to increased research interest. Current STT-MRAM technology faces several major obstacles in attaining its potential. One of the major issues is in the design of 1T-1MTJ STT-MRAM bit-cells under process variations: the bit-cells need to be significantly upsized to improve bit-cell failure, resulting in increased bit-cell area and power dissipation. In this paper, we analyze four circuit-level solutions that enable smaller 1T-1MTJ STT-MRAM bit-cells with improved yield, namely, bit-line voltage boosting, word-line voltage boosting, access transistor body biasing, and an applied external magnetic field. Results from simulation using 45-nm bulk CMOS access transistor and 40-nm magnetic tunneling junction technology show that word-line voltage boosting can be the best failure mitigation technique. Bit-cells designed with word-line boosting for write has a bit-cell area reduced by > 75% at iso-failure probability, compared to bit-cells without any failure mitigation technique. When bit-cell failure probability is optimized instead, 5 Oe of applied external magnetic field assisted write reduces power consumption by 15% , compared to bit-cells designed without failure mitigation techniques.

Compact Model for Short-Channel Junctionless Accumulation Mode Double Gate MOSFETs

Abstract: A 2-D closed form, analytical compact model for long- and short-channel junctionless accumulation mode double gate MOSFETs is presented. The physics-based 2-D model for the potential is derived with the help of Poisson's equation and the conformal mapping technique by Schwarz-Christoffel. From this closed-form solution, we derive simple equations for the calculation of the threshold voltage VT and subthreshold slope S. Using Lambert's W-function and a smoothing function for the transition between the depletion and accumulation regions, a unified charge model valid for all operating regimes is developed. Dependencies between the physical device parameters and their impact on the device performance are worked out. A comparison of our 2-D physics-based compact model is done versus 2-D technology computer-aided design (TCAD) Sentaurus simulation data.

High mobility field effect transistor based on BaSnO3 with Al2O3 gate oxide

Abstract: We fabricated an n-type accumulation-mode field effect transistor based on BaSnO3 transparent perovskite semiconductor, taking advantage of its high mobility and oxygen stability. We used the conventional metal-insulator-semiconductor structures: (In,Sn)2O3 as the source, drain, and gate electrodes, Al2O3 as the gate insulator, and La-doped BaSnO3 as the semiconducting channel. The Al2O3 gate oxide was deposited by atomic layer deposition technique. At room temperature, we achieved the field effect mobility value of 17.8 cm2/Vs and the Ion/Ioff ratio value higher than 105 for VDS = 1 V. These values are higher than those previously reported on other perovskite oxides, in spite of the large density of threading dislocations in the BaSnO3 on SrTiO3 substrates. However, a relatively large subthreshold swing value was found, which we attribute to the large density of charge traps in the Al2O3 as well as the threading dislocations.

High gain, low noise, fully complementary logic inverter based on bi-layer WSe2 field effect transistors

Abstract: In this article, first, we show that by contact work function engineering, electrostatic doping and proper scaling of both the oxide thickness and the flake thickness, high performance p- and n-type WSe2 field effect transistors (FETs) can be realized. We report record high drive current of 98 μA/μm for the electron conduction and 110 μA/μm for the hole conduction in Schottky barrier WSe2 FETs. Then, we combine high performance WSe2 PFET with WSe2 NFET in double gated transistor geometry to demonstrate a fully complementary logic inverter. We also show that by adjusting the threshold voltages for the NFET and the PFET, the gain and the noise margin of the inverter can be significantly enhanced. The maximum gain of our chemical doping free WSe2 inverter was found to be ∼25 and the noise margin was close to its ideal value of ∼2.5 V for a supply voltage of VDD = 5.0 V.

A 3600 V/80 A Series--Parallel-Connected Silicon Carbide MOSFETs Module With a Single External Gate Driver

Abstract: In this paper, a new series connection topology is introduced for silicon carbide (SiC) MOSFETs. In the topology, with a single external gate drive, three series-connected SiC MOSFETs are synchronously driven. The operating principle of the proposed topology is analyzed and presented. In order to improve the current capability of the module, parallel connection of two SiC devices are also demonstrated. A 3600 V/80 A series-parallel-connected configuration with three rows in a series and two branches in parallel is constructed with six 1200 V/40 A discrete SiC MOSFETs. Switching behavior of the configuration is completed at 2300 V/78 A. Experimental results verify the validity and feasibility of the proposed topology. Analysis based on experimental results for the circuit switching speed and switching losses is given. Finally, such a series-parallel-connected circuit is integrated in a SiC MOSFETs module, capable of 3600 V/80 A. The switching characteristics of the module are compared to the discrete configuration.

Spin Transport in Nondegenerate Si with a Spin MOSFET Structure at Room Temperature

Abstract: Although the traditional metal-on-semiconductor field-effect transistor (MOSFET) has been a workhorse in information processing for decades, we must now consider its successor. To make spintronics a reality, by analogy we need a ``spin MOSFET''. The authors demonstrate room-temperature operation of just such a device, in which a flow of spin angular momentum in nondegenerate silicon is controlled by an external gate voltage.

High-Frequency Gate-All-Around Vertical InAs Nanowire MOSFETs on Si Substrates

Abstract: We demonstrate a vertical InAs nanowire MOSFET integrated on Si substrate with an extrinsic peak cut-off frequency of 103 GHz and a maximum oscillation frequency of 155 GHz. The transistor has a transconductance of 730 mS/mm and is based on arrays of nanowires with gate-all-around and high-κ gate dielectric. Furthermore, small-signal modeling shows a ~80% reduction of the total parasitic gate capacitance when the metal pad overlap in the transistors is reduced through additional patterning.

Cofabrication of Vacuum Field Emission Transistor (VFET) and MOSFET

Abstract: Co-fabrication of a nanoscale vacuum field emission transistor (VFET) and a metal-oxide-semiconductor field effect transistor (MOSFET) is demonstrated on a silicon-on-insulator wafer. The insulated-gate VFET with a gap distance of 100 nm is achieved by using a conventional 0.18-μm process technology and subsequent photoresist ashing process. The VFET shows a turn-on voltage of 2 V at a cell current of 2 nA and a cell current of 3 μA at the operation voltage of 10 V with an ON/OFF current ratio of 10 $^{4}$ . The gap distance between the cathode and anode in the VFET is defined to be less than the mean free path of electrons in air, and consequently, the operation voltage is reduced to be less than the ionization potential of air molecules. This allows the relaxation of the vacuum requirement. The present integration scheme can be useful as it combines the advantages of both structures on the same chip.

A Comparative Performance Study of a 1200 V Si and SiC MOSFET Intrinsic Diode on an Induction Heating Inverter

Abstract: This paper presents a comparison of the behavior of the intrinsic diode of silicon (Si) and silicon carbide (SiC) MOSFETs. The study was done for 1200 V Si and SiC MOSFETs. The data sheet from manufacturers shows the characteristics of MOSFET' intrinsic diode when gate source voltage (VGS) is 0 V. There are applications where the MOSFET' intrinsic diode is used while VGS is different than 0 V. One of these applications is induction heating, where depending on the load and the regulation system, the diode can conduct a significant part of the inverter current. In most applications which use the MOSFET' intrinsic diode, the turn ON of the intrinsic diode happens at VGS = 0 V. After a blanking time, the MOSFET' gate is activated waiting for the direction change of current in the circuit. Therefore, most of the current through the MOSFET' intrinsic diode occurs with a VGS different of 0 V. This paper shows the direct output characterization of Si and SiC MOSFET' intrinsic diode under different gate voltages. The gate resistor (RG) is an important parameter of the characterization. Depending on the input capacitance of the Si or SiC MOSFET, different RG are needed. The turn-on and turn-off behaviors are obtained when RG is optimized for each Si and SiC MOSFET. This has result in the turn-off robustness of intrinsic diode with optimum RG. This paper presents a surprising result for the reverse characteristic of Si and SiC MOSFETs for the same current at different VGS. The technology of Si MOSFET has different behavior depending on the manufacturer. The technology of SiC MOSFET presents a very similar behavior to low-voltage Si MOSFETs.

An All-SiC High-Frequency Boost DC–DC Converter Operating at 320 °C Junction Temperature

Abstract: This letter presents the design, prototype development, operation, and testing of an 800 kHz, 1 kW, 800 V output boost dc–dc converter module that integrates SiC MOSFET and SiC Schottky diode die. It is observed that when the device loss is dominated by switching loss, the steady-state junction temperature of SiC MOSFET can reach as high as 320 °C. This is the highest self-heated junction temperature operation of SiC power devices under room temperature ambient reported in the literature. The high-frequency switching characteristics and high-temperature thermal reliability of the assessed converter are evaluated in detail. A solder-molten phenomenon during high junction temperature operation is detected and the die-attachment material is thus improved to enhance the high-temperature thermal reliability of the converter module. This study shows that the high-frequency capability of a gate driver and high-temperature die-attachment technology can be limiting factors preventing SiC power devices from operating at higher junction temperatures.

Extension of Planar Bulk n-Channel MOSFET Scaling With Oxygen Insertion Technology

Abstract: An experimental and simulation study of short- channel planar bulk nMOSFET performance enhancement achieved with oxygen insertion technology is presented. The benefits of this technology for low-power digital logic circuits make it a promising evolutionary approach to extend bulk MOSFET scaling. Index Terms— Low-power (LP) logic circuits, mobility enhancement, oxygen insertion (OI), super-steep retrograde well (SSRW), variability.

Ballistic performance comparison of monolayer transition metal dichalcogenide MX2 (M = Mo, W; X = S, Se, Te) metal-oxide- semiconductor field effect transistors

Abstract: We study the transport properties of monolayer MX2 (M = Mo, W; X = S, Se, Te) n- and p-channel metal-oxide-semiconductor field effect transistors (MOSFETs) using full-band ballistic non-equilibrium Green's function simulations with an atomistic tight-binding Hamiltonian with hopping potentials obtained from density functional theory. We discuss the subthreshold slope, drain-induced barrier lowering (DIBL), as well as gate-induced drain leakage (GIDL) for different monolayer MX2 MOSFETs. We also report the possibility of negative differential resistance behavior in the output characteristics of nanoscale monolayer MX2 MOSFETs.