Showing papers on "MOSFET published in 2015"

A subthermionic tunnel field-effect transistor with an atomically thin channel.

Abstract: A new type of device, the band-to-band tunnel transistor, which has atomically thin molybdenum disulfide as the active channel, operates in a fundamentally different way from a conventional silicon (MOSFET) transistor; it has turn-on characteristics and low-power operation that are better than those of state-of-the-art MOSFETs or any tunnelling transistor reported so far. Traditional transistor technology is fast approaching its fundamental limits, and two-dimensional semiconducting materials such as molybdenum disulfide (MoS2) are seen as possible replacements for silicon in a next generation of high-density, lower-power chip electronics. A particularly promising prospect is their potential in band-to-band tunnel transistors, which operate in a fundamentally different way from conventional silicon (MOSFET) transistors. So far, few such devices with overall characteristics better than silicon transistors have been demonstrated. Now Kaustav Banerjee et al. have built a tunnel transistor by making a vertical structure with atomically thin MoS2 as the active channel and germanium as the source electrode. It has turn-on characteristics and low-power operation that are better than those of existing silicon transistors, and the results will be of interest in a range of electronic applications including low-power integrated circuits, as well as ultra-sensitive bio sensors or gas sensors. The fast growth of information technology has been sustained by continuous scaling down of the silicon-based metal–oxide field-effect transistor. However, such technology faces two major challenges to further scaling. First, the device electrostatics (the ability of the transistor’s gate electrode to control its channel potential) are degraded when the channel length is decreased, using conventional bulk materials such as silicon as the channel. Recently, two-dimensional semiconducting materials1,2,3,4,5,6,7 have emerged as promising candidates to replace silicon, as they can maintain excellent device electrostatics even at much reduced channel lengths. The second, more severe, challenge is that the supply voltage can no longer be scaled down by the same factor as the transistor dimensions because of the fundamental thermionic limitation of the steepness of turn-on characteristics, or subthreshold swing8,9. To enable scaling to continue without a power penalty, a different transistor mechanism is required to obtain subthermionic subthreshold swing, such as band-to-band tunnelling10,11,12,13,14,15,16. Here we demonstrate band-to-band tunnel field-effect transistors (tunnel-FETs), based on a two-dimensional semiconductor, that exhibit steep turn-on; subthreshold swing is a minimum of 3.9 millivolts per decade and an average of 31.1 millivolts per decade for four decades of drain current at room temperature. By using highly doped germanium as the source and atomically thin molybdenum disulfide as the channel, a vertical heterostructure is built with excellent electrostatics, a strain-free heterointerface, a low tunnelling barrier, and a large tunnelling area. Our atomically thin and layered semiconducting-channel tunnel-FET (ATLAS-TFET) is the only planar architecture tunnel-FET to achieve subthermionic subthreshold swing over four decades of drain current, as recommended in ref. 17, and is also the only tunnel-FET (in any architecture) to achieve this at a low power-supply voltage of 0.1 volts. Our device is at present the thinnest-channel subthermionic transistor, and has the potential to open up new avenues for ultra-dense and low-power integrated circuits, as well as for ultra-sensitive biosensors and gas sensors18,19,20,21.

Gate Oxide Reliability Issues of SiC MOSFETs Under Short-Circuit Operation

Abstract: Silicon-Carbide (SiC) MOSFETs, due to material properties, are designed with smaller thickness in the gate oxide and a higher electric field compared to Si MOSFETs. Consequently, the SiC MOSFETs have a worse reliability which causes higher leakage currents during instantaneous abnormal operating conditions. This paper investigates the reliability issues of the SiC MOSFET gate oxide under standard short-circuit test conditions. In this paper, 1200-V SiC MOSFETs are newly modeled, and also their short-circuit sustainability (tolerance) have been studied at different drain-source and gate-source voltages. A hardware tester circuit was designed and developed to test the devices under such extreme circuit conditions. Then, the gate reliability of SiC MOSFET devices have been compared to that of Si power devices of similar ratings. The results reveal a higher reduction in the instantaneous gate-source voltage of SiC MOSFETs compared to that of Si devices under the same operating conditions. The gate-voltage reduction phenomenon results from the higher leakage currents through the gate. Furthermore, it was found that the gate-source voltage reduction during the test depends on the gate structures. The gate voltage reduction of SiC MOSFETs with planar gate is higher than that of MOSFETs with shield planar gate. As the pulse duration increases in short-circuit tests, the leakage current in the gate-source of SiC devices increases. The results show that even though the SiC MOSFETs are very capable of processing long pulses and high power in the drain-source, the gate-source side is highly degraded by these pulses in the test. Moreover, whenever a small number of the short-circuit tests are applied, the gate structure of SiC MOSFETs becomes broken while the drain-source is still able to block the dc-link voltage. The paper concludes that the short-circuit reliability of the gate was found to be worse compared with commercial Si devices with similar rating.

Evaluation of Gallium Nitride Transistors in High Frequency Resonant and Soft-Switching DC–DC Converters

Abstract: The emergence of gallium nitride (GaN)-based power devices offers the potential to achieve higher efficiencies and higher switching frequencies than possible with mature silicon (Si) power MOSFETs. In this paper, we will evaluate the ability of gallium nitride transistors to improve efficiency and output power density in high frequency resonant and soft-switching applications. To experimentally verify the benefits of replacing Si MOSFETs with enhancement mode GaN transistors (eGaNFETs) in a high frequency resonant converter, 48–12 V unregulated isolated bus converter prototypes operating at a switching frequency of 1.2 MHz and an output power of up to 400 W are compared using Si and GaN power devices.

The Impact of Nonlinear Junction Capacitance on Switching Transient and Its Modeling for SiC MOSFET

Abstract: The nonlinear junction capacitances of power devices are critical for the switching transient, which should be fully considered in the modeling and transient analysis, especially for high-frequency applications. The silicon carbide (SiC) MOSFET combined with SiC Schottky Barrier Diode (SBD) is recognized as the proposed choice for high-power and high-frequency converters. However, in the existing SiC MOSFET models only the nonlinearity of gate-drain capacitance is considered meticulously, but the drain–source capacitance, which affects the switching commutation process significantly, is generally regarded as constant. In addition, the nonlinearity of diode junction capacitance is neglected in some simplified analysis. Experiments show that without full consideration of nonlinear junction capacitances, some significant deviations between simulated and measured results will emerge in the switching waveforms. In this paper, the nonlinear characteristics of drain–source capacitance in SiC MOSFET are studied in detail, and the simplified modeling methods for engineering applications are presented. On this basis, the SiC MOSFET model is improved and the simulation results with improved model correspond with the measured results much better than before, which verify the analysis and modeling.

3DVLSI with CoolCube process: An alternative path to scaling

Abstract: 3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm2. This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.

A High-Efficiency MOSFET Transformerless Inverter for Nonisolated Microinverter Applications

Abstract: State-of-the-art low-power-level metal-oxide-semiconductor field-effect transistor (MOSFET)-based transformerless photovoltaic (PV) inverters can achieve high efficiency by using latest super junction MOSFETs. However, these MOSFET-based inverter topologies suffer from one or more of these drawbacks: MOSFET failure risk from body diode reverse recovery, increased conduction losses due to more devices, or low magnetics utilization. By splitting the conventional MOSFET-based phase leg with an optimized inductor, this paper proposes a novel MOSFET-based phase leg configuration to minimize these drawbacks. Based on the proposed phase leg configuration, a high efficiency single-phase MOSFET transformerless inverter is presented for the PV microinverter applications. The pulsewidth modulation (PWM) modulation and circuit operation principle are then described. The common-mode and differential-mode voltage model is then presented and analyzed for circuit design. Experimental results of a 250 W hardware prototype are shown to demonstrate the merits of the proposed transformerless inverter on nonisolated two-stage PV microinverter application.

Analog Circuit Design Using Tunnel-FETs

Abstract: Tunnel-FET (TFET) is a major candidate for beyond-CMOS technologies. In this paper, the properties of the TFETs that affect analog circuit design are studied. To demonstrate how TFETs can enhance the performance or change the topology of the analog circuits, several building blocks such as operational transconductance amplifiers (OTAs), current mirrors, and track-and-hold circuits are examined. It is shown that TFETs are promising for low-power and low-voltage designs, wherein transistors are biased at low-to-moderate current densities. Comparing 14-nm III–V TFET-based OTAs with Si-MOSFET-based designs demonstrates up to 5 times reduction in the power dissipation of the amplifiers and more than an order of magnitude increase in their DC voltage gain. The challenges and opportunities that come with the special characteristics of TFETs, namely asymmetry, ambipolar behavior, negative differential resistance, and superlinear operation are discussed in detail.

Overview of 1.2kV – 2.2kV SiC MOSFETs targeted for industrial power conversion applications

Abstract: This paper presents the latest 1.2kV–2.2kV SiC MOSFETs designed to maximize SiC device benefits for high-power, medium voltage power conversion applications. 1.2kV, 1.7kV and 2.2kV devices with die size of 4.5mm × 4.5mm were fabricated, exhibiting room temperature on-resistances of 34mOhm, 39mOhm and 41mOhm, respectively. The ability to safely withstand single-pulse avalanche energies of over 17J/cm2 is demonstrated. Next, the 1.7kV SiC MOSFETs were used to fabricate half-bridge power modules. The module typical onresistance was 7mOhm at Tj=25°C and 11mOhm at 150°C. The module exhibits 9mJ turn-on and 14mJ turn-off losses at Vds=900V, Id=400A. Validation of GE's SiC MOSFET performance advantages was done through continuous buck-boost operation with three 1.7kV modules per phase leg exhibiting 99.4% efficiency. Device ruggedness and tolerance to terrestrial cosmic radiation was evaluated. Experimental results show that higher voltage devices (2.2kV and 3.3kV) are more susceptible to cosmic radiation, requiring up to 45% derating in order to achieve module failure rate of 100 FIT, while 1.2kV MOSFETs require only 25% derating to deliver similar FIT rate. Finally, the feasibility of medium voltage power conversion based on series connected 1.2kV SiC MOSFETs with body diode is demonstrated.

Characterization and Enhancement of High-Voltage Cascode GaN Devices

Abstract: Gallium nitride (GaN) devices are gathering momentum, with a number of recent market introductions for a wide range of applications such as point-of-load converters, OFF-line switching power supplies, battery chargers, and motor drives. This paper studies the basic characteristics of a 600 V cascode GaN switch, such as voltage distribution during the turn-ON and turn-OFF transition. The switching loss mechanism of the cascode GaN switch is analyzed in detail, including the impact of the package parasitic inductance in both hard- and soft-switching modes. A soft-switching 5 MHz boost converter is developed and shows the advantages and the potential of the cascode GaN.

Threshold Voltage Instability in 4H-SiC MOSFETs With Phosphorus-Doped and Nitrided Gate Oxides

Abstract: Threshold voltage instability was investigated for 4H-SiC MOSFETs with phosphorus-doped (POCl3-annealed) and nitrided (NO-annealed) gate oxides. Threshold voltage shift observed in the bidirectional drain current–gate voltage characteristics was evaluated using various gate voltage sweeps at room and elevated temperatures up to 200 °C. The threshold voltage shift was also studied after applying positive and negative bias-temperature stress. Two types of MOSFETs showed different instability characteristics, depending on gate biases and temperatures. These features were found to originate from the difference in trap density and trap location at/near the oxide/SiC interface and in the oxide. It is apparent that the oxide traps in phosphorus-doped oxides and near-interface traps in nitrided oxides are the main origin of the threshold voltage instability via capture and emission (in the case of oxide traps, only capture) of both electrons and holes.

Future of nano CMOS technology

Abstract: Although Si MOS devices have dominated the integrated circuit applications over the four decades, it has been anticipated that the development of CMOS would reach its limits after the next decade because of the difficulties in the technologies for further downscaling and also because of some fundamental limits of MOSFETs. However, there have been no promising candidates yet, which can replace Si MOSFETs with better performance with low cost. Thus, for the moment, it seems that we have to stick to the Si MOSFET devices until their end. The downsizing is limited by the increase of off-leakage current between source and drain. In order to suppress the off-leakage current, multi-gate structures (FinFET, Tri-gate, and Si-nanowire MOSFETs) are replacing conventional planar MOSFETs, and continuous innovation of high-k/metal gate technologies has enabled EOT scaling down to 0.9 nm in production. However, it was found that the multi-gate structures have a future big problem of significant conduction reduction with decrease in fin width. Also it is not easy to further decrease EOT because of the mobility and reliability degradation. Furthermore, the development of EUV (Extremely Ultra-Violet) lithography, which is supposed to be essential for sub-10 nm lithography, delays significantly because of insufficient illumination intensity for production. Thus, it is now expected that the reduction rate of the gate length, which has a strong influence on the off-leakage current, will become slower in near future.

Characterization of a Silicon IGBT and Silicon Carbide MOSFET Cross-Switch Hybrid

Abstract: A parallel arrangement of a silicon (Si) IGBT and a silicon carbide (SiC) MOSFET is experimentally demonstrated. The concept referred to as the cross-switch (XS) hybrid aims to reach optimum power device performance by providing low static and dynamic losses while improving the overall electrical and thermal properties due to the combination of both the bipolar Si IGBT and unipolar SiC MOSFET characteristics. For the purpose of demonstrating the XS hybrid, the parallel configuration is implemented experimentally in a single package for devices rated at 1200 V. Test results are obtained to validate this approach with respect to the static and dynamic performance when compared to a full Si IGBT and a full SiC MOSFET reference devices having the same power ratings as for the XS hybrid samples.

An Analysis of the Switching Performance and Robustness of Power MOSFETs Body Diodes: A Technology Evaluation

Abstract: The tradeoff between the switching energy and electro-thermal robustness is explored for 1.2-kV SiC MOSFET, silicon power MOSFET, and 900-V CoolMOS body diodes at different temperatures. The maximum forward current for dynamic avalanche breakdown is decreased with increasing supply voltage and temperature for all technologies. The CoolMOS exhibited the largest latch-up current followed by the SiC MOSFET and silicon power MOSFET; however, when expressed as current density, the SiC MOSFET comes first followed by the CoolMOS and silicon power MOSFET. For the CoolMOS, the alternating p and n pillars of the superjunctions in the drift region suppress BJT latch-up during reverse recovery by minimizing lateral currents and providing low-resistance paths for carriers. Hence, the temperature dependence of the latch-up current for CoolMOS was the lowest. The switching energy of the CoolMOS body diode is the largest because of its superjunction architecture which means the drift region have higher doping, hence more reverse charge. In spite of having a higher thermal resistance, the SiC MOSFET has approximately the same latch-up current while exhibiting the lowest switching energy because of the least reverse charge. The silicon power MOSFET exhibits intermediate performance on switching energy with lowest dynamic latching current.

Characteristics of 600, 1200, and 3300 V Planar SiC-MOSFETs for Energy Conversion Applications

Abstract: SiC-MOSFETs provide superior performance for next generation power electronics systems. High threshold voltage 600 V SiC-MOSFETs were realized utilizing a reoxidation process, which drastically improves a tradeoff between an ON-resistance and a threshold voltage. Low-loss SiC-MOSFETs with a 1200 V/100-A rating have been developed. Using the developed SiC-MOSFETs, 1200 V/800-A high-power full SiC module with an ON-resistance as low as 2.9 m $\Omega $ at 150 °C was successfully fabricated. The high-power module markedly reduces power loss especially at high carrier frequency. Large-area 3300 V SiC-MOSFETs with an ON-resistance of 52 m $\Omega $ at 175 °C exhibit an adequate reverse bias safe operating area and 3300 V SiC-MOSFETs screened by applying a body diode current stress show stable characteristics under a continuous current through their body diode for 1000 h.

Understanding switching losses in SiC MOSFET: Toward lossless switching

Abstract: Due to the limitation in circuit measurements using current and voltage probes, the conventional ways of measuring switching losses lack the physical insight of the complicated witching process in power devices such as the SiC power MOSFET. This paper seeks to have a better understanding of the dynamic turn-on and turn-off processes of the SiC power MOSFET. Using a detailed finite element simulation model in TCAD Sentaurus, a better and accurate understanding of switching losses in SiC MOSFET is obtained. The physical insights during switching process, as well as the impact of gate resistance and common source parasitic inductance are studied. Based on the results obtained in this study, SiC MOSFET can achieve lossless switching for both turn-on and turn-off if certain conditions of its gate drive circuit and load current conditions are met. Therefore this analysis provides a theoretical guidance for high voltage SiC MOSFETs to be used in extremely high switching frequency applications.

A High Temperature Silicon Carbide mosfet Power Module With Integrated Silicon-On-Insulator-Based Gate Drive

Abstract: This paper presents a board-level integrated silicon carbide (SiC) mosfet power module for high temperature and high power density application. Specifically, a silicon-on-insulator (SOI)-based gate driver capable of operating at 200 °C ambient temperature is designed and fabricated. The sourcing and sinking current capability of the gate driver are tested under various ambient temperatures. Also, a 1200 V/100 A SiC mosfet phase-leg power module is developed utilizing high temperature packaging technologies. The static characteristics, switching performance, and short-circuit behavior of the fabricated power module are fully evaluated at different temperatures. Moreover, a buck converter prototype composed of the SOI gate driver and SiC power module is built for high temperature continuous operation. The converter is operated at different switching frequencies up to 100 kHz, with its junction temperature monitored by a thermosensitive electrical parameter and compared with thermal simulation results. The experimental results from the continuous operation demonstrate the high temperature capability of the power module at a junction temperature greater than 225 °C.

Hot Carrier Degradation in Semiconductor Devices

Abstract: Part I: Beyond Lucky Electrons -- From Atoms to Circuits: Theoretical and Empirical Modeling of Hot Carrier Degradation -- The Energy Driven Hot Carrier Model -- Hot-Carrier Degradation in Decananometer -- Physics-based Modeling of Hot-carrier Degradation -- The Spherical Harmonics Expansion Method for Assessing Hot Carrier Degradation -- Recovery from Hot Carrier Induced Degradation Through Temperature Treatment -- Characterization of MOSFET Interface States Using the Charge Pumping Technique -- Part II: CMOS and Beyond -- Channel Hot Carriers in SiGe and Ge pMOSFETs -- Channel Hot Carrier Degradation and Self-Heating Effects in FinFETs -- Characterization and Modeling of High-Voltage LDMOS Transistors -- Compact modelling of the Hot-carrier Degradation of Integrated HV MOSFETs -- Hot-Carrier Degradation in Silicon-Germanium Heterojunction Bipolar Transistors.

Short-circuit evaluation and overcurrent protection for SiC power MOSFETs

Abstract: In this paper, the short-circuit (SC) performance of two different SiC MOSFETs is experimentally investigated for different input voltages, biasing voltages and case temperatures. The measurement results are compared to simulations, and a good agreement is achieved. For fault handling, two different overcurrent protection (OCP) circuits are designed and applied to the SiC MOSFETs. The desaturation method is successfully tested with a hardware solution substituting the blanking time delay. The second method is based on sensing the voltage drop across the parasitic inductance at the source pin. The experimental and simulation results show that both OCP methods have the capability to detect a short circuit condition in the SiC MOSFET within safe SC time avoiding device failure.

TFET-Based Circuit Design Using the Transconductance Generation Efficiency $ {g}_{m}/ {I}_{d}$ Method

Abstract: Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS transistor technologies. In this paper, we: 1) review the perspectives of such devices for low-power high-frequency analog integrated circuit applications (e.g., GHz operation with sub-0.1 mW power consumption); 2) discuss and employ a compact TFET device model in the context of the $g_{m}/I_{d}$ integrated analog circuit design methodology; and 3) compare several proposed TFET technologies for such applications. The advantages of TFETs arise since these devices can operate in the sub-threshold region with larger transconductance-to-current ratio than traditional FETs, which is due to the current turn-on mechanism being interband tunneling rather than thermionic emission. Starting from technology computer-aided design and/or analytical models for Si-FinFETs, graphene nano-ribbon (GNR) TFETs and InAs/GaSb TFETs at the 15-nm gate-length node, as well as InAs double-gate TFETs at the 20-nm gate-length node, we conclude that GNR TFETs might promise larger bandwidths at low-voltage drives due to their high current densities in the sub-threshold region. Based on this analysis and on theoretically predicted properties, GNR TFETs are identified as one of the most attractive field effect transistor technologies proposed-to-date for ultra-low power analog applications.

The fundamental downscaling limit of field effect transistors

Abstract: We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.

Nb-doped single crystalline MoS2 field effect transistor

Abstract: We report on the demonstration of a p-type, single crystalline, few layer MoS2 field effect transistor (FET) using Niobium (Nb) as the dopant. The doping concentration was extracted and determined to be ∼3 × 1019/cm3. We also report on bilayer Nb-doped MoS2 FETs with ambipolar conduction. We found that the current ON-OFF ratio of the Nb-doped MoS2 FETs changes significantly as a function of the flake thickness. We attribute this experimental observation to bulk-type electrostatic effect in ultra-thin MoS2 crystals. We provide detailed analytical modeling in support of our claims. Finally, we show that in the presence of heavy doping, even ultra-thin 2D-semiconductors cannot be fully depleted and may behave as a 3D material when used in transistor geometry. Our findings provide important insights into the doping constraints of 2D materials, in general.

Efficiency Evaluation of the Modular Multilevel Converter Based on Si and SiC Switching Devices for Medium/High-Voltage Applications

Abstract: The modular multilevel converter (MMC) is the most promising converter topology for medium- and high-power applications. One of the main concerns in the operation of the MMC, particularly for high-power applications, is its efficiency, which should be maximized. Silicon Carbide (SiC)-based devices have the potential to provide significant efficiency improvement compared with silicon devices. However, the possibility and impact of using SiC-based devices instead of silicon devices for high-power conversion have not been thoroughly explored. This paper reports on the results obtained from a detailed study to evaluate the performance of MMCs based on medium-voltage SiC MOSFETs and diodes with hybrid MMCs that employ silicon IGBTs and SiC diodes. The results are based on detailed circuit simulations that use simple physics-based circuit models. The study suggests the potential for significant efficiency gain for MMCs based on SiC power devices.

Mixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain

Abstract: In this paper, we identify the level shifter (LS) for voltage up-conversion from the ultralow-voltage regime as a key application domain of tunnel FETs (TFETs). We propose a mixed TFET–MOSFET LS design methodology, which exploits the complementary characteristics of TFET and MOSFET devices. Simulation results show that the hybrid LS exhibits superior dynamic performance at the same static power consumption compared with the conventional MOSFET and pure TFET solutions. The advantage of the mixed design with respect to the conventional MOSFET approach is emphasized when lower voltage signals have to be up-converted, reaching an improvement of the energy-delay product up to three decades. When compared with the full MOSFET design, the mixed TFET–MOSFET solution appears to be less sensitive toward threshold voltage variations in terms of dynamic figures of merit, at the expense of higher leakage variability. Similar results are obtained for four different LS topologies, thus indicating that the hybrid TFET–MOSFET approach offers intrinsic advantages in the design of LS for voltage up-conversion from the ultralow-voltage regime compared with the conventional MOSFET and pure TFET solutions.

Simulation of Phosphorene Field-Effect Transistor at the Scaling Limit

Abstract: The ultimate scaling limit and device physics of aggressively scaled phosphorene MOSFETs are examined by self-consistent multiscale quantum transport simulations. The MOSFET structure can effectively suppress the ambipolar conduction and decrease the leakage current, and thereby, is more scalable than the Schottky barrier FET structure. The interplay of quantum mechanical effects and highly anisotropic band structure plays a critical role for phosphorene transistors with a sub 10-nm channel length, in which the optimum choice of the transport crystalline direction is completely different from phosphorene FETs with a longer channel length. Even at a sub-10-nm channel length with considerable quantum tunneling effects, the anisotropic band structure still provides a better device performance in terms of ON-current over other 2-D semiconductors with nearly isotropic band structures, such as MoS2. With the optimum choice of the transport direction, both n- and p-type phosphorene FETs meet the International Technology Roadmap for Semiconductor (ITRS) target at the 5-nm technology node.

Performance evaluation of series connected 1700V SiC MOSFET devices

Abstract: The low voltage SiC (Silicon carbide) MOSFET (1.2 kV to 1.7 kV) increases the switching frequency limits of a power electronic converter several folds compared to low voltage Si IGBTs. Significant increase in efficiency and power density of voltage source converters can be achieved. However, for medium-voltage high-power converter applications Silicon (Si) devices (4.5 kV and 6.5 kV IGBT) are still dominant. To explore the capability of low voltage SiC devices for medium or high voltage applications, series connection of 1.7 kV/300 A SiC MOSFET modules has been investigated in this paper. A simple RC snubber method has been used for dynamic voltage sharing to offset the turn-off delays due to mismatch on device's characteristics and/or gate signals. Experimental switching characterization with different values of RC snubbers have been carried out to find the optimal RC snubber which gives minimum voltage sharing difference, snubber losses and total semiconductor losses. This paper also intends to show an optimization of the RC snubber for series connection of a limited number of 1.7kV SiC MOSFETs for 6 kV dc bus and for a generalized dc bus voltage.

Process variation effect, metal-gate work-function fluctuation and random dopant fluctuation of 10-nm gate-all-around silicon nanowire MOSFET devices

Abstract: In this work, process variation effect (PVE), work function fluctuation (WKF), and random dopant fluctuation (RDF) on 10-nm high-K/metal gate gate-all-around silicon nanowire MOSFET devices using full-quantum-mechanically validated and experimentally calibrated device simulation are studied. The small aspect ratio device has greater immunity of RDF, while suffers from PVE and WKF.