Showing papers on "MOSFET published in 2017"
TL;DR: The technology progress of SiC power devices and their emerging applications are reviewed and the design challenges and future trends are summarized.
Abstract: Silicon carbide (SiC) power devices have been investigated extensively in the past two decades, and there are many devices commercially available now. Owing to the intrinsic material advantages of SiC over silicon (Si), SiC power devices can operate at higher voltage, higher switching frequency, and higher temperature. This paper reviews the technology progress of SiC power devices and their emerging applications. The design challenges and future trends are summarized at the end of the paper.
806 citations
TL;DR: A field-effect MoS2 transistor with a negative capacitor in its gate shows stable, hysteresis-free performance characterized by a sub-thermionic sub-threshold slope.
Abstract: The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of integration in a junctionless transistor topology, offer enhanced electrostatic control of the channel. Here, we combine these two advantages and demonstrate for the first time a molybdenum disulfide (MoS2) 2D steep slope transistor with a ferroelectric hafnium zirconium oxide layer (HZO) in the gate dielectric stack. This device exhibits excellent performance in both on- and off-states, with maximum drain current of 510 {\mu}A/{\mu}m, sub-thermionic subthreshold slope and is essentially hysteresis-free. Negative differential resistance (NDR) was observed at room temperature in the MoS2 negative capacitance field-effect-transistors (NC-FETs) as the result of negative capacitance due to the negative drain-induced-barrier-lowering (DIBL). High on-current induced self-heating effect was also observed and studied.
188 citations
TL;DR: This paper investigates and quantifies the increase in the conductedCM EMI emission of a pulse width modulation inverter-based motor drive when SiC and GaN devices are adopted and reveals that the influence of dv/dt on the conducted CM emission is generally limited.
Abstract: Silicon carbide (SiC) MOSFETs and gallium nitride (GaN) high-electron mobility transistors are perceived as future replacements for Si IGBTs and MOSFETs in medium- and low-voltage drives due to their low conduction and switching losses. However, it is widely believed that the already significant conducted common-mode (CM) electromagnetic interference (EMI) emission of motor drives will be further exacerbated by the high-speed switching operation of these new devices. Hence, this paper investigates and quantifies the increase in the conducted CM EMI emission of a pulse width modulation inverter-based motor drive when SiC and GaN devices are adopted. Through an analytical approach, the results reveal that the influence of dv/dt on the conducted CM emission is generally limited. On the other hand, the influence of switching frequency is more significant. Lab tests are also conducted to verify the analysis.
188 citations
TL;DR: In this article, the authors compared the use of Si and SiC mosfets for a three-level T-type inverter operating in grid-tie applications and showed that replacing only the dc bus connection switches with SiC devices significantly reduced the semiconductor losses, allowing either the converter power level or the switching frequency to be significantly increased for the same device losses.
Abstract: It is well known that multilevel converters can offer significant benefits in terms of harmonic performance and reduced switching losses compared to their two-level counterparts. However, for lower voltage applications the neutral-point-clamped inverter suffers from relatively large semiconductor conduction losses because the output current always flows through two switching devices. In contrast, the T-type multilevel inverter has less conduction losses because only a single outer loop switching device is required to connect the converter output to the upper and lower dc buses, albeit at the expense of increased switching losses since these outer switches must now block the full dc link voltage. Silicon carbide (SiC) mosfet devices potentially offer substantial advantage in this context with their lower switching losses, but the benefit of replacing all switching devices in a T-type inverter with SiC mosfets is not so clear-cut. This paper now explores this issue by presenting a detailed comparison of the use of Si and SiC devices for a three-level T-type inverter operating in grid-tie applications. The study uses datasheet values, switching loss measurements, and calibrated heat sink thermal measurements to precisely compare semiconductor losses for these two alternatives for a T-type inverter operating at or near unity power factor. The results show that replacing only the dc bus connection switches with SiC devices significantly reduces the semiconductor losses, allowing either the converter power level or the switching frequency to be significantly increased for the same device losses. Hence, the use of SiC mosfets for T-type inverters can be seen to be an attractive and potentially cost-effective alternative, since only two switching devices per phase leg need to be upgraded.
167 citations
15 Aug 2017
TL;DR: In this paper, the authors present the characteristics of 15 kV SiC MOSFET and offer a comprehensive guideline of implementing this device in practical medium voltage (MV) power conversion scenarios such as AC-DC, DC-DC and AC-AC in terms of topology selection, loss optimization and thermal management.
Abstract: Due to much higher achievable blocking voltage and faster switching speed, power devices based on wide bandgap (WBG) silicon carbide (SiC) material are ideal for medium voltage (MV) power electronics applications. For example, a 15 kV SiC MOSFET allows a simple and efficient two-level converter configuration for a 7.2 kV solid state transformer (SST) for smart grid applications. Compared with multilevel input series and output parallel (ISOP) solution, this approach offers higher efficiency and reliability, reduced system weight and cost by operating at medium to high switching frequency. However, the main concern is how to precisely implement this device in different MV applications, achieving highest switching frequency while maintaining good thermal performance. This paper reviews the characteristics of 15 kV SiC MOSFET and offers a comprehensive guideline of implementing this device in practical MV power conversion scenarios such as AC-DC, DC-DC and AC-AC in terms of topology selection, loss optimization and thermal management.
144 citations
TL;DR: In this article, a charge-plasma concept is introduced for the first time to implement a dielectric-modulated junctionless tunnel field effect transistor (DM-JLTFET) for biosensor label-free detection.
Abstract: To reduce the fabrication complexity and cost of the nanoscale devices, a charge-plasma concept is introduced for the first time to implement a dielectric-modulated junctionless tunnel field-effect transistor (DM-JLTFET) for biosensor label-free detection. The formation of p+ source and n+ drain regions in DM-JLTFET is done by the deposition of platinum (work function = 5.93 eV) and hafnium (work function = 3.9 eV) materials, respectively, over the silicon body. Furthermore, a nanogap cavity embedded within the gate dielectric is created by etching the portion of gate oxide layer toward the source end for sensing biomolecules. For this, the sensing capability of DM-JLTFET has been investigated in terms of variation in dielectric constant, charge density, length, and thickness of the cavity at different bias conditions. Finally, a comparative study between DM-JLTFET and MOSFET biosensor is investigated. The implementation of proposed device and all the simulations have been performed by using ATLAS device simulator.
142 citations
TL;DR: In this article, a partially oxidized (partial C-O) channel was used for hydrogen-terminated (C-H) diamond MOSFETs with a high breakdown voltage of over 2 kV at room temperature and normally-off characteristics with a gate threshold voltage of −2.5 −−4 V.
Abstract: Diamond has unique physical properties, which show great promise for applications in the next generation power devices. Hydrogen-terminated (C–H) diamond metal–oxide–semiconductor field-effect transistors (MOSFETs) often have normally-on operation in devices, because the C–H channel features a p-type inversion layer; however, normally-off devices are preferable in power MOSFETs from the viewpoint of fail safety. We fabricated hydrogen-terminated (C–H) diamond MOSFETs using a partially oxidized (partial C–O) channel. The fabricated MOSFETs showed a high breakdown voltage of over 2 kV at room temperature and normally-off characteristics with a gate threshold voltage $\text{V}_{\mathrm{th}}$ of −2.5–−4 V.
139 citations
TL;DR: A novel active gate driver (AGD) for improving the SiC MOSFET switching trajectory with high performance is presented and results show that the AGD can reduce the overshoots, oscillations, and losses without compromising the EMI.
Abstract: The trend in power electronic applications is to reach higher power density and higher efficiency. Currently, the wide band-gap devices such as silicon carbide MOSFET (SiC MOSFET) are of great interest because they can work at higher switching frequency with low losses. The increase of the switching speed in power devices leads to high power density systems. However, this can generate problems such as overshoots, oscillations, additional losses, and electromagnetic interference (EMI). In this paper, a novel active gate driver (AGD) for improving the SiC MOSFET switching trajectory with high performance is presented. The AGD is an open-loop control system and its principle is based on gate energy decrease with a gate resistance increment during the Miller plateau effect on gate–source voltage. The proposed AGD has been designed and validated through experimental tests for high-frequency operation. Moreover, an EMI discussion and a performance analysis were realized for the AGD. The results show that the AGD can reduce the overshoots, oscillations, and losses without compromising the EMI. In addition, the AGD can control the turn-on and turn-off transitions separately, and it is suitable for working with asymmetrical supplies required by SiC MOSFETs.
128 citations
TL;DR: In this paper, a new precursor that can be used for online condition monitoring of power mosfet gate oxide degradation is proposed, and a theoretical model is established to describe the relationship between miller platform voltage and two types of gate oxide defects, and the precursor can be extracted without impacting system operation.
Abstract: The condition monitoring problem of power devices is significant for diagnostics and prognostics of a switched-mode power supply (SMPS) system. For power mosfet , the gate oxide degradation often occurs in various applications. However, there is no online condition monitoring method for gate oxide degradation so far. In this paper, a new precursor that can be used for online condition monitoring of power mosfet gate oxide degradation is proposed. Gate oxide degradation mechanisms and effect are summarized, and the mosfet turn-on process is analyzed. Then, a theoretical model is established to describe the relationship between miller platform voltage and two types of gate oxide defects, and miller platform voltage is identified as a new precursor. The precursor can be extracted without impacting system operation, thus online condition monitoring can be accomplished. The accelerated degradation test is carried out for power mosfet s with both high electric field and gamma irradiation methods, and the degraded devices injection and in situ monitoring of miller platform voltage are conducted on a BOOST circuit to verify the feasibility of the new precursor. Experimental results demonstrate that the new precursor can be applied to online condition monitoring of power mosfet gate oxide degradation in the SMPS system.
95 citations
TL;DR: In this paper, two custom-designed testbeds are used to age a number of power MOSFETs and insulated gate bipolar transistors and an automated curve tracer is utilized to capture parametric variations in I-V curves, parasitic capacitances, and gate charges at certain time intervals.
Abstract: Thermal/power cycles are widely acknowledged methods to accelerate the package related failures. Many studies have focused on one particular aging precursor at a time and continuously monitored it using custom-built circuits. Due to the difficulties in taking sensitive measurements, the reported findings are more on the quantities requiring less sensitive measurements. In this paper, two custom-designed testbeds are used to age a number of power MOSFETs and insulated gate bipolar transistors. An automated curve tracer is utilized to capture parametric variations in I – V curves, parasitic capacitances, and gate charges at certain time intervals. The results suggest that the only viable aging precursors are the on-state voltage drop/on-state resistance, body diode voltage drop, parasitic capacitances, and gate threshold voltage for die attach solder and gate-oxide degradation mechanisms. Based on the experimental results, gate threshold voltage variation is empirically modeled to estimate the remaining useful lifetime of the switches experiencing gate oxide degradation. The model parameters are found by the least squares method applied to inliers determined by the random sample and consensus outlier removal algorithm.
94 citations
TL;DR: The tunneling width at the channel-drain interface and the source-to-channel barrier height are considerably increased in the NT JLFET due to the presence of the core gate, leading to a significantly high on-state to off-state current ratio of ~107 even for a channel length of 7 nm.
Abstract: In this paper, we propose a nanotube (NT) JLFET for significantly improved performance in the sub-10-nm regime. We show that the tunneling width at the channel-drain interface and the source-to-channel barrier height are considerably increased in the NT JLFET due to the presence of the core gate. Therefore, the lateral band-to-band-tunneling-induced parasitic bipolar junction transistor action is diminished in the off-state of NT JLFET, leading to a significantly high on-state to off-state current ratio of ~107 even for a channel length of 7 nm. Furthermore, we demonstrate that the spacer length and dielectric constant and the core gate diameter can be used as design parameters to further improve the performance of the NT JLFETs. Therefore, we also provide the necessary design guidelines for NT JLFETs.
01 May 2017
TL;DR: In this paper, the authors describe a novel SiC trench MOSFET concept, which is designed to balance low conduction losses with Si-IGBT-like reliability, and show that the favorable temperature behavior of the on-state resistance combined with a low sensitivity of the switching energies to temperature simplify the design-in.
Abstract: This paper describes a novel SiC trench MOSFET concept. The device is designed to balance low conduction losses with Si-IGBT like reliability. Basic features of the static and dynamic performance as well as short circuit capability of the 45mΩ/1200 V CoolSiC™ MOSFET are presented. The favorable temperature behavior of the on-state resistance combined with a low sensitivity of the switching energies to temperature simplify the design-in. Long-term gate oxide tests reveal a very low extrinsic failure rate well matching the requirements of industrial applications.
TL;DR: Numerical simulations are conducted to validate the proposed new concise yet accurate switching loss model for SiC power MOSFETs and provide guidelines in designing the gate driver for ultrafast SiCPower MOSfETs.
Abstract: The reduced chip size and unipolar current conduction mechanism make silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) suitable for high-frequency power electronics applications. Modeling the switching process of the SiC power MOSFET with parasitic components is important for achieving higher efficiency and power density system design. Therefore, this paper proposes a new concise yet accurate switching loss model for SiC power MOSFETs. Addressing the limitations in experimental measurements, numerical simulations are conducted to validate the proposed model taking the output capacitance C oss discharge and charge into consideration. The role of the parasitic components in the second-order model is discussed in depth for switching losses. Furthermore, this paper also provides guidelines in designing the gate driver for ultrafast SiC power MOSFETs.
TL;DR: In this paper, two commercially available silicon carbide (SiC) MOSFETs were evaluated using a load inductance of 1.42, 5.1, 10.5, and 15.8 mH.
Abstract: Commercialization of 1200-V silicon carbide (SiC) MOSFET has enabled power electronic design with improved efficiency as well as increased power density. High-voltage spikes induced in applications such as solenoid control, solid-state transformer, boost converter, and flyback converter can drive the MOSFET into avalanche mode operation due to high di / dt coupled with parasitic inductance. Avalanche mode operation is characterized by high-power dissipation within the device due to the high voltage and current crossover. This study focuses on the evaluation of two commercially available SiC MOSFETs from different manufacturers, each rated for 1200 V with an ON-state resistance of 80 mΩ, during unclamped inductive switching (UIS) mode operation. To determine device reliability, a decoupled UIS testbed was developed to evaluate the avalanche energy robustness at 22 $ \,^{\circ}$ C and 125 $ \,^{\circ}$ C during two specific conditions: high current and low energy, and low current and high energy. The SiC MOSFETs were evaluated using a load inductance of 1.42, 5.1, 10.5, and 15.8 mH to understand the effect of current and avalanche energy on device failure. To correlate the experimental results with the failure mechanism, estimated junction temperature and static device characteristics are presented; additionally, MOSFETs were decapsulated to examine the failure sites on the semiconductor die.
TL;DR: Using the proposed general embedding, an amplifier is implemented in a 65 nm CMOS process with a measured power gain of 9.2 dB at 260 GHz, which is the highest frequency reported in any silicon-based amplifier.
Abstract: In this paper, a general embedding is proposed to boost the power gain of any device to the maximum achievable gain ( $G_{\max }$ ), which is defined as the maximum theoretical gain of the device. Using a gain-plane based analysis, two linear-lossless-reciprocal embeddings are used to perform a movement from the coordinate of the transistor to the coordinate that corresponds to $G_{\max }$ . The proposed embedding is applied to a 10 $\mu \text{m}$ common-source NMOS transistor, and the theoretical and simulation results are presented and compared. The properties of the embedded transistor are inspected, and the few issues in implementation are investigated and addressed. Finally, using the proposed general embedding, an amplifier is implemented in a 65 nm CMOS process with a measured power gain of 9.2 dB at 260 GHz, which is the highest frequency reported in any silicon-based amplifier.
TL;DR: In this article, the 15kV silicon carbide (SiC) MOSFET and 15-kV SiC IGBT are compared with the complex three-level neutral point clamped and other multilevel topologies, which is required to realize for MV VSC with silicon devices.
Abstract: The 15-kV silicon carbide (SiC) MOSFET and 15-kV SiC IGBT are the two state-of-the-art high-voltage SiC devices. These high-voltage SiC devices enable simple two-level converters for a medium-voltage (MV) voltage source converter (VSC) topology compared with the complex three-level neutral point clamped and other multilevel topologies, which, otherwise, is required to realize for MV VSC with silicon devices. This paper characterizes the 15-kV SiC MOSFET module at 10- and 12-kV dc bus for two different configurations of the device under test. This paper also presents endurance test (continuous switching-mode experimental demonstration) of 15-kV SiC MOSFET for 10-kV output voltage for both a bidirectional and unidirectional dc-dc boost converter. Furthermore, this paper presents: 1) the switching loss comparison of 15-kV SiC MOSFET with 15-kV SiC IGBT for the same dv/dt condition; 2) the switching frequency limits of 15-kV SiC MOSFET for a dc-dc boost converter with a phase leg configuration at 10-kV output voltage; and 3) comparative evaluation of 15-kV SiC MOSFET and 15-kV SiC IGBT in a unidirectional dc-dc boost converter for 10 V output voltage.
TL;DR: This paper presents a novel compact circuit combining function of gate control and voltage balancing for series-connected silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET).
Abstract: This paper presents a novel compact circuit combining function of gate control and voltage balancing for series-connected silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET) Two series-connected SiC MOSFETs with the proposed circuit only require a single standard gate driver to achieve the gate control and voltage balancing during both steady-state and switching transition Moreover, the proposed circuit is only composed of ten passive components Therefore, the proposed circuit provides a low-cost and highly reliable method to increase the blocking voltage of the SiC MOSFET The operation principles of the proposed circuit are theoretically analyzed In addition, the high-blocking-voltage device is not only required in switching-mode power supply (SMPS) but also in dc-breaker applications The proposed circuit is then modified to make it suitable to the dc-breaker applications The simulation and experimental results validate the effectiveness and superiority of the proposed circuit in both SMPS and dc-breaker applications
01 May 2017
TL;DR: In this paper, the voltage drop of the SiC MOSFET body diode pn-junction at low measurement current with sufficient negative gate voltage was found most suitable one.
Abstract: The evaluation of power cycling results needs correct measurement of the course of thermal resistance. Hence an accurate online measurement of the junction temperature is necessary. Different measurement and power cycling methods were evaluated. The method of measuring the voltage drop of the SiC MOSFET body diode pn-junction at low measurement current with sufficient negative gate-voltage was found most suitable one. In addition power losses during power cycling test should be generated in forward MOSFET-mode at high positive gate-voltage. Otherwise test results will not be application conform.
TL;DR: A feasible solution of implementing press-pack packaging on SiC MOSFETs to extend the application of SiC devices into the high power range is proposed and evaluated by simulations and tests to validate the feasibility of the proposed packaging approach.
Abstract: This paper proposes a packaging method for SiC MOSFETs that provides a feasible solution of implementing press-pack packaging on SiC MOSFETs to extend the application of SiC devices into the high power range. The challenges in realizing press-pack packaging of SiC MOSFETs are addressed, and the solutions are proposed that fit the specific requirements of SiC MOSFET. To achieve pressure contact on SiC MOSFETs, miniature and flexible press pins called “fuzz buttons” are used in a low-profile interposer to realize die top side connection. Since the press-pack does not provide internal insulation between the active device and the heatsink, the heatsink is included in the power loop. To avoid large parasitic loop inductance being introduced by the heatsinks, a microchannel heatsink is developed which has a low thickness while remaining adequate heat dissipation efficiency. The structure and assembly process flow of the press-pack SiC MOSFET are provided. A half-bridge stack prototype with two press-packs and three heatsinks is developed. The thermal and electrical performances of the press-pack and the half-bridge stack are evaluated by simulations and tests to validate the feasibility of the proposed packaging approach.
TL;DR: It is found that the selection of FE thickness is important to balance current amplification and saturated output characteristics as compared with MOSFET, which exhibits a larger current, transconductance, and current-to-transconductance generation efficiency.
Abstract: Negative capacitance ferroelectric (FE) field-effect transistor (FeFET) is promising to address the issue of the increasing power density in digital circuit by realizing sub-60 mV/decade subthreshold swing. This inspires us to evaluate its applications in analog circuit. In this paper, the evaluation is performed based on the equivalent circuit model and through device- and circuit-level benchmarking against MOSFET counterpart. It is found that the selection of FE thickness is important to balance current amplification and saturated output characteristics. As compared with MOSFET, FeFET exhibits a larger current, transconductance, and current-to-transconductance generation efficiency. Its output resistance is smaller in the linear region and larger in the saturation region. It also has less variation in threshold voltage with temperature. When implementing FeFETs into various analog circuit applications, we find that a node capacitor could be discharged within shorter time to increase circuit speed; A better analog switch consisting of complementary FeFETs exhibits a lower and more linear on-resistance; Differential amplifier provides larger voltage amplification to small input signal; Current mirror transfers a more precise output current to the reference one.
TL;DR: Experimental investigation of neutron induced single event failures and the associated device cross sections as well as low altitude failure-in-time (FIT) curves in silicon (Si) and silicon carbide (SiC) power MOSFETs at room temperature are reported along with possible explanation of failure mechanisms in SiC devices as mentioned in this paper.
Abstract: Experimental investigation of neutron induced single event failures and the associated device cross sections as well as low altitude failure-in-time (FIT) curves in silicon (Si) and silicon carbide (SiC) power MOSFETs at room temperature are reported along with possible explanation of failure mechanisms in SiC devices. Neutrons are found to give rise to significantly fewer failures in SiC power MOSFETs compared to their Si equivalents; however, SiC power MOSFETs do exhibit catastrophic failures when exposed to neutrons that simulate the terrestrial spectrum.
TL;DR: In this article, a double-end sourced layout for multichip SiC MOSFET power module adopting conventional wire-bonded packaging technology is proposed, which provides each MOS-FET with two parallel commutation loops by incorporating a symmetrical pair of dc-bus terminals into the power module.
Abstract: This paper proposes a double-end sourced layout for multichip SiC MOSFET power module adopting conventional wire-bonded packaging technology. The unique design provides each MOSFET with two parallel commutation loops by incorporating a symmetrical pair of dc-bus terminals into the power module. This new layout provides symmetrical equivalent power loops to each paralleled MOSFET and thus enables consistent switching performances and equal dynamic current sharing for the paralleled MOSFETs. Compared to the conventional design, the proposed design reduces the equivalent power-loop stray inductance by more than 50% and achieves improved dynamic current sharing among devices. By mitigating the imbalance of the switching current, the new module design demonstrated reduced temperature differences among devices and decreased near-field radiation noise level compared to the conventional layout. These features can further help to improve the power module density by shrinking the heat sink and integrating the gate driver board with the power modules. In this paper, an analytic model has been proposed for fast prediction of the near-field radiation from the power module. Detailed design procedures and experimental validations are also included in this paper.
TL;DR: In this article, a split output converter was proposed to overcome the limitations of the standard two-level voltage source converters when employing the fast-switching SiC devices, which can overcome the phase-leg shoot-through (crosstalk) effect, high turn-on losses, electromagnetic interference (EMI), etc.
Abstract: The adoption of silicon carbide (SiC) MOSFETs and SiC Schottky diodes in power converters promises a further improvement of the attainable power density and system efficiency, while it is restricted by several issues caused by the ultrafast switching, such as phase-leg shoot-through (“crosstalk” effect), high turn-on losses, electromagnetic interference (EMI), etc. This paper presents a split output converter, which can overcome the limitations of the standard two-level voltage source converters when employing the fast-switching SiC devices. A mathematical model of the split output converter has been proposed to reveal how the split inductors can mitigate the crosstalk effect caused by the high switching speed. The improved switching performance (e.g., lower turn-on losses) and EMI benefit have been demonstrated experimentally. The current freewheeling problem, the current pulses and voltage spikes of the split inductors, and the disappeared synchronous rectification are explained in detail both experimentally and analytically. The results show that the split output converter can have lower power device losses compared with the standard two-level converter at high switching frequencies. However, the extra losses in the split inductors may impair the efficiency of the split output converter, which is verified by experiments in the continuous operating mode. A 95.91% efficiency has been achieved by the split output converter at the switching frequency of 100 kHz with suppressed crosstalk, lower turn-on losses, and reduced EMI.
TL;DR: A self-biased temperature-compensated CMOS voltage reference operating at picowatt-level power consumption and silicon area are remarkably reduced by combining subthreshold operation with a self- biased scheme.
Abstract: In this paper, a self-biased temperature-compensated CMOS voltage reference operating at picowatt-level power consumption is presented. The core of the proposed circuit is the self-cascode MOSFET (SCM) and two variants are explored: a self-biased SCM (SBSCM) and a self-biased NMOS (SBNMOS) voltage reference. Power consumption and silicon area are remarkably reduced by combining subthreshold operation with a self-biased scheme. Trimming techniques for both circuits are discussed aiming at the reduction of the process variations impact. The proposed circuits were fabricated in a standard 0.18- $\mu \text{m}$ CMOS process. Measurement results from 24 samples of the same batch show that both circuits herein proposed can operate at 0.45/0.6 V minimum supply voltage, consuming merely 55/184 pW at room temperature. Temperature coefficient (TC) around 104/495 ppm/°C across a temperature range from 0 to 120 °C was measured. Employment of a trimming scheme allows a reduction of the average TC to 72.4/11.6 ppm/°C for the same temperature range. Both variants of the proposed circuit achieve a line sensitivity of 0.15/0.11 %/V and a power supply rejection better than −44/−45 dB from 10 to 10 kHz. In addition, SBSCM and SBNMOS prototypes occupy a silicon area of 0.002 and 0.0017 mm2, respectively.
01 May 2017
TL;DR: In this article, an SBD is embedded into each unit cell of a 6.5 kV SiC-MOSFET to suppress current conduction of the body diodes, which causes bipolar degradation following the expansion of stacking faults.
Abstract: For higher-voltage SiC modules, larger SBD chips are required as free-wheel diodes to suppress current conduction of the body diodes of MOSFETs, which causes bipolar degradation following the expansion of stacking faults. By embedding an SBD into each unit cell of a 6.5 kV SiC-MOSFET, we achieved, without using external SBDs, a high-voltage switching device that is free from bipolar degradation. Expansion of the active area by embedding SBDs is only 10% or less, whereas the active area of external SBDs can be over three times larger than that of the coupled MOSFET. The fabricated 6.5 kV SBD-embedded SiC-MOSFETs show sufficiently high breakdown voltages, low specific on-resistances, no bipolar degradation, and good reliability.
TL;DR: In this article, a simple model of negative capacitance (NC) MOSFETs is presented, which shows quantitative agreement with numerical device simulations based on a selfconsistent solution of the Poisson equation and quantum transport equation.
Abstract: A simple model of negative capacitance (NC) MOSFETs is presented. The model treats 2-D electrostatic effects, and the ballistic to diffusive transport regimes. It shows quantitative agreement with numerical device simulations based on a self-consistent solution of the Poisson equation and quantum transport equation based on nonequilibrium Green’s function formalism, for an NC MOSFET structure without an internal floating gate. The model can accurately describe the reverse drain-induced barrier lowering (DIBL) and negative output differential conductance (NDC) effects as the NC FETs scale down. With approximations valid at low power supply voltages, it is shown that the improvement of the subthreshold swing (SS) due to electrostatic short channel effects results in a linear increase of the reverse DIBL and NDC. For a modified NC MOSFET structure with an ultrathin quantum metallic layer contacted to the source, the SS, however, can be improved considerably with the reverse DIBL and NDC approximately unchanged.
TL;DR: In this article, the effect of drain doping engineering on the ambipolar conduction and high-frequency performance of tunneling FETs was investigated using 2-D TCAD simulations, and it was demonstrated that when splitting the drain into two regions, one with high doping above the other of low doping, the tunneling width at the channel-drain interface increases.
Abstract: In this paper, the effect of a proposed drain doping engineering on the ambipolar conduction and high-frequency performance of tunneling FETs (TFETs) is investigated using 2-D TCAD simulations. The proposed TFET structure is based on using a high-doped region above a low-doped region of the drain side. It is demonstrated that when splitting the drain into two regions, one with high doping above the other of low doping, the tunneling width at the channel–drain interface increases. This increase in the tunneling width causes an appreciable reduction of ambipolar current in the TFET. Moreover, high-frequency figures of merit regarding the transconductance ( ${g_{m}}$ ), source-to-gate and drain-to-gate capacitances, and unit-gain cutoff frequency ( ${f_{T}}$ ) are analyzed. It is found that the combination of drain doping regions could enhance the high-frequency performance. Additionally, the proposed technique does not deteriorate the ON-current levels.
TL;DR: In this article, an E-mode MOSFET with an Y2O3 oxide insulator grown on the H-diamond directly using an electron beam evaporator was constructed.
Abstract: Enhancement-mode (E-mode) hydrogenated diamond (H-diamond) metal-oxide-semiconductor field-effect transistors (MOSFETs) are fabricated with an Y2O3 oxide insulator grown on the H-diamond directly using an electron beam evaporator The depletion region of the capacitance-voltage curve for the MOS capacitor shifts to the left hand side relative to 0 V, which indicates the existence of positive charges in the Y2O3 film There are distinct pinch-off and p-type channel characteristics of the Y2O3/H-diamond MOSFETs The maximum drain-source current for the MOSFET without interspace between the source/drain and the gate (LS/D-G) is −1146 mA mm−1 Those for the MOSFETs with LS/D-G are decreased from −110 to −21 mA mm−1 with the gate length increasing from 33 ± 01 to 154 ± 01 μm Threshold voltages for all the MOSFETs are negative, indicating their E-mode characteristics Negatively charged adsorbates are one of the necessary conditions for hole accumulation of the H-diamond channel layer, which are possibl
TL;DR: A current-dependent switching strategy is introduced and implemented to further improve the performance of Si/SiC hybrid switches and is based on a comprehensive consideration of reducing device losses, reliable operation, and overload capability.
Abstract: Hybrid switches configured by paralleling Silicon (Si) Insulated Gate Bipolar Transistors (IGBT) and Silicon Carbide (SiC) Metal-Oxide Semiconductor Field-Effect Transistors (MOSFET) have been verified to be a high-efficiency cost-effective device concept In this paper, a current-dependent switching strategy is introduced and implemented to further improve the performance of Si/SiC hybrid switches This proposed switching strategy is based on a comprehensive consideration of reducing device losses, reliable operation, and overload capability Based on the utilization of such Si/SiC hybrid switches and the proposed switching strategy, a 15-kW single-phase H-bridge inverter prototype was implemented and tested in the laboratory Simulation and experimental results are given to verify the performance of the hybrid switches and the new switching strategy
01 Mar 2017
TL;DR: In this article, the authors presented an experimental case study on the switching characteristics and common mode (CM) noise generation of a GaN-based half-bridge configuration operating in the synchronous boost mode.
Abstract: Wide bandgap semiconductors, such as gallium nitride (GaN)-based power devices have become increasingly popular in the automotive industry due to their low on-state resistance and fast switching capabilities These devices are sought to replace silicon (Si) devices in power electronics converters for vehicular applications GaN devices dissipate less energy during each switching event, thus, GaN converter designers can significantly increase the switching frequency without increasing switching losses, relative to Si converters However, one item of concern is that the high $dv/dt$ of GaN devices, due to the increased switching speed, has the potential to deteriorate the electromagnetic interference (EMI) emission of power converters, and thus may fail the corresponding regulations for vehicles To understand these effects, this paper presents an experimental case study on the switching characteristics and common mode (CM) noise generation of a GaN-based half-bridge configuration operating in the synchronous boost mode A comprehensive comparison has been made between the chosen GaN high electron mobility transistors (HEMTs) and Si MOSFET in terms of switching voltage waveforms, ground leakage currents, and CM noise spectrum By parametrically increasing the gate resistance of GaN HEMT and Si MOSFET, the tradeoff between converter efficiency and CM noise generation is also quantified