Showing papers on "MOSFET published in 2018"
TL;DR: In this article, a two-dimensional steep-slope MOSFET with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack is presented.
Abstract: The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV dec-1 at room temperature and therefore precludes lowering of the supply voltage and overall power consumption 1,2 . Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier 3 . Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel 4-12 . Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 μA μm-1 and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.
382 citations
TL;DR: In this article, a SiC MOSFET and Si device hybrid active neutral point-clamped (ANPC) converter is proposed, which consists of four Si active switches and only two Si C MOS-FETs.
Abstract: Three-level converters typically feature low switching loss and small filter size. In order to realize a high-power-density design for three-level converters, SiC MOSFETs may be selected instead of using Si insulated-gate bipolar transistors. However, all-SiC-MOSFET-based converters suffer from extremely high total cost. In this paper, a SiC MOSFET and Si device hybrid active neutral-point-clamped (ANPC) converter is proposed. It consists of four Si active switches and only two SiC MOSFETs. Thus, it has lower total cost compared to the all-SiC-MOSFET-based ANPC converter. Furthermore, a dedicated modulation scheme is proposed to completely move all the switching events from Si devices to SiC MOSFETs by using redundant switching states. As a result, the switching losses are significantly reduced and extremely high efficiency is achieved. The proposed converter has fully utilized the low-switching-loss advantage of SiC MOSFETs and the low-cost advantage of Si devices, which shows significant superiority in high-end grid-connected inverter and rectifier applications.
157 citations
TL;DR: A new measure-stress-measure procedure for BTI evaluation of SiC MOSFETs is proposed which allows distinguishing between reversible threshold voltage hysteresis and more permanent threshold voltage drift (BTI).
157 citations
TL;DR: In this article, a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes was developed relying on the 1-D Poisson equation and the drift-diffusion transport mechanism.
Abstract: This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes. The model is developed relying on the 1-D Poisson equation and the drift-diffusion transport mechanism. The validity of the Maxwell–Boltzmann approximation is demonstrated in the limit to 0 K as a result of dopant freezeout in cryogenic equilibrium. Explicit MOS transistor expressions are then derived, including incomplete dopant ionization, bandgap widening, mobility reduction, and interface charge traps. The temperature dependence of the interface trapping process explains the discrepancy between the measured value of the subthreshold swing and the thermal limit at deep-cryogenic temperatures. The accuracy of the developed model is validated by experimental results on long devices of a commercial 28-nm bulk CMOS process. The proposed model provides the core expressions for the development of physically accurate compact models dedicated to low-temperature CMOS circuit simulation.
129 citations
TL;DR: In this paper, the temperature-dependent characteristics of the third-generation 10-kV/20-A SiC MOSFET including the static characteristics and switching performance are carried out in a double pulse test platform.
Abstract: The temperature-dependent characteristics of the third-generation 10-kV/20-A SiC MOSFET including the static characteristics and switching performance are carried out in this paper. The steady-state characteristics, including saturation current, output characteristics, antiparallel diode, and parasitic capacitance, are tested. A double pulse test platform is constructed including a circuit breaker and gate drive with >10-kV insulation and also a hotplate under the device under test for temperature-dependent characterization during switching transients. The switching performance is tested under various load currents and gate resistances at a 7-kV dc-link voltage from 25 to 125 ˚C and compared with previous 10-kV MOSFETs. A simple behavioral model with its parameter extraction method is proposed to predict the temperature-dependent characteristics of the 10-kV SiC MOSFET. The switching speed limitations, including the reverse recovery of SiC MOSFET's body diode, overvoltage caused by stray inductance, crosstalk, heat sink, and electromagnetic interference to the control are discussed based on simulations and experimental results.
106 citations
TL;DR: The proposed novel circuits for XOR/XNOR and simultaneous XOR–XNOR functions are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation.
Abstract: In this paper, novel circuits for XOR/XNOR and simultaneous XOR–XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. We also propose six new hybrid 1-bit full-adder (FA) circuits based on the novel full-swing XOR–XNOR or XOR/XNOR gates. Each of the proposed circuits has its own merits in terms of speed, power consumption, power-delay product (PDP), driving ability, and so on. To investigate the performance of the proposed designs, extensive HSPICE and Cadence Virtuoso simulations are performed. The simulation results, based on the 65-nm CMOS process technology model, indicate that the proposed designs have superior speed and power against other FA designs. A new transistor sizing method is presented to optimize the PDP of the circuits. In the proposed method, the numerical computation particle swarm optimization algorithm is used to achieve the desired value for optimum PDP with fewer iterations. The proposed circuits are investigated in terms of variations of the supply and threshold voltages, output capacitance, input noise immunity, and the size of transistors.
101 citations
TL;DR: The proposed method can provide a valuable tool for continuous health monitoring in emerging applications of SiC devices to high-reliability applications and potentially good sensitivity to temperature variation and linearity over a wide operating range.
Abstract: This paper examines a number of techniques for junction temperature estimation of silicon carbide (SiC) MOSFET s devices based on the measurement of temperature sensitive electrical parameters for use in online condition monitoring. Linearity, sensitivity to temperature, and circuit design for practical implementation are discussed in detail. A demonstrator based on the measurement of the quasi-threshold voltage, the turn- on transient characteristic ( $di/ dt$ ), the on -state voltage, and the gate current peak is designed and validated. It is shown that the threshold voltage, the estimation of the gate current peak, and the on -state voltage have potentially good sensitivity to temperature variation and linearity over a wide operating range. Very low sensitivity to temperature is shown for $di/ dt$ . The proposed method can provide a valuable tool for continuous health monitoring in emerging applications of SiC devices to high-reliability applications.
97 citations
TL;DR: The results show that, despite its existing nonlinearities, the SiC-based drive has lower voltage distortion compared to the conventional Si- based drive as a result of its shorter switching times and smaller voltage drop, as well as a higher efficiency.
Abstract: This paper investigates the inverter nonlinearities in a drive system based on silicon carbide metal-oxide-semiconductor field-effect transistor (SiC- mosfet s) and compares its performance with that of an equivalent silicon insulated-gate bipolar transistor (Si-IGBT) system. Initially, a novel comprehensive analytical model of the inverter voltage distortion is developed. Not only voltage drops, dead time, and output capacitance, but also switching delay times and voltage overshoot of the power devices are taken into account in the model. Such a model yields a more accurate prediction of the inverter's output voltage distortion, and is validated by experimentation. Due to inherent shortcomings of the commonly used double pulse test, the switching characteristics of both SiC- mosfet s and Si-IGBTs in the pulse width modulation inverter are tested instead, such that the actual performances of the SiC and Si devices in the motor drive system are examined. Then, the switching performance is incorporated into the physical model to quantify the distorted voltages of both the SiC-based and Si-based systems. The results show that, despite its existing nonlinearities, the SiC-based drive has lower voltage distortion compared to the conventional Si-based drive as a result of its shorter switching times and smaller voltage drop, as well as a higher efficiency. Finally, the overriding operational advantages of the SiC-based drive over its Si-based counterpart is fully demonstrated by comprehensive performance comparisons.
89 citations
TL;DR: In this paper, the authors investigated SEB in high-voltage silicon carbide power MOSFETs and showed a significant decrease in SEB onset voltage for particle linear energy transfers greater than 10 MeV/cm2/mg, above which the SEB threshold voltage is nearly constant at half of the rated maximum operating voltage.
Abstract: Heavy ion-induced single-event burnout (SEB) is investigated in high-voltage silicon carbide power MOSFETs. Experimental data for 1200-V SiC power MOSFETs show a significant decrease in SEB onset voltage for particle linear energy transfers greater than 10 MeV/cm2/mg, above which the SEB threshold voltage is nearly constant at half of the rated maximum operating voltage for these devices. TCAD simulations show a parasitic bipolar junction transistor turn-on mechanism, which drives the avalanching of carriers and leads to runaway drain current, resulting in SEB.
89 citations
01 Dec 2018
TL;DR: An SoC logic compatible ferroelectric-metal field effect transistor (FeMFET) digital 2-bit weight cell by monolithic BEOL integration of a ferro electric capacitor with the gate of a conventional Si HK/MG MOSFET is demonstrated.
Abstract: We demonstrate an SoC logic compatible ferroelectric-metal field effect transistor (FeMFET) digital 2-bit weight cell by monolithic BEOL integration of a ferroelectric (FE) capacitor with the gate of a conventional Si HK/MG MOSFET. Through optimization of the area ratio between the FE capacitor and the MOSFET, we show: 1) program/erase write voltages can be scaled down to logic compatible level, ±1.8 V, simplifying write circuitry; 2) write speed of 100ns; 3) write endurance $> 10^{10}$ cycles without degradation due to elimination of charge trapping in FE; 4) 2 bits/cell achieving software levels of accuracy for inference on MNIST training database; 5) state retention approaching 104 s for a depolarization field of 0.3 MV/cm; 6) Multi-port (independent read and write) operations.
89 citations
TL;DR: In this article, the authors presented an accurate and reliable calorimetric method for the determination of soft-switching losses using the example of 10-kV SiC mosfet modules.
Abstract: The characterization of soft-switching losses (SSL) of modern high-voltage SiC mosfet s is a difficult but necessary task in order to provide a sound basis for the accurate modeling of converter systems, such as medium-voltage-connected solid-state transformers, where soft-switching techniques are employed to achieve an improved converter efficiency. Switching losses (SL), in general, are typically measured with the well-known double pulse method. In the case of SSL measurements, however, this method is very sensitive to the limited accuracy of the measurement of the current and voltage transients, and thus is unsuitable for the characterization of fast-switching high-voltage mosfet s. This paper presents an accurate and reliable calorimetric method for the determination of SSL using the example of 10-kV SiC mosfet modules. Measured SSL curves are presented for different dc-link voltages and switched currents. Furthermore, a deeper analysis concerning the origin of SSL is performed. With the proposed measurement method, it can be experimentally proven that the largest share of the SSL arises from charging and discharging the output capacitance of the mosfet module and especially of the antiparallel junction barrier Schottky diode.
TL;DR: In this paper, the junction temperature of a SiC power mosfet s is estimated in real-time by measuring its current and on-state voltage V ON at each switching period and entering the temperature in the lookup table of the device.
Abstract: This paper deals with real-time estimation of the junction temperature of SiC power mosfet s. The junction temperature of a device with four-switch module is estimated in real-time by measuring its current and on-state voltage V ON at each switching period and entering the temperature in the lookup table of the device. The temperature model is preliminarily obtained in a dedicated commissioning session, where V ON is measured at different temperature and current conditions. The results show the feasibility of online temperature monitoring and even the active limitation of the junction temperature of the tested SiC power mosfet modules accurately and with an instantaneous dynamic response. Different modules with die from different manufacturers were tested in an H-bridge demonstrator power converter, emulating the operating conditions of real converters such as voltage source dc/ac or dc/dc conversion structures. The commissioning procedure is meant to be performed directly on the final application for each converter. The measurements obtained using the proposed temperature estimation technique are validated using a thermal camera and compared to the direct measurement of the die temperature with a thermistor, showing high accuracy and high feasibility.
TL;DR: A new technique to accurately characterize the parasitic inductances of SiC power mosfets in both discrete packages and power modules based on two-port S-parameters measurement, which provides more accurate values of the internal parasitic inductance than the commonly used single-port impedance measurement technique.
Abstract: The parasitic inductances of silicon carbide (SiC) power mosfet s have a major influence on their operation and circuit performance. They incur negative effects such as switching oscillations, power losses, and electromagnetic interference noise. This paper introduces a new technique to accurately characterize the parasitic inductances of SiC power mosfet s in both discrete packages and power modules based on two-port S-parameters measurement. By treating a power mosfet as a two-port network, we obtain the scattering (S) and impedance (Z) parameters from network analyzer measurement. These parameters, through detailed network analysis, provide more accurate values of the internal parasitic inductances than the commonly used single-port impedance measurement technique. The new approach is first verified with high-frequency circuit simulation and then applied in the case study of SiC power mosfet s in a TO-247 discrete package and a half-bridge power module. In addition, a number of silicon power mosfet s and IGBTs in TO-247, TO-220, D2PAK, DPAK, and SO-8 packages are also characterized for comparison. A comparison between the characterization results from the new two-port and the prior art one-port methods reveals a significant difference ranging from 12.6% to 93.9%.
Rohm1
TL;DR: In this article, a measurement technique that overcomes self-heating and derives the high-voltage and high-current region from switching waveforms is presented. But the technique is limited to the case of single-input single-output (SiC) transistors.
Abstract: This paper presents two novel measurement methods to characterize silicon carbide (SiC) MOSFET devices. The resulting data are utilized to significantly improve the extraction of a custom device model that can now accurately reproduce device switching behavior. First, we consider the $I_{\text{d}}- V_{\text{ds}}$ output characteristics of power devices such as SiC transistors. These are typically measured using traditional curve tracers, but the characterization of the high-voltage and high-current (HVHC) region is very challenging because of device power compliance and self-heating. In this paper, we introduce a measurement technique that overcomes self-heating and derives the HVHC region from switching waveforms. The switching transient characteristics of devices are used to determine drain current $(I_{\text{d}})$ as a function of drain–source voltage $(V_{\text{ds}})$ in the HVHC range. Second, we consider another challenging characterization area: measurement of nonlinear capacitances when device is turned on. These capacitance characteristics of on-state devices are important for correcting disagreements between simulations and measurements in turn-off switching transient waveforms and cannot be measured using a conventional capacitance-voltage meter. We introduce S-parameter measurements as an effective method to obtain the capacitance characteristics of both off-state devices and on-state devices. These novel measurement techniques have been applied to the modeling of a SiC device. The extracted device model, a modified version of the popular Angelov−GaN high-electron-mobility transistor model, shows significant improvement in terms of the accuracy of switching waveforms of devices over a wide range of operating conditions.
TL;DR: The degradation induced by ultrahigh total ionizing dose in 65-nm MOS transistors is strongly gate-length dependent as mentioned in this paper, and the threshold voltage often shifts significantly during irradiation and/or high-temperature annealing, depending on transistor polarity, applied field, and irradiation/annealing temperature.
Abstract: The degradation induced by ultrahigh total ionizing dose in 65-nm MOS transistors is strongly gate-length dependent. The current drive decreases during irradiation, and the threshold voltage often shifts significantly during irradiation and/or high-temperature annealing, depending on transistor polarity, applied field, and irradiation/annealing temperature. Ionization in the spacer oxide and overlying silicon nitride layers above the lightly doped drain extensions leads to charge buildup as well as the ionization and/or release of hydrogen. Charge trapped in the spacer oxide or at its interface modifies the parasitic series resistance, reducing the drive current. The released hydrogen transports as H+ with an activation energy of ~0.92 eV. If the direction of the electric field is suitable, the H+ can reach the gate oxide interface and depassivate Si-H bonds, leading to threshold voltage shifts. Newly created interface traps are most prominent near the source or drain. The resulting transistor responses and defect-energy distributions often vary strongly in space and energy as a result, as demonstrated through current–voltage, charge-pumping, and low-frequency noise measurements.
TL;DR: In this paper, a simple improved SiC power mosfet behavioral model is proposed using SPICE language, and the effect of negative turn-off gate drive voltage is considered and a continuously differentiable function is proposed to describe the gate-source capacitance.
Abstract: Silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistors (mosfet s) have been applied in high-power and high-frequency converters recently. To effectively predict characteristics of SiC power mosfet s in the design phase, a simple and valid model is needed. In this paper, a simple improved SiC power mosfet behavioral model is proposed using SPICE language. Key parameters in the model are analyzed and determined in detail, including parasitic parameters of the power module, steady-state characteristic parameters, and nonlinear parasitic capacitances. The effect of negative turn- off gate drive voltage is considered and a continuously differentiable function is proposed to describe the gate–source capacitance. Experimental validation is performed under a double pulse circuit employing an N -channel power mosfet half-bridge module CAS300M12BM2 (Cree Inc.) rated at 300 A/1200 V. The main switching dynamic characteristic parameters of the model have been compared with those of the measured results. The results show that taking gate–source capacitance as a linear value as most previous models do will cause significant turn- on deviations between experiment and simulation results, while the improved model is more accurate compared with the measured results.
TL;DR: In this paper, the SiC mosfet power module exhibits an on-state resistance of 40 mΩ at room-temperature and leakage current in the range of 100 nA, approximately one order of magnitude lower than that of a 6.5 kV Si-IGBT.
Abstract: This paper presents a thorough characterization of 10 kV SiC mosfet power modules, equipped with third-generation mosfet chips and without external free-wheeling diodes, using the inherent SiC mosfet body-diode instead. The static performance (e.g., I DS– V DS , I DS– V GS, C – V characteristics, leakage current, body-diode characteristics) is addressed by measurements at various temperatures. Moreover, the power module is tested in a simple chopper circuit with inductive load to assess the dynamic characteristics up to 7 kV and 120 A. The SiC mosfet power module exhibits an on-state resistance of 40 mΩ at room-temperature and leakage current in the range of 100 nA, approximately one order of magnitude lower than that of a 6.5 kV Si-IGBT. The power module shows fast switching characteristics with the turn-on (turn-on loss) and turn-off (turn-off loss) times of 130 ns (89 mJ) and 145 ns (33 mJ), respectively, at 6.0 kV supply voltage and 100 A current. Furthermore, a peak short-circuit current of 900 A and a short-circuit survivability time of 3.5 μ s were observed. The extracted characterization results could serve as input for power electronic converter design and may support topology evaluation with realistic system performance predictability, using SiC mosfet power modules in the energy transmission and distribution networks.
TL;DR: In this article, the effects of ionizing radiation on β-Ga2O3 metal-oxide-semiconductor field effect transistors (MOSFETs) were investigated.
Abstract: The effects of ionizing radiation on β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated. A gamma-ray tolerance as high as 1.6 MGy(SiO2) was demonstrated for the bulk Ga2O3 channel by virtue of weak radiation effects on the MOSFETs' output current and threshold voltage. The MOSFETs remained functional with insignificant hysteresis in their transfer characteristics after exposure to the maximum cumulative dose. Despite the intrinsic radiation hardness of Ga2O3, radiation-induced gate leakage and drain current dispersion ascribed respectively to dielectric damage and interface charge trapping were found to limit the overall radiation hardness of these devices.
TL;DR: In this paper, a gate driver circuit for SiC mosfet to attenuate the negative voltage spikes in a bridge circuit is proposed, which adopts a simple voltage dividing circuit to generate a negative gate-source voltage as traditional and a passive triggered transistor with a series-connected capacitor to suppress the positive voltage spikes.
Abstract: SiC mosfet has low on-state resistance and can work on high switching frequency, high voltage, and some other tough conditions with less temperature drift, which could provide the significant improvement of power density in power converters. However, for the bridge circuit in an actual converter, high dv/dt during fast switching transient of one mosfet will amplify the negative influence of parasitic components and produce the significant negative voltage spikes on the complementary mosfet , which will threaten its safe operation. This paper proposes a new gate driver circuit for SiC mosfet to attenuate the negative voltage spikes in a bridge circuit. The proposed gate driver adopts a simple voltage dividing circuit to generate a negative gate-source voltage as traditional and a passive triggered transistor with a series-connected capacitor to suppress the negative voltage spikes, which could satisfy the stringent requirements of fast switching SiC mosfet s under the high dc voltage condition with low cost and less complexity. An analysis is presented in this paper based on the simulation and experimental results with the performance comparison evaluated.
TL;DR: In this paper, the authors used the finite-element (FE) model to provide the raw data for establishing the physical resistor-capacitor (RC) network model, where crossheating effects between the MOSFETs are represented with lateral thermal resistors.
Abstract: This paper is concerned with the thermal models which can physically reflect the heat-flow paths in a lightweight three-phase half-bridge two-level SiC power module with six MOSFETs and can be used for coupled electrothermal simulation. The finite-element (FE) model was first evaluated and calibrated to provide the raw data for establishing the physical resistor–capacitor (RC) network model. It was experimentally verified that the cooling condition of the module mounted on a water cooler can be satisfactorily described by assuming the water cooler as a heat exchange boundary in the FE model. The compact RC network consisting of 115 R and C parameters to predict the transient junction temperatures of the six MOSFETS was constructed, where cross-heating effects between the MOSFETs are represented with lateral thermal resistors. A three-step curve fitting method was especially developed to overcome the challenge for extracting the R and C values of the RC network from the selected FE simulation results. The established compact RC network model can physically be correlated with the structure and heat-flow paths in the power module, and was evaluated using the FE simulation results from the power module under realistic switching conditions. It was also integrated into the LTspice model to perform the coupled electrothermal simulation to predict the power losses and junction temperatures of the six MOSFETs under switching frequencies from 5 to 100 kHz which demonstrate the good electrothermal performance of the designed power module.
TL;DR: In this paper, the authors proposed a filter model for the selection of filter component values for a certain $dv/dt$ requirement, where the stray inductance between the power device and the converter output was used as a filter component in combination with an RC-link.
Abstract: In this paper, a novel $dv/dt$ filter is presented targeted for 100-kW to 1-MW voltage source converters using silicon carbide (SiC) power devices. This concept uses the stray inductance between the power device and the converter output as a filter component in combination with an additional small RC -link. Hence, a lossy, bulky, and costly filter inductor is avoided and the resulting output $dv/dt$ is limited to 5–10 kV/ $\mu$ s independent of the output current and switching speed of the SiC devices. As a consequence, loads with $dv/dt$ constraints, e.g., motor drives can be fed from SiC devices enabling full utilization of their high switching speed. Moreover, a filter-model is proposed for the selection of filter component values for a certain $dv/dt$ requirement. Finally, results are shown using a 300-A 1700-V SiC metal–oxide–semiconductor field-effect transistor ( mosfet ). These results show that the converter output $dv/dt$ can be limited to 7.5 kV/ $\mu$ s even though values up to 47 kV/ $\mu$ s were measured across the SiC mosfet module. Hence, the total switching losses, including the filter losses, are verified to be three times lower compared to when the mosfet $dv/dt$ was slowed down by adjusting the gate driver.
TL;DR: In this article, a temperature-dependent SPICE model for SiC power MOSFETs is presented, which describes the static and dynamic behavior and accounts for leakage current and impact ionization.
Abstract: This paper presents a temperature-dependent SPICE model for SiC power MOSFETs. The model describes the static and dynamic behavior and accounts for leakage current and impact ionization. The technology-dependent mosfet parameters are extracted from characterization measurements and datasheets. SPICE standard components and analog behavior modeling blocks are adopted for the model implementation. The model ensures a good agreement with experimental data over a wide temperature range, even under out-of-safe-operating-area (SOA) conditions close to the failure occurrence.
TL;DR: In this article, the authors demonstrate a monolithic integration of vertical GaN MOSFETs with freewheeling Schottky barrier diodes (SBD), based on a 6.7-thick n-p-n heterostructure grown on 6-inch silicon substrates by metal organic chemical vapor deposition.
Abstract: We demonstrate for the first time the monolithic integration of vertical GaN MOSFETs with freewheeling Schottky barrier diodes (SBD), based on a 6.7- $\mu \text{m}$ -thick n-p-n heterostructure grown on 6-inch silicon substrates by metal organic chemical vapor deposition. The anode of the SBD is integrated in the source pad of the MOSFET and the cathode is directly connected to the MOSFET drain through the bottom n+-GaN layer, eliminating the need of any metal wire interconnection. This monolithic integration scheme offers reduced footprint, minimized parasitic components, and simplified packaging. The integrated MOSFET-SBD showed enhancement-mode operation with a threshold voltage of 3.9 V, an ON/ OFF ratio of over 108 and a dramatic improvement in reverse conduction, without degradation in on-state performance from the integration of the SBD. The integrated GaN-on-Si vertical SBD exhibited excellent performance, with a specific on-resistance of 1.6 $\text{m}\Omega \cdot $ cm2, a turn-on voltage of 0.76 V, an ideality factor of 1.5, along with a breakdown voltage of 254 V.
TL;DR: This brief presents a novel ultralow power CMOS voltage reference (CVR) with only 4.6-nW power consumption and measurement results show that the prototype design is capable of providing a 755 mV typical reference voltage with 34 ppm/°C from −15 °C to 140 °C.
Abstract: This brief presents a novel ultralow power CMOS voltage reference (CVR) with only 4.6-nW power consumption. In the proposed CVR circuit, the proportional-to-absolute-temperature voltage is generated by feeding the leakage current of a zero- $V_{\mathrm {gs}}$ nMOS transistor to two diode-connected nMOS transistors in series, both of which are in subthreshold region; while the complementary-to-absolute-temperature voltage is created by using the body diodes of another nMOS transistor. Consequently, low-power operation can be achieved without requiring resistors or bipolar junction transistors, leading to small chip area consumption. The proposed CVR circuit is fabricated in a standard 0.18- $\mu \text{m}$ CMOS process. Measurement results show that the prototype design is capable of providing a 755 mV typical reference voltage with 34 ppm/°C from −15 °C to 140 °C. Moreover, the typical power consumption is only 4.6 nW at room temperature and the active area is only 0.0598 mm2.
TL;DR: In this article, a SiC trench MOSFET with integrated three-level protection (TLP) Schottky barrier diode (SBD), named ITS-TMOS, is proposed and investigated by simulation.
Abstract: A silicon carbide (SiC) trench MOSFET (TMOS) with integrated three-level protection (TLP) Schottky barrier diode (SBD), named ITS-TMOS, is proposed and investigated by simulation. The device features the integrated TLP-SBD that remarkably improves body diode characteristics while guarantees excellent fundamental performance of TMOS. In the blocking state, the P-base region, the trench gate, and the P+ shield at the trench bottom serve as the TLP of the Schottky contact. Each protection assists in depleting the drift region beneath Schottky contact. Benefiting from the self-assembled TLP, the leakage current of the integrated body diode of the ITS-TMOS is significantly reduced. Moreover, the reverse turn-on voltage ( ${V} _{ \mathrm{\scriptscriptstyle ON}}$ ) and the gate charge ( ${Q} _{g}$ ) of the ITS-TMOS are 65% and 18% lower than those of the conventional TMOS, respectively. The improved overall performances make the SiC ITS-TMOS a competitive candidate for high-efficiency and high power density applications.
TL;DR: A model with trap energy levels in the gate dielectric and their misalignment with the channel Fermi level is described, offering the most successful strategy to reduce both Positive and Negative Bias Temperature Instability in a range of gate stacks.
TL;DR: In this paper, a new online precursor of gate-oxide degradation, gate plateau time, was proposed to demonstrate a simultaneous dip-and-rebound variation pattern of four precursors of gateoxide degradation.
Abstract: Gate oxide in power metal–oxide–semiconductor field effect transistors (MOSFETs) degrades over time The degradation leads to an accumulation of oxide-trapped charges within the gate oxide and an accumulation of interface-trapped charges at the oxide–semiconductor surface of power MOSFETs Overtime, such charges significantly alter the electrical parameters of power MOSFETs; to observe this, the electrical parameters are utilized as precursors of gate-oxide degradation The purpose of this paper is threefold: 1) to propose a new online precursor of gate-oxide degradation—the gate plateau time; 2) to demonstrate a simultaneous dip-and-rebound variation pattern of four precursors of gate-oxide degradation: threshold voltage, gate plateau voltage, gate plateau time, and on-resistance; and 3) to compare the shift tendencies of each precursor over the course of gate-oxide degradation The existing studies of gate-oxide degradation mechanisms and their effects on threshold voltage and mobility reduction were extended to correlate a variation of all four precursors using analytical expressions The variation patterns were experimentally verified using high-electric field stressing in two different commercial power MOSFETs The new precursor, the gate plateau time, was found to be a competitive gate-oxide degradation precursor, as it had a higher positive shift than threshold voltage and gate plateau voltage In addition, the threshold voltage was found to be the most sensitive indicator of the negative shift (dip), while the on-resistance and gate plateau time were found to be the most sensitive indicators of the positive shift (rebound)
TL;DR: In this paper, the authors present the characterization and analysis over the temperature range from 4 K to 300 K of both substrate bipolar PNP transistors and MOS transistors in standard and dynamic threshold MOS (DTMOS) configurations implemented in a standard 0.16- $\mu \text{m}$ CMOS technology and demonstrate that employing MOS or DTMOS enables the operation of bandgap references and temperature sensors in standard CMOS technologies even at deep-cryogenic temperatures.
Abstract: Both CMOS bandgap voltage references and temperature sensors rely on the temperature behavior of either CMOS substrate BJTs or MOS transistors in weak inversion. Bipolar transistors are generally preferred over MOS transistors because of their lower spread. However, at deep-cryogenic temperatures, the performance of BJTs deteriorates due to a significant reduction in current gain and a substantial increase in the base resistance. On the contrary, MOS devices show more stable performance even down to 4 K, but accurate device characterization for the design of such a circuit is currently missing. We present the characterization and analysis over the temperature range from 4 K to 300 K of both substrate bipolar PNP transistors and MOS transistors in standard and dynamic threshold MOS (DTMOS) configurations implemented in a standard 0.16- $\mu \text{m}$ CMOS technology. These results demonstrate that employing MOS or DTMOS enables the operation of bandgap references and temperature sensors in standard CMOS technologies even at deep-cryogenic temperatures.
Abstract: Predictions on limits of silicon in power devices have failed spectacularly in the past, but in spite of that, the theory that generated them is still used today and adapted for wide bandgap materials to justify their superior standing against silicon. The superjunction (SJ) MOSFET was the first device to break by more than one order of magnitude the so-called “limit of silicon” above 600 V. The current theory of SJ seems, however, to define a new technology-based limit rather than a material-based only limit. This implies that by scaling down the dimensions, in particular the cell pitch, the on-state resistances can continually decrease by several orders of magnitude, without a boundary. This paper shows that the downscaling of the cell dimensions cannot happen indefinitely and there is a material-dependent intrinsic limit for any power device, which no longer is limited by the geometry or the technology available. Using an analytical approach, and backed up by advanced numerical simulations, we show that the minimum cell pitch is $0.18~\mu \text{m}$ for silicon and $0.05~\mu \text{m}$ for 4H silicon carbide, and further reduction in the cell pitch would result in an increase in the specific resistance. Finally, a new figure of merit for an SJ MOSFET based on a rigorous 2-D analysis is defined.
TL;DR: In this paper, the analytical modeling of split-gate Dielectric Modulated Junction Less Transistor (JLT) for label free electrical detection of bio molecules is presented, where some part of the channel region is opened for providing the binding sites for the bio molecules unlike conventional MOSFET which is enclosed with the gate electrode.
Abstract: This paper represents the analytical modeling of split-gate Dielectric Modulated Junction Less Transistor (JLT) for label free electrical detection of bio molecules. Some part of the channel region is opened for providing the binding sites for the bio molecules unlike conventional MOSFET which is enclosed with the gate electrode. Due to this open area, the surface potential of this region affected by the charged and neutral bio molecules immobilized to the open region of channel. Surface potential of the channel region obtained by solving two-Dimensional Poisson's equation by potential profile having parabolic nature through channel region using technique called conformal mapping. By deriving the surface potential model, derivation of threshold model can also be done. For the detection of bio molecule, variation in to the threshold voltage due to binding of bio molecule in the gate underlap region is the sensing metric.