Showing papers on "MOSFET published in 2019"

Performance Evaluation of High-Power SiC MOSFET Modules in Comparison to Si IGBT Modules

Abstract: The higher voltage blocking capability and faster switching speed of silicon-carbide (SiC) mosfet s have the potential to replace Si insulated gate bipolar transistors (IGBTs) in medium-/low-voltage and high-power applications. In this paper, a state-of-the-art commercially available 325 A, 1700 V SiC mosfet module has been fully characterized under various load currents, bus voltages, and gate resistors to reveal their switching capability. Meanwhile, Si IGBT modules with similar power ratings are also tested under the same conditions. From the test results, several interesting points have been obtained: different to the Si IGBT module, the over-shoot current of the SiC mosfet module increases linearly with the increase of the load current and it has been explained by a model of the over-shoot current proposed in this paper; the induced negative gate voltage due to the complementary device turn- off (crosstalk effect) is more harmful to the SiC mosfet module than the induced positive gate voltage during turn- on when the gate off-voltage is –6 V; the maximum dv / dt and di / dt (electromagnetic interference) during switching transients of the SiC mosfet module are close to those of the Si IGBT module when the gate resistance is larger than 8 Ω but the switching loss of the SiC mosfet module is much smaller; the switching losses of the Si IGBT module are greater than those of the SiC mosfet module even when the gate resistance of the former is reduced to zero. An accurate power loss model, which is suitable for a three-phase two-level converter based on SiC mosfet modules considering the power loss of the parasitic capacitance, has been presented and verified in this paper. From the model, a 96.2% efficiency can be achieved at the switching frequency of 80 kHz and the power of 100 kW.

A critical review of recent progress on negative capacitance field-effect transistors

Abstract: The elegant simplicity of the device concept and the urgent need for a new "transistor" at the twilight of Moore's law have inspired many researchers in industry and academia to explore the physics and technology of negative capacitance field effect transistor (NC-FET). Although hundreds of papers have been published, the validity of quasi-static NC and the frequency-reliability limits of NC-FET are still being debated. The concept of NC - if conclusively demonstrated - will have broad impacts on device physics and technology development. Here, the authors provide a critical review of recent progress on NC-FETs research and some starting points for a coherent discussion.

Active Gate-Driver With dv/dt Controller for Dynamic Voltage Balancing in Series-Connected SiC MOSFETs

Abstract: Series connection of individual semiconductors is an effective way to achieve higher voltage switches. However, the inherent unequal dynamic voltage sharing problem needs to be solved, even when well-matched gate drivers and semiconductors are used. A majority of the existing voltage balancing schemes are developed for slow-switching silicon (Si)-based semiconductors, and are also associated with a significant amount of additional losses in the control circuit or on the switches. In this paper, a novel method is proposed for balancing the dynamic voltages among series-connected silicon carbide (SiC) MOSFETs with high dv/dt rates. The method takes advantage of a small capacitor to provide additional current to the gate of the MOSFETs at turn- off , meaning the switching speed (and thus, the device voltage after turn- off ) is controlled. The proposed method generates negligible losses in the control circuit, and also does not significantly increase the switching losses of the semiconductors. Experimental results are provided to prove the effectiveness of the proposed voltage balancing scheme on two SiC MOSFETs inside a module connected in series. In order to do so, an active gate driver is designed embedding the active dv/dt control scheme as well as other essential functionalities needed for operation of SiC MOSFETs.

20-kW Zero-Voltage-Switching SiC- mosfet Grid Inverter With 300 kHz Switching Frequency

Abstract: Although SiC- mosfet has significant advantages on switching performance over traditional Si-IGBT, the switching loss of SiC- mosfet devices at hard switching rises quickly with the increment in the switching frequency. This has narrowed down further possibilities of improving efficiency and power density of the grid inverter. Zero-voltage-switching (ZVS) space-vector-modulation (SVM) technique is introduced to further push the power density of SiC- mosfet inverter. This paper focuses on the impact of applying the ZVS-SVM to three-phase two-level SiC- mosfet inverter. With the same efficiency requirement the ZVS-SVM SiC inverter can operate at a much higher switching frequency, which gives the opportunity to further reduce the size of passive components. The loss distributions, conversion efficiencies, and volumes of passive components of both a 20-kW SiC- mosfet hard-switching inverter and a 20-kW SiC- mosfet ZVS-SVM inverter have been compared under switching-frequency range from 50 to 300 kHz. Meanwhile, a new metric called “efficiency stiffness” is proposed to compare different inverters with respect to the efficiency performance against switching-frequency characteristics. In addition, high voltage overshoot of SiC- mosfet and high thermal stress of resonant inductor are the two critical issues in the SiC- mosfet ZVS-SVM inverter with high switching frequency. A power module including seven SiC- mosfet bare dies with low stray inductance is designed for ZVS-SVM inverter instead of the existing seven discrete TO-247 package SiC- mosfet s to reduce the voltage overshoots on the switches. Besides, to reduce the power loss of the resonant inductor caused by large amplitude of current at hundreds of kHz excitation frequency, design of the inductor with distributed air gap and optimal winding thickness are studied. A 20-kW SiC- mosfet ZVS-SVM grid inverter prototype is built to verify the proposed design.

Review on SiC MOSFETs High-Voltage Device Reliability Focusing on Threshold Voltage Instability

Abstract: An overview over issues and findings in SiC power MOSFET reliability is given. The focus of this article is on threshold instabilities and the differences to Si power MOSFETs. Measurement techniques for the characterization of the threshold voltage instabilities are compared and discussed. Modeling of the threshold voltage instabilities based on capture–emission-time (CET) maps is a central topic. This modeling approach takes the complete gate bias/temperature history into account. It includes both gate stress polarities and is able to reproduce the short-term threshold variations during application-relevant 50-kHz bipolar ac-stress. In addition, the impact on circuit operation is discussed.

A Megawatt-Scale Medium-Voltage High-Efficiency High Power Density “SiC+Si” Hybrid Three-Level ANPC Inverter for Aircraft Hybrid-Electric Propulsion Systems

Abstract: A hybrid-electric propulsion system is an enabling technology to make the aircraft more fuel saving, quieter, and lower carbide emission. In this article, a megawatt (MW) scale power inverter based on a three-level active neutral-point-clamped (3L-ANPC) topology will be developed. To achieve high efficiency, the switching devices operating at carrier frequency in the power converter are configured by the emerging silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors, while the conventional silicon (Si) insulated-gate bipolar transistors are selected for switches operating at the fundamental output frequency. To obtain high power density, dc bus voltage is increased from the conventional 270 V to medium voltage of 2.4 kV to reduce cable weight. Also, unlike the traditional 400 Hz dominated aircraft ac systems, the rated fundamental output frequency here is boosted to 1.4 kHz to drive the high-speed motor, which helps further to reduce the motor weight. Main hardware development and control modulation strategies are presented. Experimental results are presented to verify the performance of this MW-scale medium-voltage “SiC+Si” hybrid 3L-ANPC inverter. It is shown that the 1-MW 3L-ANPC inverter can achieve a high efficiency of 99% and a high power density of 12 kVA/kg.

Complementary Black Phosphorus Tunneling Field-Effect Transistors.

Abstract: Band-to-band tunneling field-effect transistors (TFETs) have emerged as promising candidates for low-power integration circuits beyond conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) and have been demonstrated to overcome the thermionic limit, which results intrinsically in sub-threshold swings of at least 60 mV/dec at room temperature. Here, we demonstrate complementary TFETs based on few-layer black phosphorus, in which multiple top gates create electrostatic doping in the source and drain regions. By electrically tuning the doping types and levels in the source and drain regions, the device can be reconfigured to allow for TFET or MOSFET operation and can be tuned to be n-type or p-type. Owing to the proper choice of materials and careful engineering of device structures, record-high current densities have been achieved in 2D TFETs. Full-band atomistic quantum transport simulations of the fabricated devices agree quantitatively with the current–voltage measurements, which give...

A Novel Active Gate Driver for Improving Switching Performance of High-Power SiC MOSFET Modules

Abstract: Featuring higher switching speed and lower losses, the silicon carbide mosfet s (SiC mosfet s) are widely used in higher power density and higher efficiency power electronic applications as a new solution. However, the increase of the switching speed induces oscillations, overshoots, electromagnetic interference (EMI), and even additional losses. In this paper, a novel active gate driver (AGD) for high-power SiC mosfet s is presented to fully utilize its potential of high-speed characteristic under different operation temperatures and load currents. The principle of the AGD is based on drive voltage decrement during the voltage and current slopes since high dV/dt and dI/dt are the source of the overshoots, oscillations, and EMI problems. In addition, the optimal drive voltage switching delay time has been analyzed and calculated considering a tradeoff between switching losses and switching stresses. Compared to conventional gate driver with fixed drive voltage, the proposed AGD has the capability of suppressing the overshoots, oscillations, and reducing losses without compromising the EMI. Finally, the switching performance of the AGD was experimentally verified on 1.2 kV/300 A and 1.7 kV/300 A SiC mosfet s in double pulse test under different operation temperatures and load currents. In addition, an EMI discussion and cost analysis were realized for AGD.

Device-Level Thermal Management of Gallium Oxide Field-Effect Transistors

Abstract: The ultrawide bandgap (UWBG) (~4.8 eV) and melt-grown substrate availability of $\beta $ -Ga2O3 give promise to the development of next-generation power electronic devices with dramatically improved size, weight, power, and efficiency over current state-of-the-art WBG devices based on 4H-SiC and GaN. Also, with recent advancements made in gigahertz frequency radio frequency (RF) applications, the potential for monolithic or heterogenous integration of RF and power switches has attracted researchers’ attention. However, it is expected that Ga2O3 devices will suffer from self-heating due to the poor thermal conductivity of the material. Thermoreflectance thermal imaging and infrared thermography were used to understand the thermal characteristics of a MOSFET fabricated via homoepitaxy. A 3-D coupled electrothermal model was constructed based on the electrical and thermal characterization results. The device model shows that a homoepitaxial device suffers from an unacceptable junction temperature rise of ~1500 °C under a targeted power density of 10 W/mm, indicating the importance of employing device-level thermal managements to individual Ga2O3 transistors. The effectiveness of various active and passive cooling solutions was tested to achieve a goal of reducing the device operating temperature below 200 °C at a power density of 10 W/mm. Results show that flip-chip heterointegration is a viable option to enhance both the steady-state and transient thermal characteristics of Ga2O3 devices without sacrificing the intrinsic advantage of high-quality native substrates. Also, it is not an active thermal management solution that entails peripherals requiring additional size and cost implications.

Practical Design Considerations for a Si IGBT + SiC MOSFET Hybrid Switch: Parasitic Interconnect Influences, Cost, and Current Ratio Optimization

Abstract: In this paper, a hybrid switch (HyS) consisting of a large current rated Si insulated-gate bipolar transistor (IGBT) device connected in parallel with a small current rated SiC MOSFET device (low SiC/Si current ratio below unity) is proposed for high-current high-power converters. A systematic analysis involving a parametric sweep to understand the influence and to derive a boundary line of the parasitic interconnection inductance unbalance between Si and SiC within the HyS is presented. The boundary line prescribes the selection of an appropriate gate sequence control. A comprehensive cost analysis was performed using commercial 1.2 kV devices to demonstrate the cost viability of a 1:4 or 1:6 SiC/Si current ratio HyS compared to a SiC MOSFET. An algorithm using a dynamic junction temperature prediction is presented to select an optimum SiC/Si current ratio, which ensures a reliable HyS operation. Using a design example, the possibility of reliability using a 1:6 SiC/Si HyS is studied. A 650 V Si-IGBT- and SiC-MOSFET-based HyS (1:5 SiC/Si current ratio) was successfully demonstrated in a dc–dc boost converter. Also, electromagnetic interference analysis is presented for the HyS-based converter operation.

Short-Circuit Characterization and Protection of 10-kV SiC mosfet

Abstract: This paper presents the characterization of the temperature-dependent short-circuit performance of a Gen3 10 kV/20 A silicon carbide (SiC) mosfet . The test platform consisting of a phase-leg configuration and a fast speed 10-kV solid state circuit breaker, with temperature control, is introduced in detail. A novel FPGA-based short-circuit protection circuit having a response time of 1.5 μ s is proposed and integrated into the gate driver. The short-circuit protection is validated through the platform. The short-circuit characteristics for both the hard switching fault and fault under load (FUL) types at various dc-link voltages (from 500 V to 6 kV) are tested and discussed. The saturation current increases with dc-link voltage and achieves 360 A at 6 kV. Different from low voltage SiC devices, there is no current spike in FUL type of fault. The temperature-dependent short-circuit performance is also presented from 25 to 125 °C. The difference of short-circuit waveforms at various initial junction temperatures can be neglected. A thermal model of the 10-kV SiC mosfet is built for the junction temperature estimation during the short circuit and for analysis of the initial junction temperature impact on the short-circuit performance.

Miniaturization of CMOS.

Abstract: When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

Gate Control Optimization of Si/SiC Hybrid Switch for Junction Temperature Balance and Power Loss Reduction

Abstract: The hybrid switch concept of paralleling a higher-current main Si IGBT and a lower-current auxiliary SiC mosfet offers an improved cost/performance tradeoff in power converters. Currently, the gate control strategy of these two internal devices emphasizes on minimizing the total power loss, and is referred to as the efficiency control mode in this paper. However, there is a serious risk of overheating and reliability degradation of the SiC mosfet if solely relying on this control strategy. In this paper, we propose a new method of gate control optimization, referred to as the thermal balance control mode, to keep the junction temperature of both devices within the specified temperature range, and to minimize the total power loss simultaneously. We first investigate the dependency of the hybrid switch switching losses on the gate control pattern both theoretically and experimentally. We then extensively study control optimization in these two distinct control modes in a dc–dc boost converter. It is found that the thermal balance control mode can achieve almost the same total power loss as the efficiency control mode, but much lower and more balanced junction temperatures of the two internal devices. Experimental results demonstrate that the Si/SiC hybrid switch in an optimal thermal balance control mode can achieve a 163% higher power handling capability in the 20-kHz boost converter or four times higher switching frequency in the 4-kW boost converter than a single IGBT solution with hard switching condition, and yet a considerably lower component cost than a single SiC mosfet solution in the boost converter.

Investigating Impact of Emerging Medium-Voltage SiC MOSFETs on Medium-Voltage High-Power Industrial Motor Drives

Abstract: The SiC MOSFETs are becoming game-changing devices in the field of power electronics, enabling higher temperatures, power densities, and efficiencies. However, at higher voltages than 1.7 kV, these semiconductors are at early stages of development and yet not commercialized. Based on the characterization results of the state-of-the-art 3.3-kV SiC MOSFETs, for the first time, this paper investigates the design and comparison of topologies commercially used for medium-voltage (MV) drives in 4.16–13.8-kV voltage range in the presence of MV SiC MOSFETs. For this purpose, the cascaded H-bridge, modular multilevel converter, and five-level active neutral point clamped (5-L ANPC) topologies are targeted. Design is carried out at 4.16-, 6.9-, and 13.8-kV voltages (4.16 and 6.9 kV in the case of 5-L ANPC) and 3- and 5-MVA power ratings using commercial Si IGBTs as well as latest generation noncommercial 3.3-kV SiC MOSFETs, in order to enable investigation of impact from the emerging MV SiC MOSFETs on motor drive system. Selection of several voltage and power levels is to elucidate behavior of converters at a different voltage and power rating and determine the best option for given operating point. Based on design data, comparisons are done among the mentioned topologies from different points of view including efficiency, passive component requirement, semiconductor utilization, power density, low-speed operation capability, fault containment, and parts count. Experimental results on an H-bridge cell made with 3.3-kV SiC MOSFETs are brought to verify converter modeling in MATLAB environment as well as the conveyed thermal calculations.

Power Loss Model and Efficiency Analysis of Three-Phase Inverter Based on SiC MOSFETs for PV Applications

Abstract: This paper presents the power loss model analysis and efficiency of three-level neutral-point-clamped (3L-NPC) inverter that is widely employed in solar photovoltaic energy conversion system. A silicon carbide (SiC) 3L-NPC inverter is developed in this paper by employing wide bandgap semiconductor power devices, such as SiC MOSFET and SiC diode (SiC D). These devices are used due to their superior characteristics over silicon (Si) semiconductor devices for the reduction of inverter power losses, and as a result, an improving efficiency at the high switching frequency. Accurate and detailed power loss calculation formula and power loss distribution over switching devices of the SiC 3L-NPC inverter are derived according to the modulation technique and inverter operation. The switching energy loss of SiC MOSFET is then measured and determined experimentally via inductive clamp double pulse test (DPT) at the real working condition of the circuit. Afterward, this experimental data is used in the thermal description file of the device’s library of PLECS simulation software to determine the total power loss of SiC 3L-NPC inverter. The developed simulation model replicates the real operating conditions of the 3L-NPC inverter. This method gives results close to the practical test. Finally, the power loss of SiC 3L-NPC inverter is measured and compared with the theoretical results. Furthermore, SiC MOSFET and SiC D are employed to achieve high system efficiency at the high switching frequency. The results verify the features of SiC 3L-NPC inverter, the corresponding modulation technique used and their effects on reducing and improving power loss in solar SiC photovoltaic inverters.

A Novel Non-Intrusive Technique for BTI Characterization in SiC mosfet s

Abstract: Threshold voltage ( V TH) shift due to bias temperature instability (BTI) is a well-known problem in SiC mosfet s that occurs due to oxide traps in the SiC/SiO2 gate interface. The reduced band offsets and increased interface/fixed oxide traps in SiC mosfet s makes this a more critical problem compared to silicon. Before qualification, power devices are subjected to gate bias stress tests after which V TH shift is monitored. However, some recovery occurs between the end of the stress and V TH characterization, thereby potentially underestimating the extent of the problem. In applications where the SiC mosfet module is turned off with a negative bias at high temperature, if the V TH shift is severe enough, there may be electrothermal failure due to current crowding since parallel devices lose synchronization during turn- on . In this paper, a novel method that uses the forward voltage of the body diode during reverse conduction of a small sensing current is introduced as a technique for monitoring V TH shift and recovery due to BTI. This non-invasive method exploits the increased body effect that is peculiar to SiC mosfet s due to the higher body diode forward voltage. With the proposed method, it is possible to non-invasively assess V TH shift dynamically during BTI characterization tests.

Temperature Dependence of Dynamic Performance Characterization of 1.2-kV SiC Power mosfets Compared With Si IGBTs for Wide Temperature Applications

Abstract: Due to the superior material properties, SiC mosfet is a promising candidate switching device for high power density and high efficiency power conversion system. The robustness of switching device under extreme temperature condition becomes a crucial factor to ensure power conversion system safely and continuously operating. In this paper, the temperature dependence of dynamic performance of 1.2-kV 4H-SiC power mosfet s is systematically characterized over such wide temperature range of 90–493 K and compared with 1.2-kV Si IGBT by a layout optimized double pulse tester (DPT). The degradation of dynamic on -resistance related interface traps is analyzed specially and the energy loss caused by degradation is quantified at cryogenic temperatures. Besides, to validate the performance of SiC mosfet under safely and continuously operating conditions for cryogenic temperature application, a hard switched non-isolated dc–dc buck converter is designed and tested to estimate temperature dependence of conversion efficiency under temperature range of 90–290 K. Moreover, the further characterizations are conducted with gate resistance range of 2–20 Ω, load current range of 3–30 A, and converter output current of 5–22.5 A under different switching frequency (up to 150 kHz) to validate high power and high frequency application potential of SiC mosfet .

A Compact Series-Connected SiC MOSFETs Module and Its Application in High Voltage Nanosecond Pulse Generator

Abstract: Nanosecond pulse discharge plasma has many prospects in industrial applications, and high-voltage repetitive nanosecond pulse generators with compact design and light weight have become one of the key issues limiting its development in some applications. This paper presents a high voltage series-connected silicon carbide (SiC) metal-oxide -semiconductor field effect transistor ( MOSFET s) module which can be served as the main switch in a repetitive high-voltage nanosecond pulse generator. This kind of series-connected MOSFET s module with only single external gate driver requiring very few components is very suitable for compact assembly. By analyzing the working principle, three topologies of series-connected MOSFET s module are proposed. The switching behaviors of the three different topologies with four SiC MOSFET s series-connected are compared experimentally. The variation of switching characteristics of series-connection SiC MOSFET s module with different numbers of devices are investigated. The layout is also optimized to shorten pulse front time and improve output pulse quality. Furthermore, a 10 kV SiC MOSFET s module with a turn- on transition time ∼10 ns is developed. The double pulse test result demonstrates excellent switching performances. Finally, a compact and high-voltage pulse generator composed of three 10 kV SiC MOSFET s module is tailored, with a typical rise time ∼40 ns and peak voltage of ∼30 kV.

A Single Gate Driver Based Solid-State Circuit Breaker Using Series Connected SiC MOSFETs

Abstract: Semiconductor devices based solid-state circuit breakers (SSCBs) are promising in the dc power distribution system as protective equipment for their ultrashort action time. This letter proposes a topology of SSCB using series connected silicon carbide (SiC) metal oxide semiconductor field effect transistors (mosfet s), which only requires a single isolated gate driver. The SSCB has very low cost and high reliability because it only has 13 components including passive components and diodes apart from two SiC mosfet s to achieve both balanced voltage distribution during short-circuit interruption duration and reliable positive gate voltage during on -state. The SSCB prototype is built and experimentally verified to interrupt 75 A short-circuit current under the dc-bus voltage of 1200 V within 1.5 μs.

An SiC MOSFET Based Three-Phase ZVS Inverter Employing Variable Switching Frequency Space Vector PWM Control

Abstract: In this paper, a variable switching frequency space vector pulsewidth modulation control is proposed. It is used to achieve zero voltage switching (ZVS) for a three-phase grid-connected voltage source inverter with unity power factor. A wide range of ZVS can be realized without any additional sensors, auxiliary circuits, or current zero crossing detection circuits. The switching frequency can be easily calculated by a digital controller. The frequency variation range in a line cycle is only about 1.5 times at any specific load. An LCL filter is used to attenuate the high current ripples at the inverter side, and active damping is adopted to avoid the resonance and reduce the filter power loss. The switching loss can be significantly reduced by using silicon carbide mosfet s so that the conversion efficiency is high. The power density can also be improved due to the high switching frequency and the low inductance value of the filter. The operating principle, design considerations, and loss analyses are discussed in detail. A 3.5-kW simulation and experimental prototype interfacing a 350–400-V dc with a three-phase 110-V ac grid is developed to verify the performance of the proposed control strategy.

A Low Gate Turn-OFF Impedance Driver for Suppressing Crosstalk of SiC MOSFET Based on Different Discrete Packages

Abstract: Because of higher switching speed of silicon carbide MOSFET, the crosstalk in a phase-leg configuration will be more serious, which hinders the increase of switching frequency and lowers the reliability of the power electronic equipment. The displacement current of the gate–drain capacitor and the voltage drop on the common-source inductors can induce the crosstalk. In order to suppress the crosstalk, this paper proposes a novel gate driver, in which two additional capacitors are added to create the low turn-off gate impedance. With this proposed driver, the common-source parasitic inductor can be decoupled from the gate loop and the displacement current of the gate–drain capacitor can be bypassed. In addition, the operating principle and the parameters design are also analyzed. Finally, the crosstalk in the non-Kelvin package and the Kelvin package are tested by experiments, the validity of the analysis and the effectiveness for suppression the crosstalk are proved as well.

Comprehensive Investigations on Degradations of Dynamic Characteristics for SiC Power MOSFET s Under Repetitive Avalanche Shocks

Abstract: In this work, degradations of dynamic characteristics for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors under repetitive avalanche shocks are investigated in details. With the help of Silvaco TCAD simulations, gate capacitance versus gate voltage ( Cg – Vg ) measurement, and three-terminal charge pumping test, the main damaged position is demonstrated to be the SiC/SiO2 interface along junction FET (JFET) region instead of the body diode where most of the avalanche current passes through. Dominant avalanche degradation mechanism is then confirmed to be the injection of holes into the gate oxide above the JFET region. Since the channel region and the main junction of body diode are not seriously damaged by the avalanche stress, static parameters all remain stable. Meanwhile, due to the injection of holes, the depletion layer beneath the JFET region gets thinner, resulting in the increase of gate-drain capacitance ( C gd) under low drain-source voltage ( V ds) bias condition. It further takes responsibilities for the increments in input capacitance ( Ciss ), output capacitance ( Coss ), and reverse transfer capacitance ( Crss ). Moreover, it results in the extension of Miller plateau. Therefore, the increase of gate charge and delay of turn- off time after being stressed by repetitive avalanche shocks are monitored. Moreover, turn- on and turn- off dissipated energies after different unclamped-inductive-switching stress cycles are extracted. They are rarely influenced by the stress for the overlapping areas of voltage and current during switching procedures are relatively stable.

A Simulation-Based Comparison Between Si and SiC MOSFETs on Single-Event Burnout Susceptibility

Abstract: This paper presents the simulation-based comparison between silicon (Si) and silicon carbide (SiC) MOSFETs on the single-event burnout (SEB) performance for the first time. The safe operation areas (SOAs) regarding SEB are extracted and compared between the two structures when the heavy ions with a different linear energy transfer (LET) strike the sensitive areas of the devices. It is demonstrated that benefiting from the higher doped drift region, SiC MOSFET has a larger SEB threshold voltage than Si MOSFET at low LET range. However, it is the other way around at high LET range, which is attributed to the thicker epitaxy of Si MOSFET. The introduction of buffer layer to enhance the SEB hardness is also discussed. Results indicate that a thicker buffer layer is required for SiC MOSFET to enlarge the SOA, resulting in a more serious degradation of the specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ ). Consequently, other hardening solutions need to be further explored to ensure the safe operation of SiC MOSFET in space applications.

A Line Tunneling Field-Effect Transistor Based on Misaligned Core–Shell Gate Architecture in Emerging Nanotube FETs

Abstract: In this paper, a new architecture based on an intentional misalignment between the core and shell gate is presented for the nanotube tunnel field-effect transistor (NT-TFET). The misaligned core gate overlaps with the source region and facilitates line tunneling in the core-gate–source overlapped region significantly increasing the band-to-band tunneling (BTBT) rate. Using the calibrated 3-D simulations, we show that the proposed misaligned (MG) NT-TFET outperforms the conventional NT-TFET both in terms of static as well as dynamic performance. The MGNT-TFET exhibits an increased ON-state current by nearly 11 times as compared to the conventional NT-TFET with an ultrasteep subthreshold slope (minimum point subthreshold swing of ~5 mV/dec and an average subthreshold slope of 15.5 mV/dec). The higher effective drive current also leads to an improved dynamic performance in the MGNT-TFET

A Non-Segmented PSpice Model of SiC mosfet With Temperature-Dependent Parameters

Abstract: A non-segmented PSpice model of silicon carbide metal-oxide semiconductor field effect transistor (SiC mosfet ) with temperature-dependent parameters is proposed in this paper, which can improve the model's convergence and temperature characteristics. The non-segmented equations and the parameter-extraction method for the proposed SiC mosfet PSpice model are introduced first. Simulation and experiment results are given to verify the correctness of the model while considering the temperature-dependent parameters. The static characteristics of the model are verified by comparing the simulation curves with the static characteristic curves in the SiC mosfet 's datasheet, and its dynamic characteristics are verified by comparing the simulation results with experimental results under different ambient temperatures (25, 75, and 125 °C) based on a double-pulse test platform. Moreover, the proposed non-segmented model, the conventional segmented model, and the model from the manufacturer are adopted and simulated in a full-bridge inverter. The simulation results show better convergence of the proposed non-segmented model. Therefore, an accurate and practical simulation model of SiC mosfet is provided for circuit design in this paper.

Achieving Zero Switching Loss in Silicon Carbide MOSFET

Abstract: Due to the unipolar conduction mechanism, the switching loss of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor ( mosfet ) is reduced significantly when compared with silicon insulated gate bipolar transistor (IGBT). This enables the use of SiC mosfet in high-frequency application. However, the switching loss could still thermally limit the upper limit of the switching frequency. Further reduction of switching loss of SiC mosfet , therefore, remains an open challenge for higher frequency applications. Based on the in-depth revelation of device physics of the switching process, accurate switching loss model is established which highlights the dependence of the switching loss on the gate driving condition. With extreme fast gate driving condition, several loss limitations can be established. The minimum turn- on loss is the energy stored in the output capacitance and the minimum turn- off loss can approach zero or the so-called zero turn- off loss (ZTL). Furthermore, zero switching loss (ZSL) is achieved when utilizing zero-voltage switching turn- on and ZTL turn- off condition. With ZSL, the upper limit of the switching frequency is no long thermally limited which is verified by co-package experimental demonstration. We believe the trailblazing concepts of SiC mosfet switching loss will provide guiding principles for device innovation, package optimization, gate driver improvement, and current possible solutions toward higher frequency applications.

Voltage Overshoot Suppression for SiC MOSFET-Based DC Solid-State Circuit Breaker

Abstract: The transient overvoltage and oscillation phenomena, which are caused by its high switching speed in a solid-state dc circuit breaker based on the silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET), are a crucial problem. This paper presents a simple and reliable method to manage such a problem. An equivalent circuit model for SiC MOSFET is primarily established. The influence of stray inductance in energy absorption loop on the turn-off characteristics of the dc circuit breaker is then analyzed. Subsequently, possible typical overvoltage suppression methods, such as using a resistor–capacitor snubber circuit and increasing gate resistance and parallel capacitance between the gate and source, are simulated and analyzed. Thereafter, a peak voltage suppression method that does not sacrifice the fast switching capability of SiC MOSFET is proposed based on different amounts of energy absorbed by metal oxide varistors (MOVs) with varying voltage levels. A basic principle for selecting a snubber MOV is proposed based on the voltage ratio of a snubber and an energy-absorbing MOV. Finally, the feasibility of the proposed method is verified via a small-scale principle prototype.

Leakage and breakdown mechanisms of GaN vertical power FinFETs

Abstract: This work studies the leakage and breakdown mechanisms of 1.2 kV GaN vertical power FinFETs with edge termination. Two competing leakage and breakdown mechanisms have been identified. The first mechanism is dominated by the electric field, with the leakage current dominated by the electric field in the drift region and destructive breakdown voltage by the peak electric field at the edge termination. The second leakage and breakdown mechanism is controlled by an energy (or potential) barrier in the fin channel. This energy barrier suffers from the drain-induced barrier lowering (DIBL) effect and is highly dependent on gate/drain biases, fin geometries, and GaN/oxide interface charges. The electrons injected into the drift region due to the DIBL effect further lead to trap-assisted space-charge-limited conduction, which results in a nondestructive early breakdown. The barrier height in the fin channel determines which mechanism is dominant; the same device could show either destructive or nondestructive breakdown at different gate biases. To enable the normally off power switching, it is important to suppress the leakage from the second mechanism and maintain a sufficiently high energy barrier in the fin channel up to high drain voltages. Finally, the key device parameters determining the energy barrier in the fin channel have been identified. The findings in this work provide critical device understanding and design guidelines for GaN vertical power FinFETs and other “junctionless” vertical high-voltage power transistors.

Thermal Concept Design of MOSFET Power Modules in Inverter Subsystems for Electric Vehicles

Abstract: The most important key in the thermal management of power electronic devices is the cooling system design. One of the most promising cooling techniques is indirect liquid cooling using cold plates. This paper studies the performance of a liquid cooling system on the junction temperature of a high-power inverter drive utilizing three legs of half-bridge modules (CAS120M12BM2 Silicon Carbide CREE MOSFET). One of the primary objectives is to compare the effect of different geometries and boundary conditions on the thermal performances regarded as maximum junction temperature. Based on the analysis of the liquid cooling, different boundary conditions are proposed and a comparison of the main case study is made against the case of different geometries and boundary conditions. Furthermore, the concept of varying the distance between three half-bridge MOSFETs in an inverter drive is introduced. According to the simulation results, in the best combination, the maximum junction temperature of the module is decreased to 82.2°C when the thermal paste and NX100 materials are selected for the thermal interface material and the heat sink, respectively. In addition, Simulation results show that the best distance between each of the modules in the inverter drive is 10mm spacing.

Short-Circuit Ruggedness and Failure Mechanisms of Si/SiC Hybrid Switch

Abstract: The hybrid switch (HyS) of a higher-current main Si IGBT and a parallel lower-current auxiliary Silicon Carbide (SiC) mosfet offer an improved cost/performance tradeoff for practical power electronic designs. The purpose of this paper is to investigate the short-circuit (SC) ruggedness, failure mechanisms, and techniques for improvement of the Silicon/SiC HyS. The influence of major limiting factors, including dc bus voltage, gate drive voltage, gate control pattern, case temperature, and SiC mosfet sizing are experimentally studied. Two SC failure mechanisms, the thermal runaway and gate interlayer dielectric breakdown of the SiC mosfet are identified using microscopic failure analysis techniques. An optimum gate control selection is proposed to improve the HyS's SC withstanding time with minimum increase in its power loss.