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Showing papers on "MOSFET published in 2020"



Journal ArticleDOI
TL;DR: The future of power conversion at low-to-medium voltages (around 650 V) poses a very interesting debate with all the major device manufacturers releasing different technology variants ranging from SiC Trench MOSFETs, SiC Planar MOSFs, cascode-driven WBG Fets, silicon NPT and Field-stop IGBTs, silicon super-junction MOSfETs and enhancement mode GaN high electron mobility transistors (HEMTs).
Abstract: The future of power conversion at low-to-medium voltages (around 650 V) poses a very interesting debate. At low voltages (below 100 V), the silicon (Si) MOSFET reigns supreme and at the higher end of the automotive medium-voltage application spectrum (approximately 1 kV and above) the SiC power MOSFET looks set to topple the dominance of the Si insulated-gate bipolar transistor (IGBT). At very high voltages (4.5 kV, 6.5 kV and above) used for grid applications, the press-pack thyristor remains undisputed for current source converters and the press-pack IGBTs for voltage source converters. However, around 650 V, there does not seem to be a clear choice with all the major device manufacturers releasing different technology variants ranging from SiC Trench MOSFETs, SiC Planar MOSFETs, cascode-driven WBG FETs, silicon NPT and Field-stop IGBTs, silicon super-junction MOSFETs, standard silicon MOSFETs, and enhancement mode GaN high electron mobility transistors (HEMTs). Each technology comes with its unique selling point with gallium nitride (GaN) being well known for ultrahigh speed and compact integration, SiC is well known for high temperature, electro-thermal ruggedness, and fast switching while silicon remains clearly dominant in cost and proven reliability. This article comparatively assesses the performance of some of these technologies, investigates their body diodes, discusses device reliability, and avalanche ruggedness.

97 citations


Journal ArticleDOI
TL;DR: In this article, the authors review the important engineering achievements and performance milestones of the two major types of vertical Ga2O3 transistors (MOSFETs) and discuss challenges underlying the unique processing approaches to these devices and their implications on device reliability.
Abstract: With projected performance advantages over silicon and incumbent wide-bandgap compound semiconductors, gallium oxide (Ga2O3) has garnered worldwide attention as an ultrawide-bandgap semiconductor material suitable for high-voltage, high-temperature, and radiation-hard electronics. Thanks to recent breakthroughs in crystal growth and device processing technologies, the research and development of vertically oriented Ga2O3 power transistors has made rapid strides. In this article, we review the important engineering achievements and performance milestones of the two major types of vertical Ga2O3 transistors—current aperture vertical metal–oxide–semiconductor field-effect transistors (MOSFETs) and vertical fin-channel MOSFETs. Challenges underlying the unique processing approaches to these devices and their implications on device reliability are also discussed.

73 citations


Journal ArticleDOI
TL;DR: The design and testing of a 10-kV SiC mosfet power module that switches at a record 250 V/ns without compromising the signal and ground integrity due to an integrated screen reduces the common-mode current by ten times and increases the partial discharge inception voltage by more than 50%.
Abstract: The advancement of silicon carbide (SiC) power devices with voltage ratings exceeding 10 kV is expected to revolutionize medium- and high-voltage systems. However, present power module packages are limiting the performance of these unique switches. The objective of this research is to push the boundaries of high-density, high-speed, 10-kV power module packaging. The proposed package addresses the well-known electromagnetic and thermal challenges, as well as the prominent electrostatic and electromagnetic interference (EMI) issues associated with high-speed, 10-kV devices. The high-speed switching and high voltage rating of these devices causes significant EMI and high electric fields. Existing power module packages are unable to address these challenges, resulting in detrimental EMI and partial discharge that limit the converter operation. This article presents the design and testing of a 10-kV SiC mosfet power module that switches at a record 250 V/ns without compromising the signal and ground integrity due to an integrated screen reduces the common-mode current by ten times. This screen connection simultaneously increases the partial discharge inception voltage by more than 50%. With the integrated cooling system, the power module prototype achieves a power density of 4 W/mm3.

69 citations


Journal ArticleDOI
TL;DR: It is turned out the low-cost DMC is easy to design and utilize without complex feedback circuits or control schemes, which is a cost-effective component to guarantee consistent and synchronous on–off trajectories of parallel SiC MOSFETs.
Abstract: Parallel connection of silicon carbide (SiC) MOSFETs is a cost-effective solution for high-capacity power converters. However, transient imbalance current, during turn- on and - off processes, challenges the safety and stability of parallel SiC MOSFETs. In this paper, considering the impact factors of device parameters, circuit parasitics, and junction temperatures, in-depth mathematical models are created to reveal the electrothermal mechanisms of the imbalance current. Moreover, with the incorporation of a differential mode choke (DMC), an effective approach is proposed to suppress the imbalance current among parallel SiC MOSFETs. Physics concepts, operation principles, and design guidelines of the DMC-based suppression method are fully presented. Besides, to reduce the equivalent leakage inductance and equivalent parallel capacitance of the DMC, winding patterns of the DMC are comparatively studied and optimized to suppress turn- off over-voltage and switching ringing. Concerning the influence of winding patterns, load currents, gate resistances, and junction temperatures, experimental results are comprehensively demonstrated to confirm the validity of theoretical models and the function of the proposed DMC-based suppression method. It is turned out the low-cost DMC is easy to design and utilize without complex feedback circuits or control schemes, which is a cost-effective component to guarantee consistent and synchronous on–off trajectories of parallel SiC MOSFETs.

66 citations


Journal ArticleDOI
TL;DR: In this paper, a mechanism based on ion-induced, highly localized energy pulses is demonstrated in simulations and shown to be capable of causing degradation and SEB for both the MOSFETs and junction barrier Schottky (JBS) diodes.
Abstract: Heavy-ion data suggest that a common mechanism is responsible for single-event burnout (SEB) in 1200-V power MOSFETs and junction barrier Schottky (JBS) diodes. Similarly, heavy-ion data suggest a common mechanism is also responsible for leakage current degradation in both devices. This mechanism, based on ion-induced, highly localized energy pulses, is demonstrated in simulations and shown to be capable of causing degradation and SEB for both the MOSFETs and JBS diodes.

59 citations


Journal ArticleDOI
TL;DR: The design and fabrication procedure of a modular dc–ac three-level t-type single phase-leg power electronics building block (PEBB) rated for 100-kW, 1-kV dc-link is reported for the first time.
Abstract: The electric propulsion drives for the more-electric aircraft need lightweight and high-efficiency power converters. Moreover, a modular approach to the construction of the drive ensures reduced costs, reliability, and ease of maintenance. In this article, the design and fabrication procedure of a modular dc–ac three-level t-type single phase-leg power electronics building block (PEBB) rated for 100-kW, 1-kV dc-link is reported for the first time. A hybrid switch (HyS) consisting of a silicon insulated-gate bipolar junction transistor (IGBT) and silicon carbide metal–oxide–semiconductor field-effect transistor (MOSFET) was used as an active device to enable high switching frequencies at high power. The topology and semiconductor selection were based on a model-based design tool for achieving high conversion efficiency and lightweight. Due to the unavailability of commercial three-level t-type power modules, a printed circuit board (PCB) and off-the-shelf discrete semiconductor-based high-power switch was designed for the neutral-point clamping. Also, a nontrivial aluminum-based multilayer laminated bus bar was designed to facilitate the low-inductance interconnection of the selected active devices and the capacitor bank. The measured inductance indicated symmetry of both current commutation loops in the bus bar and value in the range of 28–29 nH. The specific power and volumetric power density of the block were estimated to be 27.7 kW/kg and 308.61 W/in3, respectively. The continuous operation of the block was demonstrated at 48 kVA. The efficiency of the block was measured to be 98.2%.

58 citations


Journal ArticleDOI
TL;DR: In this paper, the impact, root cause, and mitigation techniques of switching oscillations in high frequency power converters enabled by wide bandgap (WBG) and silicon semiconductor devices are reviewed.
Abstract: High-frequency power converters enabled by wide bandgap (WBG) and silicon semiconductor devices offer distinct advantages in power density and dynamic performance. However, switching oscillations are commonly observed in these circuits with undesirable consequences. This paper reviews the impacts, root causes, and mitigation techniques of switching oscillations through literature survey, modeling analysis, and experimental investigation. We categorize the following root causes for oscillations during switching transients: 1) damped oscillation triggered by high di/dt and/or dv/dt coupled with parasitic elements; 2) undamped oscillation of WBG devices as part of a negative resistance oscillator; and 3) semiconductor device physical mechanisms such as the negative capacitance phenomenon due to conductivity modulation in insulated gate bipolar transistors or impact ionization in MOSFETs, the plasma extraction transit-time effect in bipolar power devices, and the reverse conduction property of GaN HEMTs. Furthermore, this paper discusses various circuit techniques to suppress switching oscillations, and techniques of extracting parasitic inductances of power devices.

58 citations


Journal ArticleDOI
TL;DR: In this paper, the authors present a comprehensive analysis of thermal material properties determining the temperature distribution inside SiC power mosfet s using a calibrated technology computer-aided design (TCAD) electrothermal model.
Abstract: Electrothermal modeling of silicon carbide (SiC) power devices is frequently performed to estimate the device temperature in operation, typically assuming a constant thermal conductivity and/or heat capacity of the SiC material. Whether and by how much the accuracy of the resulting device temperature prediction under these assumptions is compromised has not been investigated so far. Focusing on high-temperature operating conditions as found under short circuit (SC), this paper presents a comprehensive analysis of thermal material properties determining the temperature distribution inside SiC power mosfet s. Using a calibrated technology computer-aided design (TCAD) electrothermal model, it is demonstrated that the temperature prediction of SiC power devices under SC operation when neglecting either the top metallization or the temperature dependence of the heat capacity is inaccurate by as high as 25%. The presented analysis enables to optimize compact electrothermal models in terms of accuracy and computational time, which can be used to assess the maximum temperature of SiC power mosfet s in both discrete packages and multichip power modules exposed to fast thermal transients. A one-dimensional thermal network of a SiC power mosfet is proposed based on the thermal material properties, the size of the active area of the device, and its thickness.

52 citations


Journal ArticleDOI
TL;DR: In this paper, a detailed analysis and quantitative measurements of the module parasitic capacitance impact on terms of added switching energy losses, and common-mode currents are investigated using a custom-packaged 10-kV half-bridge SiC MOSFET power modules.
Abstract: Increased switching speeds of wide bandgap (WBG) semiconductors result in a significant magnitude of the displacement currents through power module parasitic capacitances that are inherent in packaging design. This is of increasing concern, particularly in case of newly emerging medium-voltage (MV) SiC MOSFETs since the magnitude of the displacement currents can be several order higher due to the fast switching transients and increased voltage magnitudes of the SiC MOSFETs compared to their Si counter parts. The severity intensifies when the magnitude of the displacement current becomes comparable to a significant fraction of SiC MOSFETs rated current, leading to the worsened impact on the converter electromagnetic interference (EMI) as well as performance in terms of switching losses. The key objective of this article is to provide a detail insight into the impact of the module parasitic capacitances on the SiC MOSFET switching dynamics and losses. To realize this, a well-defined approach to dissect the switching energy dissipation is proposed, based on which the detailed analysis and quantitative measurements of the module parasitic capacitance impact on terms of added switching energy losses, and common-mode currents are investigated using a custom-packaged 10-kV half-bridge SiC MOSFET power modules. The theoretical analysis and experimental results obtained from dynamic as well as static characterization reveal that the impact of the module parasitic capacitance on the switching energy dissipation is twofold and substantially adverse such that it cannot be overlooked considering its intended application in the high-power MV power electronic converters.

52 citations


Journal ArticleDOI
TL;DR: In this paper, the effect of power source parasitic inductance on dynamic current sharing is investigated for paralleled SiC mosfet s with Kelvin-source connection and some guidelines are provided for layout design and application.
Abstract: Parallel connection of silicon carbide (SiC) mosfet s is a popular solution for high-capacity applications. In order to improve the switching speed of paralleled SiC mosfet s, Kelvin-source connection is widely employed. However, the influences of asymmetric layout and unequal junction temperature on current sharing of paralleled SiC mosfet s with Kelvin-source connection are not clear. This article addresses the issue for the first time by theoretical analysis and experimental verifications. The mechanism of current imbalance resulting from asymmetric layout and unequal junction temperature in the case with Kelvin-source connection is comprehensively investigated. Then, some significant discoveries are obtained. The static current sharing performance can be affected by drain and power source parasitic inductance, which is seldom mentioned before. Besides, this article first points out that the effect of power source parasitic inductance on dynamic current sharing is dominant compared with other parasitic inductance. What is more, the thermal–electric analyzing results suggest that there is a risk of thermal runaway for paralleled SiC mosfet s with Kelvin-source connection at high switching frequency due to positively temperature-dependent dynamic current and switching losses. Based on the discoveries, some guidelines are provided for layout design and application of paralleled SiC mosfet s with Kelvin-source connection.

Journal ArticleDOI
TL;DR: In this article, several gate and channel engineered MOSFET structures are analyzed and compared for sub 45 nm technology node for analog/RF performance in terms of IOFF, subthreshold performance parameters and DIBL values.
Abstract: CMOS technology is one of the most frequently used technologies in the semiconductor industry as it can be successfully integrated with ICs. Every two years the number of MOS transistors doubles because the size of the MOSFET is reduced. Reducing the size of the MOSFET reduces the size of the channel length which causes short channel effects and it increases the leakage current. To reduce the short channel effects new designs and technologies are implemented. Double gate MOSFET design has shown improvement in performance as amplifiers over a single MOSFET. Silicon-based MOSFET design can be used in a harsh environment. It has been used in various applications such as in detecting biomolecules. The increase in number of gates increases the current drive capability of transistors. GAA MOSFET is an example of a quadruple gate around the four sides of channel that increases gate control over the channel region. It also increases effective channel width that improves drain current and reduces leakage current keeping short channel effects under limit. Junctionless MOSFET operates faster and uses less power with increase in ON-state current leading to a good value of ION/IOFF ratio. In this paper, several gate and channel engineered MOSFET structures are analyzed and compared for sub 45 nm technology node. A comparison among different MOSFET structures has been made for subthreshold performance parameters in terms of IOFF, subthreshold slope and DIBL values. The analog/RF performance is analyzed for transconductance, effective transistor capacitances, stability factor and critical frequency. The paper also covers different applications of advance MOSFET structures in analog/digital or IoT/ biomedical applications.

Journal ArticleDOI
TL;DR: In this article, the authors presented a vertical GaN planar MOSFET fabricated by an all ion implantation process, which showed an on-resistance of 2.78 mΩ cm2 and a breakdown voltage of 1200 V.
Abstract: We present a vertical GaN planar MOSFET fabricated by an all ion implantation process. The fabricated MOSFET shows an on-resistance of 2.78 mΩ cm2 and a breakdown voltage of 1200 V, by applying the short cell pitch design to reduce the on-resistance and a Mg and N sequential implantation to improve the breakdown voltage of the pn-junction. By evaluating each on-resistance component in the fabricated vertical GaN planar MOSFET using the simultaneously formed test structures, an effective on-resistance of the active region excluding the source parasitic resistance is 1.4 mΩ cm2. Consequently, it was demonstrated that an all ion implantation process can fabricate a vertical GaN planar MOSFET with a high breakdown voltage and low on-resistance. This result will greatly contribute to the realization of GaN power devices.

Journal ArticleDOI
TL;DR: In this paper, the authors investigated the role of threshold voltage shifts caused by the instability mechanisms in accelerated power cycling tests for silicon carbide (SiC) power MOSFETs.
Abstract: In silicon carbide (SiC) power MOSFETs, threshold voltage instability under high-temperature conditions has potential reliability threats to long-term operation. In this paper, the threshold voltage shifts caused by the instability mechanisms in accelerated power cycling tests for SiC MOSFETs are investigated. In conventional power cycling tests, the positive threshold voltage shift can cause successive ON-state resistance increases, which can sequentially increase junction temperature variations gradually under fixed test conditions. In order to distinguish the increased die voltage drop from the bond wire resistance degradation, an independent measurement method is used during the power cycling tests. As the number of cycle increases, SiC die degradation can be observed independently of bond wire increases during the tests. It is studied that the SiC die degradation is associated with the threshold voltage instability mechanisms. Unlike the bond wire lift-off failure, the die degradation and the related die resistance increase can stop the power cycling test earlier than expected. In addition, a new test protocol considering the die degradation is proposed for the power cycling test. By means of power device analyzer, the failure mechanism and the degradation performance of SiC MOSFETs before and after the power cycling test are compared and discussed. Finally, experimental results confirm the role of threshold voltage shifting and identify different failure mechanisms.

Journal ArticleDOI
TL;DR: In this article, a high-density, high-speed, 10-kV power module was proposed for wide bandgap (WBG) power devices with voltage ratings exceeding 10 kV.
Abstract: Wide bandgap (WBG) power devices with voltage ratings exceeding 10 kV have the potential to revolutionize medium- and high-voltage systems due to their high-speed switching and lower ON-state losses. However, the present power module packages are limiting the performance of these unique switches. The objective of this article is to push the boundaries of high-density, high-speed, 10-kV power module packaging. The proposed package addresses the well-known electromagnetic and thermal challenges, as well as the more recent and prominent electrostatic and electromagnetic interference (EMI) issues associated with high-speed, 10-kV devices. The module achieves low and balanced parasitic inductances, resulting in a record switching speed of 250 V/ns with negligible ringing and voltage overshoot. An integrated screen reduces the common-mode (CM) current that is generated by these fast voltage transients by ten times. This screen connection simultaneously increases the partial discharge inception voltage (PDIV) by more than 50%. A compact, medium-voltage termination and system interface design is also proposed in this article. With the integrated jet-impingement cooler, the power module prototype achieves a power density of 4 W/mm3. This article presents the design, prototyping, and testing of this optimized package for 10-kV SiC MOSFETs.

Journal ArticleDOI
Chunhui Liu1, Zhengda Zhang1, Yifu Liu1, Yunpeng Si1, Qin Lei1 
TL;DR: An isolated voltage source gate driver with crosstalk suppression capability is proposed to take full advantage of the inherent high switching speed ability of silicon-carbide devices.
Abstract: Wide-bandgap devices, such as silicon carbide and gallium nitride, have high switching speed potential. However, the actual speed in practical application is limited by circuit parasitics and interaction between high-side switch and low-side switch in a phase-leg configuration, known as crosstalk effect. This article proposes an isolated voltage source gate driver with crosstalk suppression capability to take full advantage of the inherent high switching speed ability of silicon-carbide devices. By applying variable gate voltage through the auxiliary circuit, the crosstalk problem can be mitigated. Using the original gate–source voltage as auxiliary circuit driving signal, the gate driver does not introduce any extra control signals, which avoids additional signal/power isolations and makes the auxiliary circuit very convenient to be implemented on the existing commercial gate driver. The auxiliary circuit makes the gate voltage rise from 0 V other than −5 V when the switch turns on, leading to faster switching speed and lower switching loss compared with a traditional gate driver. LTSPICE simulation and double pulse test experiment based on 1.2-kV/60-A silicon-carbide MOSFETs are conducted to evaluate the crosstalk suppression capability of the proposed gate driver.

Journal ArticleDOI
30 Apr 2020
TL;DR: In this article, a vertical p-type tunnel FET (TFET) co-integrated on the same flake with a 2D MOSFET in a WSe2/SnSe2 material system platform is reported.
Abstract: Two-dimensional/two-dimensional (2D/2D) heterojunctions form one of the most versatile technological solutions for building tunneling field effect transistors because of the sharp and potentially clean interfaces resulting from van der Waals assembly. Several evidences of room temperature band-to-band tunneling (BTBT) have been recently reported, but only few tunneling devices have been proven to break the Boltzmann limit of the minimum subthreshold slope, 60 mV per decade at 300 K. Here, we report the fabrication and characterization of a vertical p-type Tunnel FET (TFET) co-integrated on the same flake with a p-type MOSFET in a WSe2/SnSe2 material system platform. Due to the selected beneficial band alignment and to a van der Waals device architecture having an excellent heterostructure 2D–2D interface, the reported tunneling devices have a sub-thermionic point swing, reaching a value of 35 mV per decade, while maintaining excellent ON/OFF current ratio in excess of 105 at VDS = 500 mV. The TFET characteristics are directly compared with the ones of a WSe2 MOSFET realized on the very same flake used in the heterojunction. The tunneling device clearly outperforms the 2D MOSFET in the subthreshold region, crossing its characteristic over several orders of magnitude of the output current and providing better digital and analog figures of merit.

Journal ArticleDOI
TL;DR: In this paper, a physical model of the threshold voltage in MOSFETs valid down to 4.2 K was presented and validated with measurements in large-area nMOS and pMOS devices of a commercial 28-nm bulk CMOS process.
Abstract: This article presents a physical model of the threshold voltage in MOSFETs valid down to 4.2 K. Interface traps close to the band edge modify the saturating temperature behavior of the threshold voltage observed in cryogenic measurements. Dopant freezeout, bandgap widening, and uniformly distributed traps in the bandgap do not change the qualitative behavior of the threshold voltage over temperature. Care should be taken because dopant freezeout results in a different physical definition of the threshold voltage. Using different definitions changes significantly the threshold current level. The proposed model is experimentally validated with measurements in large-area nMOS and pMOS devices of a commercial 28-nm bulk CMOS process down to 4.2 K. Our modeling results suggest that a pMOS-specific phenomenon in the gate stack is responsible for the non-saturating temperature behavior of the threshold voltage in pMOS devices.

Journal ArticleDOI
TL;DR: In this article, the fracture of the interlayer dielectric, caused by high mechanical stress due to different thermal expansion rates, is the source of failure in the 400-V short-circuit transient.
Abstract: In this study, unique short-circuit failure mechanisms in 1.2-kV SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) at 400 and 800-V dc bias were investigated using experiments and numerical TCAD simulations, taking electrical, thermal, and mechanical stress into account. It was found that the fracture of the interlayer dielectric, caused by high mechanical stress due to different thermal expansion rates, is the source of failure in the 400-V short-circuit transient. The activation of the parasitic bipolar junction transistor under extreme high temperature was confirmed to be the failure mechanism in the 800-V short-circuit transient.

Journal ArticleDOI
TL;DR: In this article, an enhancement-mode (E-mode) β-Ga2O3 metal-oxide-semiconductor field effect transistor (MOSFET) has been achieved by incorporating a laminated-ferroelectric charge storage gate (L-FeG) structure.
Abstract: In this work, an enhancement-mode (E-mode) β-Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) has been achieved by incorporating a laminated-ferroelectric charge storage gate (L-FeG) structure [Al2O3/HfO2/Al2O3/Hf05Zr05O2 (HZO) of 10/5/2/16 nm] The band diagram between L-FeG dielectrics (Al2O3, HfO2, and HZO) and β-Ga2O3 was determined by x-ray photoelectron spectroscopy After applying a gate pulse with an intensity of +18 V and width of 1 ms, the saturation current of the E-mode device was measured to be 232 mA/mm, which shows a negligible current reduction compared to that of 221 mA/mm in a depletion- (D-) mode device In addition, the threshold voltage (VTH) is only shifted by 276% and 218%, respectively, after applying the gate stress and gate-drain stress of 15 V for 104 s Meanwhile, a high breakdown voltage of 2142 V and specific on-resistance (RON,sp) of 2384 mΩ·cm2 were also achieved, which correspond to a state-of-art high power figure of merit of 1925 MW/cm2, showing the great potential of combing the ferroelectric gate stack and lateral Ga2O3 MOSFET as next generation power devices

Journal ArticleDOI
Huaping Jiang1, Xiaohan Zhong1, Guanqun Qiu1, Lei Tang1, Xiaowei Qi1, Li Ran1 
TL;DR: In this article, the authors investigated the threshold voltage drift under dynamic or switching gate stresses and showed that, beside static stress, the switching events can themselves be a driving force of the voltage drift, but this happens only when the dynamic gate stress is bipolar.
Abstract: For silicon carbide (SiC) power MOSFETs, threshold voltage drift is a remaining obstacle in their way to the market. This study experimentally investigates the drift under dynamic or switching gate stresses. It is shown that, beside static stress, the switching events can themselves be a driving force of the threshold voltage drift. However, this happens only when the dynamic gate stress is bipolar. The study extends to show that the dynamic stress induced drift can be sustained. The findings can be used in further work for managing and coping with the threshold voltage drift in device applications.

Journal ArticleDOI
TL;DR: In this paper, a comprehensive analysis of the MOSFET subthreshold swing for a 2D subband with exponential band tail of states is proposed, and a compact analytical expression for the sub-swing as a function of temperature is derived, well accounting for both its cryogenic temperature saturation and classical higher temperature increase.
Abstract: A comprehensive analysis of the MOSFET subthreshold swing for a 2D subband with exponential band tail of states is first proposed. Then, a compact analytical expression for the subthreshold swing as a function of temperature is derived, well accounting for both its cryogenic temperature saturation and classical higher temperature increase. Moreover, a generalized subthreshold swing calculation applicable to the situation where the MOSFET drain current should be evaluated from the conductivity function within the Kubo-Greenwood formalism is developed.

Journal ArticleDOI
TL;DR: In this article, the authors investigated the failure mechanisms of asymmetric and double trench SiC mosfet transistors under single-pulse unclamped inductive switching (UIS) stress.
Abstract: In this article, commercially 1200-V asymmetric and double trench silicon carbide (SiC) metal–oxide–semiconductor-field-effect transistors ( mosfet s) from two manufacturers are investigated by experiment and finite-element simulation under single-pulse unclamped inductive switching (UIS) stress. The variation in avalanche time with mosfet avalanche energy and temperatures dependence of critical avalanche energy and maximum power dissipation are evaluated. It is found that two failure mechanisms are identified, i.e., thermal runaway and gate oxide rupture. For asymmetric trench SiC mosfet s, the failure mode are all thermal runaway at various temperatures. However, the failure mode of double trench SiC mosfet s is thermal runaway or gate oxide rupture, which indicates an instable avalanche robustness under UIS stress. The variations of dc parameters are recorded to evaluate external features of device failure. Furthermore, finite-element simulation is used to reveal the electro-thermal stress inside the device during avalanche. Finally, failed devices are decapsulated to verify the location of failure point from the perspective of the semiconductor die.

Journal ArticleDOI
Wenxi Fei1, Te Bi1, Masayuki Iwataki1, Shoichiro Imanishi1, Hiroshi Kawarada1 
TL;DR: In this paper, a C-Si diamond channel channel and selectively grown undoped or heavily boron-doped (p+) source/drain (S/D) layers have been fabricated, with undoped and p+ S/D exhibited enhancement mode (normally off) FET characteristics.
Abstract: During selective epitaxial growth of diamond through SiO2 masks, silicon terminations were formed on a diamond surface by replacing oxygen terminations under the masks. The high temperature of selective growth and its reductive atmosphere possibly allowed Si atoms in SiO2 to interact with the diamond surface, resulting in silicon terminated diamond (C–Si diamond) composed of a monolayer or thin multi-layers of carbon and silicon bonds on diamond. Diamond metal oxide semiconductor field effect transistors (MOSFETs), with a C–Si diamond channel and selectively grown undoped or heavily boron-doped (p+) source/drain (S/D) layers, have been fabricated. Both the MOSFETs with undoped and p+ S/D exhibited enhancement mode (normally off) FET characteristics. The drain current (IDS) of the undoped device reached −17 mA/mm with threshold voltage (VT) −19 V; the p+ device attained a high IDS −165 mA/mm with a VT of −6 V being one of the best normally off diamond FETs. Transmission electron microscopy and energy dispersive x-ray spectroscopy confirmed the presence of C–Si diamond under the SiO2 masking area. The field effect mobility and interface state density at the C–Si/SiO2 (220 nm)/Al2O3 (100 nm) MOS capacitor are 102 cm2 V−1 s−1 and 4.6 × 1012 cm−2 eV−1, respectively. The MOSFET operation of C–Si diamond provides an alternative approach for diamond.

Journal ArticleDOI
TL;DR: In this article, the authors investigated the switching transient of SiC MOSFET with $RC$ snubber with an analytical model based on the finite-state machine (FSM).
Abstract: As the most popular wide bandgap (WBG) power device, the silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET) has been widely adopted in the power electronics applications and brings in the benefits, including reduced switching losses, enhanced switching frequency, and improved power density. However, the switching oscillation and the electromagnetic interference (EMI) become more serious due to the rapid switching speed of SiC MOSFET. Thus, adding $RC$ snubber branch is considered as an effective method to suppress such unwanted oscillation in the early works. In this article, the switching transient of SiC MOSFET with $RC$ snubber is investigated with an analytical model based on the finite-state machine (FSM). The accuracy of the proposed analytical model can be verified by comparisons between the calculated and measured waveforms during the switching transition. In addition, the impacts of the $RC$ snubber on switching oscillation, switching loss, and high-frequency (HF) EMI noise have been comprehensively investigated based on the model, which shows that the added $RC$ snubber can effectively avoid the switching oscillation and reduce the level of HF EMI without increasing switching loss.

Journal ArticleDOI
TL;DR: In this article, the authors developed a generalized power loss model for Si/SiC hybrid switches with total power loss and junction temperature as outputs and SiC device size as a continuous input variable.
Abstract: Si/SiC hybrid switches of parallel Si insulated-gate bipolar transistor (IGBT) and SiC metal–oxide–semiconductor field-effect transistor ( mosfet ) offer most of the SiC benefits but at a much lower cost in comparison to a full SiC solution. The hybrid switch can be optimized to achieve a minimum total power loss while utilizing the smallest SiC chip size without exceeding the specified maximum junction temperature. In this article, we first develop a generalized power loss model for Si/SiC hybrid switches with total power loss and junction temperature as outputs and SiC device size as a continuous input variable, and then develop a methodology to minimize SiC device size while optimizing total IGBT/ mosfet power loss and ensuring maximum junction temperature still below 150 °C. The power loss model is experimentally validated through both simple double pulse testing and a dc–dc buck converter case study. Using the model and optimization methodology, a minimum SiC device size can be obtained with optimized power loss and safe operation temperature.

Journal ArticleDOI
TL;DR: In this paper, the intrinsic body diode of SiC planar gate MOSFETs was subjected to surge current stress, and the degradation mechanism was discussed when the SiC SBD was removed.
Abstract: Eliminating antiparallel silicon carbide Schottky barrier diode (SiC SBD) and making use of the intrinsic body diode of SiC metal–oxide–semiconductor-field-effect transistor (SiC MOSFET) offer a cost-effectiveness solution without obviously sacrificing the conversion efficiency in some power converter applications. Although the body diode of commercial SiC MOSFET has been qualified by several manufacturers, the reliability of SiC MOSFET under repetitive surge current stress of body diode has not been sufficiently studied. In this article, the new degradation phenomena of SiC MOSFET’s gate oxide are observed, and the degradation mechanism is discussed when the intrinsic body diode of the 1200-V SiC planar gate MOSFETs was subjected to surge current stress. TCAD simulation and experimental measurements indicate that the generation and accumulation of electrons or holes within the gate oxide under surge current stress are the main reasons for the degradation of SiC MOSFET. Finally, a mitigation technique with optimal gate turn-off voltage is suggested to suppress the gate oxide degradation of the SiC MOSFET under surge current stress of its body diode.

Journal ArticleDOI
TL;DR: Experimental results show that an accurate measurement can be achieved with the design considerations regarding precise parameter measurement of the device’s parameter, and the practical issues affecting the measurement accuracy in a multiple-phase setup are investigated.
Abstract: The long-term reliability concerns regarding the latest power devices, e.g., silicon carbide (SiC) MOSFETs, need to be well understood for their rapid and widespread deployment in industrial applications. As an effective reliability assessment, the dc power cycling test is one of the most realistic procedures providing accelerated lifetime tests. In this paper, a dc power cycling setup for SiC power MOSFETs is proposed, and the design methodology is generalized for practicing engineers. At first, the aging-independent junction temperature measurement method is identified to eliminate the laborious recalibration process. Specifically, the electrical parameter changes of commercial SiC MOSFETs are evaluated in a power cycling test. It is observed experimentally that the body diode’s voltage drop at low current and negative gate bias is unaffected by the device/package degradation. Therefore, it is selected for $T_{j}$ measurement in the proposed setup. Following that, the design considerations regarding precise parameter measurement of the device’s parameter are presented. The transient behavior of the proposed test setup is analyzed, and a simulation model is built in LTspice. Based on the model, the effects of gate timing control and paralleled capacitors are investigated for realizing accurate measurements, and the simulation results are verified experimentally in a prototype. In addition, considering the measurement delay in the conditioning circuits and the common-mode noise, the practical issues affecting the measurement accuracy in a multiple-phase setup are investigated in the experiment. Experimental results show that an accurate measurement can be achieved with the design considerations.

Proceedings ArticleDOI
17 Jun 2020
TL;DR: In the paper, the main characteristics of the bi-directional switch and the performance in the four-quadrant of operation are examined and discussed and the device characteristics are compared with the traditional MOSFET and IGBT solutions.
Abstract: The paper deals with a bi-directional switch based on N-channel enhancement-mode GaN FET. The proposed device is a Gate Injection Transistor monolithic solution to reduce the volume of the switch with high current density and blocking voltage of 600V. It features a dual-gate control pin and two power terminal. In the paper, the main characteristics of the bi-directional switch and the performance in the four-quadrant of operation are examined and discussed. The device characteristics are compared with the traditional MOSFET and IGBT solutions. The gate driver design issues are considered to optimize the switching transient of the GaN-based switch. Finally, an experimental evaluation of the GaN FET as the bidirectional circuit breaker is carried out in an AC power supply system to validate the effectiveness of the proposed monolithic new device.

Journal ArticleDOI
TL;DR: In this paper, β-Ga2O3 MOSFETs are demonstrated on heterogeneous GaO3-Al2O 3-Si (GaOISi) substrate fabricated by ion-cutting process.
Abstract: β-Ga2O3 MOSFETs are demonstrated on heterogeneous Ga2O3-Al2O3-Si (GaOISi) substrate fabricated by ion-cutting process. Enhancement (E)- and depletion (D)-mode β-Ga2O3 transistors are realized on by varying the channel thickness ( T ch). E-mode GaOISi transistor with a T ch of 15 nm achieves a high threshold voltage V TH of ~ 8 V. With the same T increase, GaOISi transistors demonstrate more stable ON-current I ON and OFF-current I OFF performance compared to the reported devices on bulk Ga2O3 wafer. Transistors on GaOISi achieve the breakdown voltage of 522 and 391 V at 25°C and 200°C, respectively.