Showing papers on "MOSFET published in 2022"
TL;DR: In this article, the authors investigated the threshold voltage instability under ac gate stresses with different duty ratios, and on and off-state gate voltages, and found that no prominent drift would occur even for bipolar gate stresses, as long as the offstate gate voltage is within (higher than) the critical negative bias voltage which is related to the device fabrication process.
Abstract: With increasing applications of silicon carbide power MOSFETs, more attention is being paid to reliability issues, among which the long-term stability of the gate threshold voltage is of paramount importance. In this article, laboratory experiments are conducted to investigate the threshold voltage instability under ac gate stresses with different duty ratios, and on and off -state gate voltages. It is found that no prominent drift would occur even for bipolar gate stresses, as long as the off -state gate voltage is within (higher than) the critical negative bias voltage which is related to the device fabrication process. Furthermore, not only the gate voltage swing but also the gate voltage polarity will affect the speed of threshold voltage drift when it occurs. The findings are intended for better understanding and management of potential threshold voltage drift in device applications.
27 citations
TL;DR: A general review of the critical processing steps for manufacturing silicon carbide (SiC) MOSFETs and power applications based on SiC power devices are covered in this article . But, the reliability issues of SiC MOS FETs are also briefly summarized.
Abstract: Owing to the superior properties of silicon carbide (SiC), such as higher breakdown voltage, higher thermal conductivity, higher operating frequency, higher operating temperature, and higher saturation drift velocity, SiC has attracted much attention from researchers and the industry for decades. With the advances in material science and processing technology, many power applications such as new smart energy vehicles, power converters, inverters, and power supplies are being realized using SiC power devices. In particular, SiC MOSFETs are generally chosen to be used as a power device due to their ability to achieve lower on-resistance, reduced switching losses, and high switching speeds than the silicon counterpart and have been commercialized extensively in recent years. A general review of the critical processing steps for manufacturing SiC MOSFETs, types of SiC MOSFETs, and power applications based on SiC power devices are covered in this paper. Additionally, the reliability issues of SiC power MOSFET are also briefly summarized.
27 citations
TL;DR: A comprehensive review of state-of-the-art ALTs circuits, operating principles, and induced failure modes for SiC MOSFETs is presented in this paper .
Abstract: Accelerated lifetime tests (ALTs) play a critical role in long-term reliability studies of SiC MOSFETs, including lifetime estimation, failure analysis, and condition monitoring. This article presents a comprehensive review of state-of-the-art ALTs circuits, operating principles, and induced failure modes for SiC MOSFETs. First, the weak spots and corresponding aging mechanisms in both device chip and package are summarized. Next, based on the system operating conditions, ALT configurations and working principles are discussed. Specifically, SiC MOSFET ALTs under normal operation, third-quadrant conduction, and extreme conditions are comprehensively described and compared. Requirements and future trends on ALTs selection and development are comprehensively discussed corresponding to various reliability research directions. Finally, suitable ALTs, corresponding failure locations, and mechanisms are tabulated as the conclusion. This review intends to provide insight on SiC MOSFET reliability test selection, platform development, and test parameter adjustments depending on application requirements.
23 citations
TL;DR: In this paper , the authors demonstrate that the avalanche current in GaN JFETs can be tuned to flow through the source, by using either a mosfet driver with a large gate resistance or an RC-interface driver.
Abstract: The 1.2-kV vertical gallium nitride (GaN) fin-channel junction-gate field-effect transistor (JFET) has recently emerged as a promising candidate for power electronics. It is normally off and has a specific on-resistance smaller than that of 1.2-kV SiC mosfets. A robust avalanche capability has also been reported in vertical GaN JFETs with an avalanche current flowing through the gate. This avalanche path differs from that of power mosfets (via the source) and may pose challenges in gate driver reliability. This article, for the first time, demonstrates that the avalanche current in GaN JFETs can be tuned to flow through the source, by using either a mosfet driver with a large gate resistance or an RC-interface driver. These drivers turn on the fin channel during the device avalanche and obviate a large avalanche current into the gate driver. The carrier dynamics within the GaN JFET under the two avalanche paths have been unveiled by physics-based mixed-mode electrothermal simulations. The critical avalanche energy density in both paths was found to be comparable with the state-of-the-art SiC mosfets. Additionally, the RC-interface driver was shown to outperform the mosfet driver for vertical GaN JFETs. The learning about normally off GaN JFETs was applied to a study of commercial normally on SiC JFETs. Two avalanche paths of a similar nature were observed with different gate drivers. This article provides new insights of the JFET avalanche and show the excellent robustness of the novel 1.2 kV vertical GaN JFET.
22 citations
TL;DR: In this paper , the authors applied a newly developed integrated-charge technique to measure the density of NITs that are active in the above-threshold region of commercial SiC MOSFETs.
Abstract: Characterization of near-interface traps (NITs) in commercial SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) is essential because they adversely impact both performance and reliability by reducing the channel carrier mobility and causing threshold-voltage drift. In this work, we have applied a newly developed integrated-charge technique to measure the density of NITs that are active in the above-threshold region of commercial SiC MOSFETs. The results demonstrate that NITs trap about 10% of the channel electrons for longer than 500 ns.
21 citations
TL;DR: In this article , a half-floating-gate field effect transistor based on MoS2-BN-graphene vdW heterostuctures is proposed for logic operations as a MOSFET, nonvolatile memory as a floating-gate MOSFL, and rectification as a diode.
Abstract: Multifunctional electronic devices that combine logic operation and data storage functions are of great importance in developing next-generation computation. The recent development of van der Waals (vdW) heterostructures based on various two-dimensional (2D) materials have brought exceptional opportunities in designing novel electronic devices. Although various 2D-heterostructure-based electronic devices have been reported, multifunctional devices that can combine logic operations and data storage functions are still quite rare. In this work, we design and fabricate a half-floating-gate field-effect transistor based on MoS2-BN-graphene vdW heterostuctures, which can be used for logic operations as a MOSFET, nonvolatile memory as a floating-gate MOSFET (FG-MOSFET), and rectification as a diode. These results could lay the foundation for various applications based on 2D vdW heterostuctures and inspire the design of next-generation computation beyond the von Neumann architecture.
16 citations
TL;DR: In this paper , the microstructure of atomic layer deposition (ALD) Al 2O3./(110) C-H diamond interface structure is analyzed.
Abstract: Hole concentration of 2-D hole gas (2DHG) on (110) diamond is higher than that on other faces, making it the best choice for power device application. Detailed analysis of atomic layer deposition (ALD) Al2O3/(110) C–H diamond interface structure is of vital importance. MOSFETs with thin (10 nm) and thick (100 nm) ALD Al2O3 layer were made in this study. The microstructure of Al2O3 on (110) C–H diamond was analyzed. Abrupt interface of ALD Al2O3/C–H diamond was observed through high resolution transmission electron microscope (HRTEM). Cascode structure using diamond MOSFETs and enhancement mode silicon MOSFET is fabricated and its high performance is confirmed.
16 citations
15 citations
TL;DR: In this article, an indirect series-connected SiC MOSFET power module using quasi-two-level hybrid-clamp topology is proposed, where the voltages across the devices are automatically balanced with an open-loop modulation strategy to avoid sensors and control algorithm.
Abstract: High-voltage and fast-switching silicon carbide (SiC) power modules are needed to construct high-voltage and high power-density converters. Stacking multiple low-voltage SiC devices to increase the equivalent blocking voltage shows advantages in on -state resistance, current capacity, and cost over one single high-voltage device. An indirect series-connected SiC MOSFET power module using quasi-two-level hybrid-clamp topology is proposed in this article. The voltages across the devices are automatically balanced with an open-loop modulation strategy to avoid sensors and control algorithm. Moreover, only ceramic capacitors are needed besides the MOSFETs and diodes in the topology. Thanks to this, the topology was highly integrated into a power module using SiC dies, which is equivalent to a general-purpose two-level medium-voltage SiC MOSFET power module. The switching losses of the power module show advantages over other stacking methods and even a single high-voltage switch and it can be evaluated with a two-level half-bridge (HB). To achieve this, the automatic voltage-balancing performance is analyzed in detail and the parasitic output capacitance in the topology is investigated, based on which the design considerations are presented. The simulation results from LTspice confirm the voltage-balancing and a 3600V/20A HB power module is built in the lab and the experimental results verify the design.
15 citations
TL;DR: In this article , an ultrathin chips (UTCs) based flexible tactile sensing system for dynamic contact pressure measurement is presented, which comprises of an AlN piezocapacitor based UTCs tightly coupled with another UTCs having metal-oxide-semiconductor field effect transistors (MOSFETs).
Abstract: This paper presents ultrathin chips (UTCs) based flexible tactile sensing system for dynamic contact pressure measurement. The device comprises of an AlN piezocapacitor based UTCs tightly coupled with another UTCs having metal-oxide-semiconductor field-effect transistors (MOSFETs). In this arrangement the AlN piezocapacitor forms the extended gate of MOSFETs. Both AlN piezocapacitor and MOSFET based UTCs are obtained by post-process reduction of wafer thicknesses to ~35μm using backside lapping. The performances of both UTCs were evaluated both before and after thinning and there was no noticeable performance degradation. The UTC-based AlN piezocapacitor exhibited six times higher sensitivity (43.79mV/N) than the thin filmbased AlN sensors. When coupled with MOSFETs based UTC, the observed sensitivity was 0.43N-1. The excellent performance, flexible form factor and compactness shows the potential of presented device in applications such minimal invasive surgical instruments where high-resolution tactile feedback is much needed.
15 citations
TL;DR: In this paper , the authors evaluate the high-bias robustness of SiC MOSFETs under continuous, hard-switched, turn-off stresses with a dc bias higher than the device rated voltage.
Abstract: Evaluating the robustness of power semiconductor devices is key for their adoption into power electronics applications. Recent static acceleration tests have revealed that SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) can safely operate for thousands of hours at a blocking voltage higher than the rated voltage and near the avalanche boundary. This work evaluates the high-bias robustness of SiC MOSFETs under continuous, hard-switched, turn-off stresses with a dc bias higher than the device rated voltage. Under this high-bias switching condition, SiC MOSFETs show degradation in merely tens of hours at 25 °C and tens of minutes at 100 °C. Two independent degradation and failure mechanisms are unveiled: one present in the gate oxide and the other in the bulk-semiconductor regions, featured by the increase in the gate leakage current and the drain leakage current, respectively. The second degradation mechanism has not been previously reported in the literature; it is found to be related to the electron hopping along with the defects in semiconductors generated in the switching tests. The comparison with the static acceleration tests reveals that both degradation mechanisms correlate to the high-bias switching transients rather than the high-bias blocking states. These results suggest the insufficient robustness of SiC MOSFETs under high-bias, hard-switching conditions and the significance of using switching-based tests to evaluate the device robustness.
TL;DR: In this paper , the authors proposed using deep learning to improve the accuracy of the partially-physics-based conventional MOSFET currentvoltage model, which can well predict IV, output conductance, and transconductance of a TCAD-simulated gate-all-around transistor (GAAFET) with outstanding 3-sigma errors of 1.3, 4.1%, and 2.9%, respectively.
Abstract: In this work, we propose using deep learning to improve the accuracy of the partially-physics-based conventional MOSFET current-voltage model. The benefits of having some physics-driven features in the model are discussed. Using a portion of the Berkeley Short-channel IGFET Common-Multi-Gate (BSIM-CMG), the industry-standard FinFET and GAAFET compact model, as the physics model and a 3-layer neural network with 6 neurons per layer, the resultant model can well predict IV, output conductance, and transconductance of a TCAD-simulated gate-all-around transistor (GAAFET) with outstanding 3-sigma errors of 1.3%, 4.1%, and 2.9%, respectively. Implications for circuit simulation are also discussed.
TL;DR: In this paper , the authors characterized the thermal behavior of a 65 nm bulk CMOS transistor by measuring the self-heating effect (SHE) as a function of bias condition.
Abstract: We characterized the thermal behavior of a 65 nm bulk CMOS transistor, by measuring the self-heating effect (SHE) as a function of bias condition. We demonstrated that at a base temperature of 6.5 K the channel temperature of the transistor can increase up to several tens of kelvins due to power dissipation. The thermal behavior of the transistor is determined not only by the thermal response of the transistor itself but also by the thermal properties of the surroundings, i.e., source, drain, bulk, and gate interfaces, metal contacts, and vias. On top of it, the thermal response is bias-dependent through bias dependence of power and self-heating. This information becomes relevant for proper design of integrated circuits for quantum computing or other cryogenic applications, where the circuitry requires to be operated at a stable cryogenic temperature.
TL;DR: In this paper , the authors proposed simple models for dead time optimization in a gallium nitride (GaN) based buck converter under different load conditions, which can be extended for other GaN-based dc-dc converters.
Abstract: A gallium nitride (GaN) field effect transistor can provide superior performance over a Si- mosfet due to its low on -state resistance and low junction capacitances. However, a GaN-based converter exhibits higher dead time loss during reverse conduction. Thus, to improve the efficiency, dead time optimization is required. This article proposes simple models for dead time optimization in a GaN-based buck converter under different load conditions. The proposed models are analytical in nature compared to the conventional models available for Si-based converters. A buck converter prototype is designed using a 100 V GaN device (GS61008P from GaN Systems) and the proposed analytical model-based dead time optimization techniques are validated experimentally. The proposed modeling techniques can be extended for other GaN-based dc–dc converters.
TL;DR: In this paper , an enhancement-mode β-Ga2O3 U-shaped gate trench vertical metaloxide-semiconductor field effect transistor (UMOSFET) featuring a current blocking layer (CBL) was realized by high-temperature annealing under oxygen ambient, which provided electrical isolation between the source and drain electrodes.
Abstract: Vertical metal–oxide–semiconductor field effect transistor (MOSFET) is essential to the future application of ultrawide bandgap β-Ga2O3. In this work, we demonstrated an enhancement-mode β-Ga2O3 U-shaped gate trench vertical metal–oxide–semiconductor field effect transistor (UMOSFET) featuring a current blocking layer (CBL). The CBL was realized by high-temperature annealing under oxygen ambient, which provided electrical isolation between the source and drain electrodes. The CBL thicknesses of different annealing temperatures were derived from C–V measurements and the Fermi level position of the sample surfaces of different annealing temperature was characterized by x-ray photoelectron spectroscopy measurements, indicating good process controllability. Furthermore, photoluminescence spectra were measured to study the effect of oxygen annealing. The fabricated UMOSFET showed normally off with a Vth of 11.5 V, an on-state resistance of 1.48 Ω cm2, a maximum on-state current of 11 A/cm2, an on–off ratio of 6 × 104, and a three-terminal breakdown voltage over 100 V. This work paves a way to form a CBL and broadens the design space for high-power β-Ga2O3 vertical transistors.
TL;DR: In this article, a junction temperature and current extraction method based on the electroluminescence mechanism of the SiC mosfet body diode was presented, which decoupled the relationship between the intensity of the electroluarinescence peaks, the current, and the temperature.
Abstract: In this letter, a junction-temperature and current extraction method is presented based on the electroluminescence mechanism of the SiC mosfet body diode. Starting from the observation of two characteristic peaks in the emitted light spectrum, we proved that the junction temperature and the drain current can be simultaneously measured. This novel method consists of decoupling the relationship between the intensity of the electroluminescence peaks, the current, and the temperature. Through this optical method with inherent electrical isolation, the junction temperature and current in the SiC chip can be simultaneously measured with high precision. The total error of the junction temperature estimation is within ±3 °C, and the error of the current estimation is about ±0.2 A.
TL;DR: In this paper , the single-pulse avalanche capability of two types of 1.2-kV silicon carbide (SiC) trench MOSFETs was investigated through unclamped inductive switching (UIS) testing and numerical TCAD simulation.
Abstract: In this study, the single-pulse avalanche capability of two types of 1.2-kV silicon carbide (SiC) trench MOSFETs was investigated through unclamped inductive switching (UIS) testing and numerical TCAD simulation. It was found that the UIS failure mechanisms differed in the two MOSFETs. In the asymmetric trench MOSFET, the failure was caused by high temperature, which can damage the SiC layer during the UIS transient, whereas in the double-trench MOSFET, the failure was caused by a high electric field concentration at the trench gate bottom oxide, and the physical damage was confirmed by optical beam induced resistance change (OBIRCH) and scanning electron microscopy (SEM) cross-sectional analysis. In addition, the UIS-based local damage phenomenon was investigated with varying inductance. Nonuniform contact resistance may have been a cause of the avalanche current concentration.
TL;DR: In this article , two types of Silicon (Si) IGBT and Silicon Carbide (SiC) hybrid switch (Si/SiC HyS) based three-level active neutral-point-clamped (3L-ANPC) inverter are proposed for high efficiency and low device cost.
Abstract: In this paper, two types of Silicon (Si) IGBT and Silicon Carbide (SiC) hybrid switch (Si/SiC HyS) based three-level active neutral-point-clamped (3L-ANPC) inverter are proposed for high efficiency and low device cost. The proposed Si/SiC HyS-based 3L-ANPC inverters are compared with the full Si IGBT, full SiC MOSFET, and Si with SiC devices-based hybrid 3L-ANPC solutions on the inverter efficiency, power capacity, and device cost. It is shown that compared with the full Si IGBT 3L-ANPC solution, the inverter efficiency improvement by Si/SiC HyS is 2.4% and 1.8% at light load condition and heavy load condition, respectively. Compared to the full SiC MOSFET solution and 2-SiC MOSFET hybrid scheme, the device cost of 2-Si/SiC HyS-based 3L-ANPC is reduced by 78% and 50% with 0.28% and 0.21% maximum inverter efficiency sacrifices. The testing results show that the proposed Si/SiC HyS-based 3L-ANPC inverter is a cost-effective way to realize high inverter efficiency. Between the two proposed Si/SiC HyS-based 3L-ANPC inverters, the 2-Si/SiC HyS-based 3L-ANPC inverter has lower device cost which makes it more suitable for cost-sensitive and high efficiency applications. While the 4-Si/SiC HyS-based 3L-ANPC inverter has higher output power capacity, making it a better candidate for high power density, high power capacity, and high efficiency applications.
TL;DR: In this article , the authors evaluated the applicability of the existing TID test standards to the wide-gap semiconductor silicon carbide (SiC) devices, and the degradation of SiC MOSFETs irradiated at high dose rate is dominated by the positive trapped oxide charges, but the threshold voltages shift due to HT-gate-bias.
Abstract: The total ionizing dose (TID) test standards have been developed based on silicon devices to evaluate the TID response of MOS devices for space use. To estimate the applicability of the existing TID test standards to the wide-gap semiconductor silicon carbide (SiC) devices, 1200 V SiC n-channel MOSFETs from three manufacturers were irradiated with Cobalt-60 $\gamma $ -rays at the high radiation dose rate of 50 rad(Si)/s and the low radiation dose rate of 0.01 rad(Si)/s, respectively. The threshold voltage of devices under test (DUT) shifted toward negative due to the radiation-induced positive oxide trapped charges. Room temperature (RT) anneal of maximum time of 2100 h and high temperature (HT) accelerated anneal of maximum temperature of 105 °C were performed, causing the threshold voltage shift to recover. The synergetic effects of temperature-gate-bias stress and TID on SiC MOSFETs were experimentally studied. In conclusion, the degradation of SiC MOSFETs irradiated at high dose rate is dominated by the positive trapped oxide charges, and the existing TID test standards are applicable to evaluate the SiC MOSFETs radiation hardness level, but the threshold voltages shift due to HT-gate-bias (HTGB) should be evaluated.
TL;DR: In this paper , an online gate-oxide degradation monitoring method for planar SiC mosfets is proposed by extracting gate charge time at a specific range of gate voltage, which is theoretically analyzed and experimentally verified.
Abstract: Gate-oxide degradation has been one of the critical reliability concerns of silicon carbide (SiC) metal–oxide–semiconductor-field-effect transistors (mosfets), which could be monitored through aging-sensitive parameters. In this article, an online gate-oxide degradation monitoring method for planar SiC mosfets is proposed by extracting gate charge time at a specific range of gate voltage. It is based on the findings that the input capacitances of planar SiC mosfets change significantly over gate-oxide degradation, which is theoretically analyzed and experimentally verified. The capacitance variations are converted into the gate charge time as the new aging-sensitive parameter. The new parameter measurement circuit is proposed and integrated into the gate driver module. The article results indicate that the new parameter varies noticeably with gate-oxide degradation and the difference of this parameter caused by junction temperature is much smaller than that caused by degradation. Besides, the parameter is immune to package degradation and load current. The condition monitoring method can be implemented online since the parameter is extracted during the off-state of SiC mosfet devices, which does not affect normal operation. The confirmatory experiment is carried out to verify the correctness of the proposed method.
TL;DR: In this paper , a comparative analysis among four power MOSFET technologies: conventional Silicon (Si), Superjunction (SJ), Silicon Carbide (SiC) and Gallium Nitride (GaN), indicating the voltage, current and frequency ranges of the best performance for each technology.
Abstract: This work presents a comparative analysis among four power MOSFET technologies: conventional Silicon (Si), Superjunction (SJ), Silicon Carbide (SiC) and Gallium Nitride (GaN), indicating the voltage, current and frequency ranges of the best performance for each technology. For this, a database with 91 power MOSFETs from different manufacturers was built. MOSFET losses are related to individual characteristics of the technology: drain-source on-state resistance, input capacitance, Miller capacitance and internal gate resistance. The total losses are evaluated considering a drain-source voltage of 400 V, power levels from 1 kW to 16 kW (1 A–40 A) and frequencies from 1 kHz to 500 kHz. A methodology for selecting power MOSFETs in power electronics applications is also presented.
TL;DR: In this paper , a single β-Ga2O3 nanowire with a diameter of ∼60nm transferred to Si substrate is demonstrated. And the channel of the FinFET depletes much faster than that of the back-gate FET with negative gate bias, which is consistent with the measurement results.
Abstract: A fin field-effect transistor (FinFET) based on single β-Ga2O3 nanowire with a diameter of ∼60 nm transferred to Si substrate is demonstrated. The FinFET device shows good saturation performance within a drain-to-source voltage up to 5 V and exhibits a high on/off ratio of ∼4 × 108, a system-limit low leakage current (∼4 fA), and a relatively low subthreshold swing (∼110 mV). Simulation shows that the channel of the FinFET depletes much faster than that of the back-gate FET with negative gate bias, which is consistent with the measurement results. Moreover, trap-related 1/ f noise and 1/ f2 noise have been identified according to low frequency noise analysis, and a carrier number fluctuation is expected to be the dominant 1/ f noise mechanism in the β-Ga2O3 FinFET in this work.
TL;DR: In this article , the authors demonstrate the iterative impact of high pressure deuterium annealing (HPD) for the better fabrication of semiconductor devices and provide an HPD condition that maximizes on-state current (ION) but minimizes off-state currents (IOFF).
Abstract: In contrast to conventional forming gas annealing (FGA), high-pressure deuterium annealing (HPD) shows a superior passivation of dangling bonds on the Si/SiO2 interface. However, research detailing the process optimization for HPD has been modest. In this context, this paper demonstrates the iterative impact of HPD for the better fabrication of semiconductor devices. Long-channel gate-enclosed FETs are fabricated as a test vehicle. After each cycle of the annealing, device parameters are extracted and compared depending on the number of the HPD. Based on the results, an HPD condition that maximizes on-state current (ION) but minimizes off-state current (IOFF) can be provided.
TL;DR: In this article , the authors present a comprehensive analysis on gate C-voltage measurements of silicon (Si) and silicon carbide (SiC) power mosfet s leading to clear measurement guidelines.
Abstract: Capacitance–voltage (C–V) gate characteristics of power metal-oxide-semiconductor field-effect transistors (mosfet s) play an important role in the dynamic device performance. C–V characterization of the mosfet gate structure is a necessary step for evaluating the mosfet switching behavior and calibrating lumped equivalent capacitances of mosfet compact models. This article presents a comprehensive analysis on gate C–V measurements of silicon (Si) and silicon carbide (SiC) power mosfet s leading to clear measurement guidelines. The requirements on the measurement setup, the selection of equivalent models used for the mosfet capacitance extraction, and the measurement frequency range are defined and supported by an accurate C–V characterization of several Si- and SiC power mosfet s. The results show that the gate-source and gate-drain capacitances should be extracted at a frequency of some 10 kHz rather than at 1 MHz, as typically adopted in datasheets, to avoid parasitic effects introduced by the measurement setup and package. Furthermore, analytical expressions for $C_\text{dg}$ $C_\text{sg}$ mosfet ’s on -state resistance components $R_\text{ch}$ $R_\text{drift}$ mosfet s.
TL;DR: In this article , a pocket implant in the source/drain regions of the FDSOI MOSFET with ground plane (GP) under the influence of back-gate bias (VB) effect is investigated.
TL;DR: In this paper , a structured method to determine the temperature-dependent switching loss of a SiC mosfet in a half-bridge is presented, where a simple methodology has been proposed to analyze the carrier lifetime.
Abstract: In a hard switched mosfet based converter, turn-on energy losses is predominant in the total switching loss. At higher junction temperature the turn-on energy loss further increases due to the reverse recovery effect of the complementary mosfets body diode in a half-bridge configuration. Estimation of the switching loss under different operating conditions at an early design stage is essential for optimizing the thermal design. Analytical switching loss models available in literature are generally used for estimating the switching losses due to its accuracy and simplicity. In this article, the inaccuracy in the reported loss models due to non-inclusion of temperature-dependent reverse recovery characteristics of body diode, is investigated. A structured method to determine the temperature-dependent switching loss of a SiC mosfet in a half-bridge is presented. A simple methodology has been proposed to analyze the carrier lifetime's temperature dependencies of a SiC mosfets body diode. Device parameters from a $\text{1.2}\,\text{kV}/36\,\text{A}$