Showing papers on "Multi-core processor published in 1989"

A 200 MIPS single-chip 1 k FFT processor

Abstract: A device is described which is capable of converting real or complex data from the time domain into the frequency domain, or vice versa Its integrated dual-port workspace RAM, coefficient ROM, and multiple-resource data path allow the computation of a 1024-point complex transform in less than 100 mu s No external memory is needed Multiple devices can be connected in parallel to further increase processing benchmarks The device can also be used as the core processor in the construction of large (>1 k) one- or two-dimensional transforms, but with additional external memory Provision is also made for the computation of real-only data transforms with commensurate reductions in calculation time Six devices in parallel will allow a 1 k transform to be computed at 40-MHz sample rate, equivalent to a 200-MHz radix-2 butterfly rate and an 800-MHz multiplication rate The processor fabricated in 14- mu m CMOS technology, is designed for shrinking to a 1 mu m process The die size is 1316 mm*1366 mm, and the device is assembled in an 84-pin PGA package Power dissipation is 3 W with a 40-MHz system clock >

A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit

Abstract: A microprocessor designed as a processing element of a scientific parallel computer system is described. This chip consists of a simple integer processor core and dedicated floating-point hardware and executes 64-bit floating-point addition, subtraction, and multiplication at a rate of every 50 ns and division every 350 ns. The processor, which employs RISC architecture and Harvard-style bus organization, executes most of the 47 instructions in one 50-ns cycle. The chip is fabricated in 1.2- mu m n-well CMOS technology, containing 440K transistors in a 14.4*13.5-mm/sup 2/ die. The authors provide an overview of the processor, especially focusing on the functions for a parallel system, floating-point hardware, and the new divide algorithm. >

DSP core with parallel module testability

Abstract: A description is given of a custom-designed, 160 K-transistor TMS320C25 DSP (digital signal processor) core processor, which has been combined with a 5 K user-programmable gate array and built-in parallel module testability The research vehicle, designed to analyze practical issues of embedded core DSPs and manufactured in a 1- mu m CMOS process, runs at a 50-MHz clock frequency in the DSP core and has a gate delay of 05 ns (FO=3) in the gate array The parallel module test (PMT) methodology is used to obtain and effectively test the DSP core during manufacturing The method introduces a minimum speed penalty, approximately one quarter of a nanosecond, under normal operation paths and requires only one dedicated TEST pin at the device package The joint test action group PMT system architecture can also support board-level testing >

A single chip modem

Abstract: The authors describe a VLSI CMOS chip designed to be used as a core processor in a high-speed modem (14400 b/s). This VLSI circuit integrated a 16-b fixed-point digital signal processor with its associated data and instruction memories, an analog-digital and digital-analog front-end converter using sigma-delta modulation, and a function called modem adaptor handling the signal-processor clocks and interrupts, the data transfers between the sigma-delta and the processor, and the communications between the single-chip modem (SCM) and slow external input-output devices. The SCM is designed in a submicron CMOS technology. The logic is implemented using a mixed library of standard-cell and gate-array books. >