Multi-core processor

About: Multi-core processor is a research topic. Over the lifetime, 15435 publications have been published within this topic receiving 266049 citations. The topic is also known as: multi-core & multicore processor.

Response-Time Analysis for Single Core Equivalence Framework

Abstract: Multi-core platforms represent the answer of the industry to the increasing demand for computational capabilities. From a real-time perspective, however, the inherent sharing of resources, such as memory subsystem and I/O channels, creates inter-core timing interference among critical tasks and applications deployed on different cores. As a result, modular per-core certification cannot be performed, meaning that: (1) current industrial engineering processes cannot be reused; (2) software developed and certified for single-core chips cannot be deployed on multi-core platforms as is. In this work, we propose the Single Core Equivalence (SCE) technology: a framework of OS-level techniques designed for commercial (COTS) architectures that exports a set of equivalent single-core virtual machines from a multi-core platform. This allows per-core schedulability results to be calculated in isolation and to hold when all the cores of the system are composed together. Thus, SCE allows each core of a multi-core chip to be considered as a conventional single-core chip, ultimately enabling industries to reuse existing software, schedulability analysis methodologies and engineering processes.

Method and apparatus for increasing processor performance

Abstract: A method and apparatus for reducing the number of cycles required to implement load instructions in a data processing system having a Central Processing Unit (CPU). The CPU includes a cache register file, indexed via the offset field of the load instruction, for retaining cache lines from previously executed load instructions. The cache register file is then used by subsequent instructions (e.g. load instructions) requiring the data previously loaded therein. Thus, reducing the cycles normally associated with retrieving the data from the cache for the subsequent instructions.

Synchronization in a Computing System with Multi-Core Processing Devices

Abstract: Systems and methods for synchronization within a processing system use events and/or signals to indicate whether certain buffers (or other system components) are idle. New tasks may be assigned to individual processing elements once they are deemed idle by virtue of certain buffers or components being idle.

Storage performance evaluation of media server based on multi-core network processors

Abstract: Nowadays, the rapid development of digital TV media applications proposes higher requirements on the performance of the media servers This paper discusses such a media server based on multi-core network processors These servers are deployed at the edge of the Internet to provide services independently, catering to the characteristics of digital TV However, it is crucial to find an appropriate storage solution that provides high IO performance for the media servers in such architecture In this paper, based on the disk array and storage cluster technology, several storage solutions for the media server are evaluated and discussed Finally we propose the most appropriate storage solution for the media server at present

Analysis of task scheduling for multi-core embedded systems

Abstract: This thesis performs a research on scheduling algorithms for parallel appli-cations. The main focus is their usage on multi-core embedded systems’ appli-cations. A parallel application can be descr ...