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Showing papers on "Multipath routing published in 1985"


Journal ArticleDOI
TL;DR: In this article, a mixed-integer programming formulation of the Warehouse Location-Routing Problem (WLRP) is presented, which is a generalization of well-known and difficult location and routing problems, such as the location allocation problem and the multi-depot vehicle dispatch problem.
Abstract: The interdependence between distribution center location and vehicle routing has been recognized by both academics and practitioners. However, only few attempts have been made to incorporate routing in location analysis. This paper defines the Warehouse Location-Routing Problem (WLRP) as one of simultaneously solving the DC location and vehicle routing problems. We present a mixed integer programming formulation of the WLRP. Based on this formulation, it can be seen that the WLRP is a generalization of well-known and difficult location and routing problems, such as the Location-Allocation Problem and the Multi-depot Vehicle Dispatch Problem. It is therefore a large and complex problem which cannot be solved using existing mixed-integer programming techniques. We present a heuristic solution method for the WLRP, based on decomposing the problem into three subproblems. The proposed method solves the subproblems in a sequential manner while accounting for the dependence between them. We discuss a large-scale application of the proposed method to a national distribution company at a regional level.

293 citations


Proceedings ArticleDOI
21 Oct 1985
TL;DR: In a VLSI-like model where hardware cost is equated with physical volume, the routing algorithm is used to demonstrate that fat-trees are universal routing networks in the sense that any routing network can be efficiently simulated by a fat-tree of comparable hardware cost.
Abstract: Fat-trees are a class of routing networks for hardwareefficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor λ = Ω(lg n lg lg n) on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(λ) with probability 1-O(1/n). The best previous bound was O(λ lg n) for the off-line problem where switch settings can be determined in advance. In a VLSI-like model where hardware cost is equated with physical volume, we use the routing algorithm to demonstrate that fat-trees are universal routing networks in the sense that any routing network can be efficiently simulated by a fat-tree of comparable hardware cost.

119 citations


Patent
26 Apr 1985
TL;DR: In this article, a non-hierarchial switching system employing a modified unified algorithm for developing link sizes for paths that connect switches and routing sequences for the switches in the system, and further employing means for updating the routing sequences to minimize potential blocking in the network.
Abstract: A nonhierarchial switching system employing a modified unified algorithm for developing link sizes for paths that connect switches in the system and routing sequences for the switches in the system, and further employing means for updating the routing sequences to minimize potential blocking in the network. In one embodiment, the modified unified algorithm develops improved link size determinations by taking advantage of traffic sensitive dynamic routing on the alternate paths available in the nonhierarchial switching system for connecting any switch to any other switch in the system. Updating of the routing sequences is achieved in that embodiment by evaluating the least loaded path for each potential connection of two switches in the system and, when appropriate, by installing the least loaded path as the second choice path in the routing sequence for that potential connection.

117 citations


Journal ArticleDOI
TL;DR: In this article, the authors focus on fault location procedures suitable for use in networks that use distributed routing control through the use of routing tags and message transmission protocols and present a logical superset to those of the centralized control systems (where message routing is dictated by the actions of a global control unit).
Abstract: One class of networks suitable for use in parallel processing systems is the multistage cube network. The authors focus on fault location procedures suitable for use in networks that use distributed routing control through the use of routing tags and message transmission protocols. Faults occurring in the data lines can corrupt message routing tags transmitted over them and thereby cause misrouting of messages. Protocol lines (used in handshaking between network sources and destinations), if faulty, can prevent a message path from being established or can cause the path to `lock up' once transmission of data has begun. These faults have more pronounced effects on the network performance than faults previously considered for centralized routing control systems. The single-fault location procedures presented form a logical superset to those of the centralized control systems (where message routing is dictated by the actions of a global control unit) and can be adapted for use in both circuit and packet switching networks.

31 citations


Proceedings ArticleDOI
01 Jun 1985
TL;DR: This paper has successfully developed the LSI layout system that handles up to polygon blocks with arbitrary outlines by remodeling the line search method often used for PCB routing.
Abstract: Because most LSI layout systems use the Channel Assignment method for routing, they have disadvantages in which block outlines, terminal positions, and placement of blocks are restricted for some reasons and layers with the multilayer routing are used ineffectively. We have successfully developed the LSI layout system that handles up to polygon blocks with arbitrary outlines by remodeling the line search method often used for PCB routing. This paper describes the accelerating of the line search method.

28 citations


Journal ArticleDOI
TL;DR: This paper formalizes this intuition by examining a hard (NP-complete) routing problem, the problem of multi-destination routing, and shows that with only limited information it is impossible to optimize network utilization for the multi-Destination routing problem.
Abstract: In computer networks, message routing is often accomplished by network nodes using local information. The unavailability of global information intuitively makes hard routing problems virtually impossible. This paper formalizes this intuition by examining a hard (NP-complete) routing problem, the problem of multi-destination routing. It is shown that with only limited information it is impossible to optimize network utilization for the multi-destination routing problem. Moreover, it is impossible to even approximate optimality to within a specific tolerance. Several versions of this result are proved; the versions differ in terms of the amount of information available at a node, and the extent to which the problem cannot be approximated. An improved local information algorithm is presented which is best possible amongst local information algorithms.

19 citations


Proceedings ArticleDOI
01 Oct 1985
TL;DR: Analysis of routing and preemption algorithms developed for circuit-switched networks such as the Defense Switched Network indicated that the new routing algorithms provided reduced point-to-point blocking probabilities after damage without adding extra trunking.
Abstract: New routing and preemption algorithms were developed for circuit-switched networks such as the Defense Switched Network that include both broadcast satellite and point-to-point transmission media. Three classes of routing procedures were evaluated: (1) mixed-media routing with fixed routing tables and call processing rules that included crankback and remote earth-station querying, (2) adaptive mixed-media routing which adapted routing tables after network damage, and (3) precedence flooding which routed high-precedence calls using flooding techniques. A new preemption technique called guided preemption was also evaluated. When guided preemption is used, lower precedence calls to preempt are selected after examining the paths of all calls previously routed through a switch. Call paths are added to the call-setup-success common-channel-signalling (CCS) packet at the call destination and then read in and stored within each switch in the call path as this message travels back to the call source. Tools developed to evaluate algorithms included a steady-state network analysis program, a call-by-call simulator, and the EISN testbed network described in a companion paper by H.M. Heggestad. Analytic results with the simulator and the steady-state analysis program indicated that the new routing algorithms provided reduced point-to-point blocking probabilities after damage without adding extra trunking. Best performance was obtained with adaptive mixed-media routing and precedence flooding techniques. Guided preemption preempted fewer low-precedence calls than blind preemption as used in AUTOVON to complete the same number of high-precedence calls.

9 citations


Proceedings ArticleDOI
01 Jun 1985
TL;DR: An efficient routing algorithm for one-and-half layer channel model which is based on single layer metal mask and fixed polysilicon crossunders in CMOS gate array is presented.
Abstract: Channel routing is one of the key problems in the automatic layout design of LSI chips This paper presents an efficient routing algorithm for one-and-half layer channel model which is based on single layer metal mask and fixed polysilicon crossunders in CMOS gate array The algorithm makes parallel horizontal routing in each zone by means of ordering and prediction The nets contend for crossunders in a greedy approach This results in higher probability of routing success and less crossunders occupied (equally less via holes) Furthermore, by inserting interactive information at the same time of execution if necessary, the router provides more chances of 100% routing success

7 citations


Proceedings ArticleDOI
01 Dec 1985
TL;DR: A process is presented for evaluating throughput sensitivity with respect to this parameter along an observed sample path and it is shown that sensitivity analysis can still be performed on-line and provide accurate results.
Abstract: For several classes of queueing networks, on-line perturbation techniques have been used to determine parametric sensitivity of performance. These techniques typically assume "small" perturbations affecting only the occurrence time of events in the system. In networks with dynamic routing, however, queue length perturbations are also inevitably created. In order to investigate the phenomena involved in this case, a simple routing strategy is considered, based on comparing queue length to a given threshold parameter. A process is presented for evaluating throughput sensitivity with respect to this parameter along an observed sample path. Compared to earlier results, some additional information is now needed for tracking state perturbations. It is shown, however, that sensitivity analysis can still be performed on-line and provide accurate results.

3 citations


Proceedings ArticleDOI
01 Jun 1985
TL;DR: A hierarchical gate array architecture and associated design methodology is presented in this article, which is optimized for fast processing and low cost by using a single level of E-beam direct-write programmable interconnect.
Abstract: A hierarchical gate array architecture and associated design methodology are presented. The hierarchical architecture has several advantages over conventional flat structures. A high gate density is achieved by separately optimizing local and global routing tradeoffs. Associated with the physical hierarchy is a hierarchical layout methodology, which reduces the difficulty of placement and routing by decomposing the process into several small independent operations. The architecture is optimized for fast processing and low cost by using a single level of E-beam direct-write programmable interconnect. The hierarchical placement and routing methodology is presented with results of placement and routing test cases. Finally, future enhancements are discussed.

3 citations



Proceedings ArticleDOI
01 Oct 1985
TL;DR: The design philosophy and functional characteristics of the EISN testbed are presented, and a series of routing and control experiments is described, as well as some additional experiments in voice/data integration using the Transmission Control Protocol (TCP) for the data transfers.
Abstract: The Experimental Integrated Switched Network (EISN) was set up to develop and experimentally evaluate new routing and control techniques potentially applicable in the Defense Switched Network, focusing on the new routing and preemption algorithms described in the companion paper [1]. Significant achievements in the EISN effort include establishment of a geographically distributed telecommunications testbed, featuring common channel signalling (CCS), multi-media trunking, and off-the-shelf digital switches with programmable out-board Routing/Control Processors (RCPs). Selected new algorithms have been evaluated in the form of actual implementations on the testbed. A preliminary description of the EISN testbed, its components, and its objectives was given at MILCOM '83 [2], along with earlier steady-state analysis results on the new adaptive routing algorithms. This paper focuses primarily on the EISN testbed as it is now implemented. The design philosophy and functional characteristics of the testbed are presented, and a series of routing and control experiments is described, as well as some additional experiments in voice/data integration using the Transmission Control Protocol (TCP) for the data transfers. The routing experiments are aimed at validating the logic and the CCS protocols developed for the new routing and preemption algorithms described in the companion paper.

Journal ArticleDOI
01 Sep 1985
TL;DR: Simulation of this routing strategy shows that maximum network throughput can be increased substantially compared to a single path routing strategy, and that stable multiple path routing is achieved without packet disordering.
Abstract: A path-oriented routing strategy is proposed for packet switching networks with end-to-end internal protocols. It allows switch pairs to communicate over multiple paths (for better network throughput), while maintaining knowledge of user connections at the network's endpoints only. The most significant aspect of this strategy lies in its flow assignment method. A distributed loop-free shortest path algorithm assigns a number to a path at the time it is created and this number remains valid through shortest path changes. Consequently, existing traffic can be maintained on existing paths, while new traffic is assigned to the current shortest paths. Stable multiple path routing is thus achieved without packet disordering. Abnormal conditions such as trunk failure and recovery and trunk congestion are dealt with by tagging routing updates with update causes. Simulation of this routing strategy shows that maximum network throughput (under a certain congestion constraint) can be increased substantially compared to a single path routing strategy.

Proceedings Article
01 Jan 1985
TL;DR: The fault location procedures presented form a logi- cal superset to those of the centralized control systems (where message routing is dictated by the actions of a global control unit) and can be adapted for use in both circuit and packet switching networks.
Abstract: One class of networks suitable for use in parallel processing systems is the multistage cube network. Unfor- tunately, the cube network is not fault tolerant and any single failure within the network can prevent some source- destination communications. Cube networks with "extra" stages can be constructed that permit faults to be bypassed — providing the exact location of the fault is known. This paper focuses on fault location procedures suitable for use in net- works that employ distributed routing control through the use of routing tags and message transmission protocols. Faults occurring in the data lines can corrupt message routing tags transmitted over them and thereby cause misrouting of mes- sages. Protocol lines (used in handshaking between network sources and destinations), if faulty, can prevent a message path from being established or can cause the path to "lock- up" once transmission of data has begun. These faults have more pronounced effects on the network performance than faults previously considered for centralized routing control systems. The fault location procedures presented form a logi- cal superset to those of the centralized control systems (where message routing is dictated by the actions of a global control unit) and can be adapted for use in both circuit and packet switching networks.

Journal ArticleDOI
TL;DR: An adaptation of the bit-reversal algorithm is presented which computes the control bits ‘on-line’ during the execution of the algorithm.

Journal ArticleDOI
TL;DR: An approach to the solution of the dynamic routing problem in a queueing network is presented, based on Lagrangian duality and decomposition techniques, which can be obtained by a multilevel off-line computational procedure.
Abstract: An approach to the solution of the dynamic routing problem in a queueing network is presented in the paper, based on Lagrangian duality and decomposition techniques. A numerical solution can be obtained by a multilevel off-line computational procedure. The considered network has deterministic inputs and initial state, and the optimization problem is in discrete time. Link capacity and queue length constraints are taken into account.