Multiplier (economics)

Abstract: We argue that the government-spending multiplier can be much larger than one when the zero lower bound on the nominal interest rate binds. The larger the fraction of government spending that occurs while the nominal interest rate is zero, the larger the value of the multiplier. After providing intuition for these results, we investigate the size of the multiplier in a dynamic, stochastic, general equilibrium model. In this model the multiplier effect is substantially larger than one when the zero bound binds. Our model is consistent with the behavior of key macro aggregates during the recent financial crisis.

Abstract: It is suggested that the economics of present large-scale scientific computers could benefit from a greater investment in hardware to mechanize multiplication and division than is now common. As a move in this direction, a design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step. Using straightforward diode-transistor logic, it appears presently possible to obtain products in under 1, ?sec, and quotients in 3 ?sec. A rapid square-root process is also outlined. Approximate component counts are given for the proposed design, and it is found that the cost of the unit would be about 10 per cent of the cost of a modern large-scale computer.

Abstract: An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails. With this technique, the multiplication efficiency and current driving capability are both independent of the number of multiplier stages. A mathematical model and simple equivalent circuit have been developed for the multiplier and the predicted performance agrees well with measured results. A multiplier has already been incorporated into a TTL compatible nonvolatile quad-latch, in which it occupies a chip area of 600 /spl mu/m/spl times/240 /spl mu/m. It is operated with a clock frequency of 1 MHz and can supply a maximum load current of about 10 /spl mu/A. The output impedance is 3.2 M/spl Omega/.

Abstract: This paper describes a technique for the design of two-signal four-quadrant multipliers, linear on both inputs and useful from dc to an upper frequency very close to the f/SUB t/ of the transistors comprising the circuit. The precision of the product is shown to be limited primarily by the matching of the transistors, particularly with reference to emitter-junction areas. Expressions are derived for the nonlinearities due to various causes.

Abstract: This paper explains the key factors that determine the output multiplier of government purchases in New Keynesian models, through a series of simple examples that can be solved analytically. Sticky prices or wages allow for larger multipliers than in a neoclassical model, though the size of the multiplier depends crucially on the monetary policy response. A multiplier well in excess of 1 is possible when monetary policy is constrained by the zero lower bound, and in this case welfare increases if government purchases expand to partially flll the output gap that arises from the inability to lower interest rates.