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Multistage interconnection networks

About: Multistage interconnection networks is a research topic. Over the lifetime, 1324 publications have been published within this topic receiving 23860 citations. The topic is also known as: MINs.


Papers
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Journal ArticleDOI
TL;DR: In this article, the authors describe a method of designing arrays of crosspoints for use in telephone switching systems in which it will always be possible to establish a connection from an idle inlet to an idle outlet regardless of the number of calls served by the system.
Abstract: This paper describes a method of designing arrays of crosspoints for use in telephone switching systems in which it will always be possible to establish a connection from an idle inlet to an idle outlet regardless of the number of calls served by the system.

1,778 citations

Journal ArticleDOI
TL;DR: This paper discusses the design of a primary memory system for an array processor which allows parallel, conflict-free access to various slices of data, and subsequent alignment of these data for processing, and a network based on Stone's shuffle-exchange operation is presented.
Abstract: This paper discusses the design of a primary memory system for an array processor which allows parallel, conflict-free access to various slices of data (e.g., rows, columns, diagonals, etc.), and subsequent alignment of these data for processing. Memory access requirements for an array processor are discussed in general terms and a set of common requirements are defined. The ability to meet these requirements is shown to depend on the number of independent memory units and on the mapping of the data in these memories. Next, the need to align these data for processing is demonstrated and various alignment requirements are defined. Hardware which can perform this alignment function is discussed, e.g., permutation, indexing, switching or sorting networks, and a network (the omega network) based on Stone's shuffle-exchange operation [1] is presented. Construction of this network is described and many of its useful properties are proven. Finally, as an example of these ideas, an array processor is shown which allows conflict-free access and alignment of rows, columns, diagonals, backward diagonals, and square blocks in row or column major order, as well as certain other special operations.

1,210 citations

Journal ArticleDOI
TL;DR: A baseline network and a configuration concept are introduced to evaluate relationships among some proposed multistage interconnection networks and it is proven that the data manipulator, flip network, omega network, indirect binary n-cube network, and regular SW banyan network are topologically equivalent.
Abstract: A baseline network and a configuration concept are introduced to evaluate relationships among some proposed multistage interconnection networks. It is proven that the data manipulator (modified version), flip network, omega network, indirect binary n-cube network, and regular SW banyan network (S = F = 2) are topologically equivalent. The configuration concept facilitates developing a homogeneous routing algorithm which allows one-to-one and one- to-many connections from an arbitrary side of a network to the other side. This routing algorithm is extended to full communication which allows connections between terminals on the same side of a network. A conflict resolution scheme is also included. Some practical implications of our results are presented for further research.

799 citations

Journal ArticleDOI
TL;DR: A general class of hypercube structures is presented in this paper for interconnecting a network of microcomputers in parallel and distributed environments and the performance is compared to that of other existing hyper cube structures such as Boolean n-cube and nearest neighbor mesh computers.
Abstract: A general class of hypercube structures is presented in this paper for interconnecting a network of microcomputers in parallel and distributed environments. The interconnection is based on a mixed radix number system and the technique results in a variety of hypercube structures for a given number of processors N, depending on the desired diameter of the network. A cost optimal realization is obtained through a process of discrete optimization. The performance of such a structure is compared to that of other existing hypercube structures such as Boolean n-cube and nearest neighbor mesh computers.

786 citations

Journal ArticleDOI
TL;DR: The analysis shows that delta networks have a far better performance per cost than crossbars in large multiprocessing systems.
Abstract: A class of interconnection networks based on some existing permutation networks is described with applications to processor to memory communication in multiprocessing systems. These networks, termed delta networks, allow a direct link between any processor to any memory module. The delta networks and full crossbars are analyzed with respect to their effective bandwidth and cost. The analysis shows that delta networks have a far better performance per cost than crossbars in large multiprocessing systems.

752 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20234
20226
20218
202010
201911
20187