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NAND gate

About: NAND gate is a research topic. Over the lifetime, 9596 publications have been published within this topic receiving 109951 citations.


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Journal ArticleDOI
TL;DR: This paper demonstrates an inverter, a NAND gate, a static random access memory, and a five-stage ring oscillator based on a direct-coupled transistor logic technology based on the semiconducting nature of molybdenum disulfide.
Abstract: Two-dimensional (2D) materials, such as molybdenum disulfide (MoS2), have been shown to exhibit excellent electrical and optical properties. The semiconducting nature of MoS2 allows it to overcome the shortcomings of zero-bandgap graphene, while still sharing many of graphene’s advantages for electronic and optoelectronic applications. Discrete electronic and optoelectronic components, such as field-effect transistors, sensors, and photodetectors made from few-layer MoS2 show promising performance as potential substitute of Si in conventional electronics and of organic and amorphous Si semiconductors in ubiquitous systems and display applications. An important next step is the fabrication of fully integrated multistage circuits and logic building blocks on MoS2 to demonstrate its capability for complex digital logic and high-frequency ac applications. This paper demonstrates an inverter, a NAND gate, a static random access memory, and a five-stage ring oscillator based on a direct-coupled transistor logic...

1,555 citations

Proceedings Article
01 Jun 2006
TL;DR: Damascened metal gate SONOS type cell in the vertical NAND flash string is realized by a unique dasiagate replacementpsila process and conventional bulk erase operation of the cell is successfully demonstrated.
Abstract: Vertical NAND flash memory cell array by TCAT (terabit cell array transistor) technology is proposed. Damascened metal gate SONOS type cell in the vertical NAND flash string is realized by a unique dasiagate replacementpsila process. Also, conventional bulk erase operation of the cell is successfully demonstrated. All advantages of TCAT flash is achieved without any sacrifice of bit cost scalability.

747 citations

Journal ArticleDOI
TL;DR: In this brief, a memristor-only logic family, i.e., memristar-aided logic (MAGIC), is presented, and in each MAGIC logic gate, memristors serve as an input with previously stored data, and an additional Memristor serves as an output.
Abstract: Memristors are passive components with a varying resistance that depends on the previous voltage applied across the device. While memristors are naturally used as memory, memristors can also be used for other applications, including logic circuits. In this brief, a memristor-only logic family, i.e., memristor-aided logic (MAGIC), is presented. In each MAGIC logic gate, memristors serve as an input with previously stored data, and an additional memristor serves as an output. The topology of a MAGIC nor gate is similar to the structure of a common memristor-based crossbar memory array. A MAGIC nor gate can therefore be placed within memory, providing opportunities for novel non-von Neumann computer architectures. Other MAGIC gates also exist (e.g., and , or , not , and nand ) and are described in this brief.

617 citations

Journal ArticleDOI
09 Apr 1999-Science
TL;DR: A functioning logic gate based on quantum-dot cellular automata is presented, where digital data are encoded in the positions of only two electrons, and theoretical simulations of the logic gate output characteristics are in excellent agreement with experiment.
Abstract: A functioning logic gate based on quantum-dot cellular automata is presented, where digital data are encoded in the positions of only two electrons. The logic gate consists of a cell, composed of four dots connected in a ring by tunnel junctions, and two single-dot electrometers. The device is operated by applying inputs to the gates of the cell. The logic AND and OR operations are verified using the electrometer outputs. Theoretical simulations of the logic gate output characteristics are in excellent agreement with experiment.

594 citations

Journal ArticleDOI
TL;DR: In this article, the concept of floating-gate interference in flash memory cells was introduced for the first time and the floating gate interference causes V/sub T/ shift of a cell proportional to the V/ sub T/ change of the adjacent cells.
Abstract: Introduced the concept of floating-gate interference in flash memory cells for the first time The floating-gate interference causes V/sub T/ shift of a cell proportional to the V/sub T/ change of the adjacent cells It results from capacitive coupling via parasitic capacitors around the floating gate The coupling ratio defined in the previous works should be modified to include the floating-gate interference In a 012-/spl mu/m design-rule NAND flash cell, the floating-gate interference corresponds to about 02 V shift in multilevel cell operation Furthermore, the adjacent word-line voltages affect the programming speed via parasitic capacitors

593 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023184
2022328
2021189
2020323
2019356
2018357