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Showing papers on "Nanoelectronics published in 1997"


Journal ArticleDOI
01 Apr 1997
TL;DR: In particular, linear threshold networks, the associative matrix, self-organizing feature maps, and cellular arrays are investigated from the viewpoint of their potential significance for nanoelectronics and their usefulness to system implementations with quantum-effect devices is given.
Abstract: A large number of devices, a limitation of wiring, and very low power dissipation density are design constraints of future nanoelectronic circuits composed of quantum-effect devices. Furthermore, functional integration, which is the possibility of exploiting quantum effects to obtain a function specific behavior, becomes a core design principle. This paper analyzes the effect of this technological progress on the design of nanoelectronic circuits and describes computational paradigms revealing novel features such as distributed storage, fault tolerance, self-organization, and local processing. In particular, linear threshold networks, the associative matrix, self-organizing feature maps, and cellular arrays are investigated from the viewpoint of their potential significance for nanoelectronics. Although these concepts have already been implemented using present technologies, the intention of this paper is to give an impression of their usefulness to system implementations with quantum-effect devices.

76 citations


Journal ArticleDOI
01 Apr 1997
TL;DR: A nanoelectronic implementation of Boolean logic circuits is described where logic functionality is realized through charge interactions between metallic dots self-assembled on the surface of a double-barrier resonant tunneling diode (RTD) structure.
Abstract: A nanoelectronic implementation of Boolean logic circuits is described where logic functionality is realized through charge interactions between metallic dots self-assembled on the surface of a double-barrier resonant tunneling diode (RTD) structure. The primitive computational cell in this architecture consists of a number of dots with nearest neighbor (resistive) interconnections. Specific logic functionality is provided by appropriate rectifying connections between cells. We show how basic logic gates, leading to combinational and sequential circuits, can be realized in this architecture. Additionally, architectural issues including directionality, fault tolerance, and power dissipation are discussed. Estimates based on the current-voltage characteristics of RTD's and the capacitance and resistance values of the interdot connections indicate that static power dissipation as small as 0.1 nW/gate and switching delay as small as a few picoseconds can be expected. We also present a strategy for fabricating/synthesizing such systems using chemical self-organizing/self-assembly phenomena. The proposed synthesis procedure utilizes several chemical self-assembly techniques which have been demonstrated recently, including self-assembly of uniform arrays of close-packed metallic dots with nanometer diameters, controlled resistive linking of nearest neighbor dots with conjugated organic molecules and organic rectifiers.

66 citations


Journal ArticleDOI
TL;DR: In this article, the fabrication of single electron tunneling devices using silicon nanocrystals using very high-frequency plasma processing is described, and Coulomb staircase appears in I-V characteristics even at room temperature.
Abstract: This paper presents results on the fabrication of single electron tunneling devices using silicon nanocrystals. We prepare silicon nanocrystals of uniform particle size by very-high-frequency plasma processing and deposit them on a poly-silicon electrode structure having a very small inter-electrode separation of 26–70 nm. Current-voltage (I–V) characteristics show Coulomb blockade and Coulomb staircase at 77 K. For very narrow electrode separation, Coulomb staircase appears in I-V characteristics even at room temperature.

52 citations


Book
15 Jan 1997
TL;DR: In this article, the physics, technology and device applications of semiconductor structures with ultrathin layers where the electronic properties are governed by the quantum-mechanical laws are discussed.
Abstract: This invaluable book is devoted to the physics, technology and device applications of semiconductor structures with ultrathin layers where the electronic properties are governed by the quantum-mechanical laws. Such structures called quantum wells or structures with the two-dimensional electron gas, have become one of the most actively investigated objects in modern solid state physics. Electronic properties of quantum wells differ dramatically from those of bulk semiconductors, which allows one to observe new types of physical phenomena, such as the quantum Hall effect and many other so-far-unknown kinetic and optical effects. This, in turn, offers wide opportunities for creating semiconductor devices based on new principles, and it has give birth to the new branch of electronics called nanoelectronics.

42 citations


Proceedings ArticleDOI
06 Jan 1997
TL;DR: In this paper, metal silicide source/drain MOSFETs may provide a simple route to terabit integrated circuits with /spl sim/25 nm gate length and /pl sim/100 nm overall device size.
Abstract: Metal silicide source/drain MOSFETs may provide a simple route to terabit integrated circuits with /spl sim/25 nm gate length and /spl sim/100 nm overall device size Potential advantages of this approach are outlined here along with recent progress

35 citations


Book ChapterDOI
TL;DR: Nanofabrication for electronics as mentioned in this paper describes the process of making minute artifacts in a material for electronic device applications and basic physics studies and emphasizes the processes of pattern generation by which designed structures for devices are fabricated in a semiconductor substrate.
Abstract: Publisher Summary This chapter discusses the nanofabrication for electronics. Within the broad classification of nanotechnology one of the most important topics is nanoelectronics. It is primarily the relentless quest to reduce the size of integrated circuit elements that has been the driving force toward the development of nanotechnology. Nanotechnology in microelectronics describes the process of making minute artifacts in a material for electronic device applications and basic physics studies. It emphasizes the processes of pattern generation by which designed structures for devices are fabricated in a semiconductor substrate. Nanotechnology is particularly important because it enables device miniaturization, which not only results in dramatic reductions in the unit cost per function but also leads to improved performance. As device dimensions decrease, the intrinsic switching time decreases and there is a reduction in power consumption per device in the circuit, leading to more devices per chip and greater circuit functionality. Nanometer-scale fabrication with the potential for industrial applications was first demonstrated using electron-beam lithography (EBL) in the 1970s. Irradiation-sensitive film patterned by electrons, ions, or X-ray radiation, are generally used in plannar process. The purpose of resist exposure is to use the pattern in the resist as a mask for producing structures in the substrate material. After the exposure, the pattern generated in the resist has to be transferred to underlying materials to make functional devices. There are many high-resolution pattern transfer techniques and they can be either additive (liftoff and plating) or subtractive (dry etching or wet chemical etching). Structures less than 10 nm have been transferred to solid substrates, with both additive and subtractive methods.

10 citations


Journal ArticleDOI
TL;DR: In this paper, a miniaturized " untethered flying observer " as a robotic free-flying vehicle supplied with MEMS/nano-to-micro payload and hosted on a much larger spaceship from which it would detach for short exploration missions is discussed.

3 citations


Proceedings ArticleDOI
22 Sep 1997
TL;DR: In this paper, the authors employ a comprehensive RF analysis technique based on transient ensemble Monte Carlo simulations to study and compare the high frequency potential of strained Si channel MODFETs and MOSFET, correctly accounting for realistic device geometries and parasitics.
Abstract: We employ a comprehensive RF analysis technique based on transient ensemble Monte Carlo simulations to study and compare the high frequency potential of strained Si channel MODFETs and MOSFETs correctly accounting for realistic device geometries and parasitics. Both devices show well pronounced overshoot effects. The MOSFET channel is more closely confined by the self aligned source and drain contacts, resulting in a shorter effective channel length and better device performance. The cut-off frequency fT is robust in the presence of realistic device contact and gate resistances, unlike the maximum frequency of oscillation fmax, which is strongly effected by the device parasitics.

3 citations


Journal ArticleDOI
TL;DR: In this paper, a spacer-cladded GaAs/AlAs multiple-quantum-well resonant tunneling structures, stabilized by a microstrip resonator system, is shown to provide proper circuit conditions at high frequencies and can be effectively used in millimeter and submillimeter wavelength range nanoelectronics.

3 citations


Proceedings ArticleDOI
M. Van Rossum1
22 Sep 1997
TL;DR: In this article, the authors discuss the contribution of nanotechnology to the evolution of MOS processing, as well as the role that silicon technology could play in the projected development of nanoelectronic.
Abstract: Silicon technology and nanoelectronics are two important components which will shape the future of the IC industry. This paper discusses their mutual interaction, i.e. the contribution that nanotechnology may o er to the evolution of MOS processing, as well as the role that silicon technology could play in the projected development of nanoelectronic

2 citations


Book
01 Apr 1997
TL;DR: In this article, the authors propose a quantum computing paradigm appropriate for nanoelectronics, including single electron devices and circuits, quantum interference devices, neuromorphic and other unconventional architectures employing above devices.
Abstract: Single electron devices and circuits quantum interference devices and circuits neuromorphic and other unconventional architectures employing above devices quantum computing dissipationless computing mesoscopic superconducting devices and circuits architecture issues nanofabrication issues self assembly of networks interconnects/molecular wires novel computing paradigms appropriate for nanoelectronics.

01 Jun 1997
TL;DR: In this paper, the potential energy function in a quantum dot is modeled, a nanostructure in which electrons are quantum-mechanically confined in all three dimensions and which represents the inevitable result of continued downscaling of semiconductor devices.
Abstract: : Much of the progress in solid-state microelectronics has come from the continued reduction in size of the transistors that make up integrated circuits (ICs), having dropped by a factor of 10 in the last decade to where minimum device geometries have reached approximately 350 nanometers in mass production. Continued improvements in ICs will require a device technology that can be scaled down to the sub-100 nanometer size regime. There, the quantum mechanical nature of the electron becomes strongly evident, and new design tools are required for a nano-electronic semiconductor technology. The combined scaling and speed advantages of these new devices could portend orders of magnitude increases in the functional performance of future-generation ICs. Quantum device performance is extremely sensitive to small variations in design parameters. Accurate theoretical modeling is therefore required to guide the technology development. Conventional device design tools are based on classical physics, and do not incorporate quantum effects. New design tools are required to explicitly account for the quantum effects that control charge transport at the nanometer scale. To further understand and develop nanoscale device technology, this thesis will model the potential energy function in a quantum dot, a nanostructure in which electrons are quantum-mechanically confined in all three dimensions and which represents the inevitable result of continued downscaling of semiconductor devices.

Proceedings ArticleDOI
06 Jan 1997
TL;DR: In this article, the current prospects for Si-based heterojunctions including SiGeC, CaF/sub 2, CeO/sub2, SiO/Sub 2, SiS, ZnS, and SiS are discussed.
Abstract: It is widely recognized that the holy grail for nanoelectronics is a technology that is compatible with standard silicon. We review the current prospects for the development of such a technology. We will discuss the current prospects for Si based heterojunctions including SiGeC, CaF/sub 2/, CeO/sub 2/, SiO/sub 2/ and ZnS to name just a few. Further, we review the status of one device structures, the tunnel switched diode, which can currently be deployed in a number of applications.