Showing papers on "Nanoelectronics published in 2012"

Optical nano-imaging of gate-tunable graphene plasmons

Abstract: The ability to manipulate optical fields and the energy flow of light is central to modern information and communication technologies, as well as quantum information processing schemes However, because photons do not possess charge, a way of controlling them efficiently by electrical means has so far proved elusive A promising way to achieve electric control of light could be through plasmon polaritons—coupled excitations of photons and charge carriers—in graphene In this two-dimensional sheet of carbon atoms, it is expected that plasmon polaritons and their associated optical fields can readily be tuned electrically by varying the graphene carrier density Although evidence of optical graphene plasmon resonances has recently been obtained spectroscopically, no experiments so far have directly resolved propagating plasmons in real space Here we launch and detect propagating optical plasmons in tapered graphene nanostructures using near-field scattering microscopy with infrared excitation light We provide real-space images of plasmon fields, and find that the extracted plasmon wavelength is very short—more than 40 times smaller than the wavelength of illumination We exploit this strong optical field confinement to turn a graphene nanostructure into a tunable resonant plasmonic cavity with extremely small mode volume The cavity resonance is controlled in situ by gating the graphene, and in particular, complete switching on and off of the plasmon modes is demonstrated, thus paving the way towards graphene-based optical transistors This successful alliance between nanoelectronics and nano-optics enables the development of active subwavelength-scale optics and a plethora of nano-optoelectronic devices and functionalities, such as tunable metamaterials, nanoscale optical processing, and strongly enhanced light–matter interactions for quantum devices and biosensing applications

Two‐Dimensional Dielectric Nanosheets: Novel Nanoelectronics From Nanocrystal Building Blocks

Abstract: Two-dimensional (2D) nanosheets, which possess atomic or molecular thickness and infinite planar lengths, are regarded as the thinnest functional nanomaterials. The recent development of methods for manipulating graphene (carbon nanosheet) has provided new possibilities and applications for 2D systems; many amazing functionalities such as high electron mobility and quantum Hall effects have been discovered. However, graphene is a conductor, and electronic technology also requires insulators, which are essential for many devices such as memories, capacitors, and gate dielectrics. Along with graphene, inorganic nanosheets have thus increasingly attracted fundamental research interest because they have the potential to be used as dielectric alternatives in next-generation nanoelectronics. Here, we review the progress made in the properties of dielectric nanosheets, highlighting emerging functionalities in electronic applications. We also present a perspective on the advantages offered by this class of materials for future nanoelectronics.

Breakdown of High-Performance Monolayer MoS2 Transistors

Abstract: Two-dimensional (2D) materials such as monolayer molybdenum disulfide (MoS(2)) are extremely interesting for integration in nanoelectronic devices where they represent the ultimate limit of miniaturization in the vertical direction. Thanks to the presence of a band gap and subnanometer thickness, monolayer MoS(2) can be used for the fabrication of transistors exhibiting extremely high on/off ratios and very low power dissipation. Here, we report on the development of 2D MoS(2) transistors with improved performance due to enhanced electrostatic control. Our devices show currents in the 100 μA/μm range and transconductance exceeding 20 μS/μm as well as current saturation. We also record electrical breakdown of our devices and find that MoS(2) can support very high current densities, exceeding the current-carrying capacity of copper by a factor of 50. Our results push the performance limit of MoS(2) and open the way to their use in low-power and low-cost analog and radio frequency circuits.

Fabrication of graphene nanomesh by using an anodic aluminum oxide membrane as a template.

Abstract: Graphene, a one-atom-thick two-dimensional carbon sheet, has been extensively studied owing to its broad applications in nanoelectronics, [ 1 , 2 ] nanocomposites, [ 3 , 4 ] chemical sensors and biosensors, [ 5–10 ] solar cells, [ 11–13 ] and electrical and optical devices. [ 14–16 ] However, the application of graphene in fi eldeffect transistors (FETs) is limited because of its semi-metallic behavior with zero bandgap. [ 17 , 18 ] Cutting graphene sheets into nanoribbons led to bandgap opening, with current ON/OFF ratio large enough for transistor operation. [ 19–23 ] Unfortunately, FET devices based on the individual nanoribbons exhibited low driving current and conductance. [ 22 ]

Vacuum nanoelectronics: Back to the future?—Gate insulated nanoscale vacuum channel transistor

Abstract: A gate-insulated vacuum channel transistor was fabricated using standard silicon semiconductor processing. Advantages of the vacuum tube and transistor are combined here by nanofabrication. A photoresist ashing technique enabled the nanogap separation of the emitter and the collector, thus allowing operation at less than 10 V. A cut-off frequency fT of 0.46 THz has been obtained. The nanoscale vacuum tubes can provide high frequency/power output while satisfying the metrics of lightness, cost, lifetime, and stability at harsh conditions, and the operation voltage can be decreased comparable to the modern semiconductor devices.

Lateral Graphene–hBCN Heterostructures as a Platform for Fully Two-Dimensional Transistors

Abstract: We propose that lateral heterostructures of single-atomic-layer graphene and hexagonal boron-carbon-nitrogen (hBCN) domains, can represent a powerful platform for the fabrication and the technological exploration of real two-dimensional field-effect transistors. Indeed, hBCN domains have an energy bandgap between 1 and 5 eV, and are lattice-matched with graphene; therefore they can be used in the channel of a FET to effectively inhibit charge transport when the transistor needs to be switched off. We show through ab initio and atomistic simulations that a FET with a graphene-hBCN-graphene heterostructure in the channel can exceed the requirements of the International Technology Roadmap for Semiconductors for logic transistors at the 10 and 7 nm technology nodes. Considering the main figures of merit for digital electronics, a FET with gate length of 7 nm at a supply voltage of 0.6 V exhibits I(on)/I(off) ratio larger than 10(4), intrinsic delay time of about 0.1 ps, and a power-delay-product close to 0.1 nJ/m. More complex graphene-hBCN heterostructures can allow the realization of different multifunctional devices, translating on a truly two-dimensional structure some of the device principles proposed during the first wave of nanoelectronics based on III-V heterostructures, as for example the resonant tunneling FET.

Fundamental Performance Limits of Carbon Nanotube Thin-Film Transistors Achieved Using Hybrid Molecular Dielectrics

Abstract: In the past decade, semiconducting carbon nanotube thin films have been recognized as contending materials for wide-ranging applications in electronics, energy, and sensing. In particular, improvements in large-area flexible electronics have been achieved through independent advances in postgrowth processing to resolve metallic versus semiconducting carbon nanotube heterogeneity, in improved gate dielectrics, and in self-assembly processes. Moreover, controlled tuning of specific device components has afforded fundamental probes of the trade-offs between materials properties and device performance metrics. Nevertheless, carbon nanotube transistor performance suitable for real-world applications awaits understanding-based progress in the integration of independently pioneered device components. We achieve this here by integrating high-purity semiconducting carbon nanotube films with a custom-designed hybrid inorganic–organic gate dielectric. This synergistic combination of materials circumvents conventiona...

Graphene: A Rising Star on the Horizon of Materials Science

Abstract: Graphene, a one-atom thick planar sheet of sp2 bonded carbon atoms packed in a honeycomb lattice, is considered to be the mother of all graphitic materials like fullerenes, carbon nanotubes, and graphite. Graphene has created tremendous interest to both physicists and chemists due to its various fascinating properties, both observed and predicted with possible potential applications in nanoelectronics, supercapacitors, solar cells, batteries, flexible displays, hydrogen storage, and sensors. In this paper, a brief overview on various aspects of graphene such as synthesis, functionalization, self-assembly, and some of its amazing properties along with its various applications ranging from sensors to energy storage devices had been illustrated.

Growth and optical properties of axial hybrid III–V/silicon nanowires

Abstract: Hybrid silicon nanowires with an integrated light-emitting segment can significantly advance nanoelectronics and nanophotonics. They would combine transport and optical characteristics in a nanoscale device, which can operate in the fundamental single-electron and single-photon regime. III-V materials, such as direct bandgap gallium arsenide, are excellent candidates for such optical segments. However, interfacing them with silicon during crystal growth is a major challenge, because of the lattice mismatch, different expansion coefficients and the formation of antiphase boundaries. Here we demonstrate a silicon nanowire with an integrated gallium-arsenide segment. We precisely control the catalyst composition and surface chemistry to obtain dislocation-free interfaces. The integration of gallium arsenide of high optical quality with silicon is enabled by short gallium phosphide buffers. We anticipate that such hybrid silicon/III-V nanowires open practical routes for quantum information devices, where for instance electronic and photonic quantum bits are manipulated in a III-V segment and stored in a silicon section.

Ultra-sensitive thermal conductance measurement of one-dimensional nanostructures enhanced by differential bridge.

Abstract: Thermal conductivity of one-dimensional nanostructures, such as nanowires, nanotubes, and polymer chains, is of significant interest for understanding nanoscale thermal transport phenomena as well as for practical applications in nanoelectronics, energy conversion, and thermal management. Various techniques have been developed during the past decade for measuring this fundamental quantity at the individual nanostructure level. However, the sensitivity of these techniques is generally limited to 1 × 10−9 W/K, which is inadequate for small diameter nanostructures that potentially possess thermal conductance ranging between 10−11 and 10−10 W/K. In this paper, we demonstrate an experimental technique which is capable of measuring thermal conductance of ∼10−11 W/K. The improved sensitivity is achieved by using an on-chip Wheatstone bridge circuit that overcomes several instrumentation issues. It provides a more effective method of characterizing the thermal properties of smaller and less conductive one-dimensi...

High-performance photodetectors for visible and near-infrared lights based on individual WS2 nanotubes

Abstract: We propose that a photodetector based on nanotubes formed from layered structure may have a faster response than nanowires or nanobelts. The layered compound tungsten disulfide (WS2) can absorb visible and near-infrared lights. We fabricated photodetectors based on individual WS2 nanotubes. The photodetectors exhibited a remarkable response to excitation with 633 and 785 nm light. The nanotube-based photodetectors exhibited short rise and decay times of a few hundred μs, high on/off ratio, and high spectral responsivity and external quantum efficiency. Our results imply that WS2 nanotubes are prospective candidates for high-performance nanoscale optoelectronic devices.

Selective synthesis and device applications of semiconducting single-walled carbon nanotubes using isopropyl alcohol as feedstock.

Abstract: The development of guided chemical vapor deposition (CVD) growth of single-walled carbon nanotubes provides a great platform for wafer-scale integration of aligned nanotubes into circuits and functional electronic systems. However, the coexistence of metallic and semiconducting nanotubes is still a major obstacle for the development of carbon-nanotube-based nanoelectronics. To address this problem, we have developed a method to obtain predominantly semiconducting nanotubes from direct CVD growth. By using isopropyl alcohol (IPA) as the carbon feedstock, a semiconducting nanotube purity of above 90% is achieved, which is unambiguously confirmed by both electrical and micro-Raman measurements. Mass spectrometric study was performed to elucidate the underlying chemical mechanism. Furthermore, high performance thin-film transistors with an on/off ratio above 104 and mobility up to 116 cm2/(V·s) have been achieved using the IPA-synthesized nanotube networks grown on silicon substrate. The method reported in th...

Electrochemical metallization cells—blending nanoionics into nanoelectronics?

Abstract: A range of material systems exist in which nanoscale ionic transport and redox reactions provide the essential mechanisms for memristive switching. One class relies on mobile cations, which are easily created by electrochemical oxidation of the corresponding electrode metal, transported in the insulating layer, and reduced at the inert counterelectrode. These devices are termed electrochemical metallization (ECM) memories, also called conductive bridge random access memories. The memristive characteristics of the ECM cells provide opportunities for circuit design and computational concepts that go beyond those in traditional complementary metal oxide semiconductor (CMOS) technology. Passive memory arrays open up paths toward ultradense and 3D stackable memory and logic gate arrays. Furthermore, the multivalued conductance characteristics allow for potential exploitation of the cells as synapses in neuromorphic circuits in future energy efficient high-performance computer architectures. Despite exciting results obtained in recent years, many challenges have to be met before these physical effects can be turned into competitive industrial technology. Here, we briefly review the basic working principle, the different possible and potential material combinations, and the fundamental electrochemical processes in ECM cells and their implications for device operations. The prospects of ECM-based resistive random access memory as an emerging memory technology are also reviewed in terms of switching speed and scalability.

Spintronics with graphene

Abstract: Because of its fascinating electronic properties, graphene is expected to produce breakthroughs in many areas of nanoelectronics. For spintronics, its key advantage is the expected long spin lifetime, combined with its large electron velocity. In this article, we review recent theoretical and experimental results showing that graphene could be the long-awaited platform for spintronics. A critical parameter for both characterization and devices is the resistance of the contact between the electrodes and the graphene, which must be large enough to prevent quenching of the induced spin polarization but small enough to allow for the detection of this polarization. Spin diffusion lengths in the 100- μ m range, much longer than those in conventional metals and semiconductors, have been observed. This could be a unique advantage for several concepts of spintronic devices, particularly for the implementation of complex architectures or logic circuits in which information is coded by pure spin currents.

Supercurrent and multiple Andreev reflections in an InSb nanowire Josephson junction

Abstract: Epitaxially grown, high quality semiconductor InSb nanowires are emerging material systems for the development of high performance nanoelectronics and quantum information processing and communication devices and for the studies of new physical phenomena in solid state systems. Here, we report on measurements of a superconductor-normal conductor-superconductor junction device fabricated from an InSb nanowire with aluminum-based superconducting contacts. The measurements show a proximity-induced supercurrent flowing through the InSb nanowire segment with a critical current tunable by a gate in the current bias configuration and multiple Andreev reflection characteristics in the voltage bias configuration. The temperature dependence and the magnetic field dependence of the critical current and the multiple Andreev reflection characteristics of the junction are also studied. Furthermore, we extract the excess current from the measurements and study its temperature and magnetic field dependences. The successful observation of the superconductivity in the InSb nanowire-based Josephson junction device indicates that InSb nanowires provide an excellent material system for creating and observing novel physical phenomena such as Majorana fermions in solid-state systems.

Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis

Abstract: Design of hybrid circuits and systems based on CMOS and nano-device requires rethinking of fundamental circuit analysis to aid design exploration. Conventional circuit analysis with modified nodal analysis (MNA) cannot consider new nano-devices such as memristor together with the traditional CMOS devices. This paper has introduced a new MNA method with magnetic flux (Φ) as new state variable. New SPICE-like circuit simulator is thereby developed for the design of hybrid CMOS and memristor circuits. A number of CMOS and memristor-based designs are explored, such as oscillator, chaotic circuit, programmable logic, analog-learning circuit, and crossbar memory, where their functionality, performance, reliability and power can be efficiently verified by the newly developed simulator. Specifically, one new 3-D-crossbar architecture with diode-added memristor is also proposed to improve integration density and to avoid sneak path during read-write operation.

Monolithic Growth of Ultrathin Ge Nanowires on Si(001)

Abstract: Self-assembled Ge wires with a height of only 3 unit cells and a length of up to 2 micrometers were grown on Si(001) by means of a catalyst-free method based on molecular beam epitaxy. The wires grow horizontally along either the [100] or the [010] direction. On atomically flat surfaces, they exhibit a highly uniform, triangular cross section. A simple thermodynamic model accounts for the existence of a preferential base width for longitudinal expansion, in quantitative agreement with the experimental findings. Despite the absence of intentional doping, the first transistor-type devices made from single wires show low-resistive electrical contacts and single-hole transport at sub-Kelvin temperatures. In view of their exceptionally small and self-defined cross section, these Ge wires hold promise for the realization of hole systems with exotic properties and provide a new development route for silicon-based nanoelectronics.

Performance Comparisons of III–V and Strained-Si in Planar FETs and Nonplanar FinFETs at Ultrashort Gate Length (12 nm)

Abstract: The exponential miniaturization of Si complementary metal-oxide-semiconductor technology has been a key to the electronics revolution. However, the downscaling of the gate length becomes the biggest challenge to maintain higher speed, lower power, and better electrostatic integrity for each following generation. Both industry and academia have been studying new device architectures and materials to address this challenge. In preparation for the 12-nm technology node, this paper assesses the performance of the In0.75Ga0.25As of III-V semiconductor compounds and strained-Si channel nanoscale transistors with identical dimensions. The impact of the channel material property and the device architecture on the ultimate performance of ballistic transistors is theoretically analyzed. Two-dimensional and three-dimensional real-space ballistic quantum transport models are employed with band structure nonparabolicity. The simulation results indicate three conclusions: 1) the In0.75Ga0.25As FETs do not outperform strained-Si FETs; 2) triple-gate Fin-shaped Field Effect Transistor (FinFET) surely represent the best architecture for sub-15-nm gate contacts, independently from the material choice; and 3) the simulations results further show that the overall device performance is very strongly influenced by the source and drain resistances.

Supercurrent and multiple Andreev reflections in an InSb nanowire Josephson junction

Abstract: Epitaxially grown, high quality semiconductor InSb nanowires are emerging material systems for the development of high performance nanoelectronics and quantum information processing and communication devices, and for the studies of new physical phenomena in solid state systems. Here, we report on measurements of a superconductor-normal conductor-superconductor junction device fabricated from an InSb nanowire with aluminum based superconducting contacts. The measurements show a proximity induced supercurrent flowing through the InSb nanowire segment, with a critical current tunable by a gate, in the current bias configuration and multiple Andreev reflection characteristics in the voltage bias configuration. The temperature dependence and the magnetic field dependence of the critical current and the multiple Andreev reflection characteristics of the junction are also studied. Furthermore, we extract the excess current from the measurements and study its temperature and magnetic field dependences. The successful observation of the superconductivity in the InSb nanowire based Josephson junction device indicates that InSb nanowires provide an excellent material system for creating and observing novel physical phenomena such as Majorana fermions in solid state systems.

Transport characteristics of multichannel transistors made from densely aligned sub-10 nm half-pitch graphene nanoribbons

Abstract: Densely aligned sub-10 nm graphene nanoribbons are desirable for scale-up applications in nanoelectronics. We implemented directed self-assembly of block-copolymers in combination with nanoimprint lithography to pattern sub-10 nm half-pitch nanoribbons over large areas. These graphene nanoribbons have the highest density and uniformity to date. Multichannel field-effect transistors were made from such nanoribbons, and the transport characteristics of transistors were studied. Our work indicates that a large ribbon-to-ribbon width variation in a multichannel FET can lead to nonsynchronized switching characters of multiple graphene channels and thus a poor ON/OFF current ratio. Through process optimization, we have created 8 nm half-pitch graphene nanoribbons with the minimal ribbon-to-ribbon width variation of ∼2.4 nm (3σ value). The corresponding transistors exhibit an ON/OFF current ratio >10, which is among the highest values ever reported for transistors consisting of densely arranged graphene nanoribbons. This work provides important insights for optimizing the uniformity and transport properties of lithographically patterned graphene nanostructures. In addition, the presented fabrication route could be further developed for the scalable nanomanufacturing of graphene-based nanoelectronic devices over large areas.

Embedded-gate graphene transistors for high-mobility detachable flexible nanoelectronics

Abstract: A high-mobility graphene field-effect transistor with embedded gate was fabricated on smooth spin-coated polyimide films. Electrostatic transport measurements reveal a maximum electron and hole mobility of 4930 cm2/V s and 1130 cm2/V s, respectively. Temperature dependent measurements indicate that carrier transport is not limited by intrinsic mechanisms but by charged impurities, surface roughness, and defects, suggesting that further increases in mobility are possible. The measured carrier mobilities are the highest reported for graphene transistors on polymeric substrates and hence enable high-speed devices for flexible electronics from graphene grown by size-scalable chemical vapor deposition.

Large-scale 2D electronics based on single-layer MoS 2 grown by chemical vapor deposition

Abstract: 2D nanoelectronics based on single-layer MoS 2 offers great advantages for both conventional and ubiquitous applications. This paper discusses the large-scale CVD growth of single-layer MoS 2 and fabrication of integrated devices and circuits for the first time. Fundamental building blocks of digital electronics, such as inverters and NAND gates, are fabricated to demonstrate its capability for logic applications.

Carbon nanotubes and nanosensors: vibration, buckling and ballistic impact

Abstract: The main properties that make carbon nanotubes (CNTs) a promising technology for many future applications are: extremely high strength, low mass density, linear elastic behavior, almost perfect geometrical structure, and nanometer scale structure. Also, CNTs can conduct electricity better than copper and transmit heat better than diamonds. Therefore, they are bound to find a wide, and possibly revolutionary use in all fields of engineering. The interest in CNTs and their potential use in a wide range of commercial applications; such as nanoelectronics, quantum wire interconnects, field emission devices, composites, chemical sensors, biosensors, detectors, etc.; have rapidly increased in the last two decades. However, the performance of any CNT-based nanostructure is dependent on the mechanical properties of constituent CNTs. Therefore, it is crucial to know the mechanical behavior of individual CNTs such as their vibration frequencies, buckling loads, and deformations under different loadings. This title is dedicated to the vibration, buckling and impact behavior of CNTs, along with theory for carbon nanosensors, like the Bubnov-Galerkin and the Petrov-Galerkin methods, the Bresse-Timoshenko and the Donnell shell theory.

Heat dissipation at a graphene–substrate interface

Abstract: The development of nanoelectronics faces severe challenges from Joule heating, leading to high power density and spatial localization of heat, which nucleates thermal hot spots, limits the maximum current density and potentially causes catastrophic materials failure. Weak interfacial coupling with the substrate is a major route for effective heat mitigation in low-dimensional materials such as graphene and carbon nanotubes. Here we investigate the molecular-scale physics of this process by performing molecular dynamics simulations, and find that significant heating in graphene supported by a silicon carbide substrate cannot be avoided when the areal power density exceeds PG = 0.5 GW m−2. A steady state will be established within 200 ps with a significant temperature difference built up across the interface, and the interfacial thermal conductivity κc increases at higher power densities from 10 to 50 MW m−2 K−1. These observations are explained by a two-resistor model, where strong phonon scattering at the interface may perturb the ballistic heat transport and lead to a diffusive mechanism. Nanoengineering the interfacial thermal coupling by intercalating guest atoms shows potential for designing thermally transparent but electronically insulating interfaces, which paves the way for simultaneously optimizing thermal management and charge carrier mobility in nanoelectronics.

Design and Evaluation of CNFET-Based Quaternary Circuits

Abstract: This paper presents novel high-performance and PVT tolerant quaternary logic circuits as well as efficient quaternary arithmetic circuits for nanoelectronics. These Carbon Nanotube FET (CNFET)-based circuits are compatible with the recent technologies and are designed based on the conventional CMOS architecture, while the previous quaternary designs used methods which are not suitable for nanoelectronics and have become obsolete. The proposed designs are robust and have large noise margins and high driving capability. The singular characteristics of CNFETs, such as the capability of having the desired threshold voltage by regulating the diameters of the nanotubes, make them very appropriate for voltage-mode multiple-threshold circuits design. The proposed circuits are examined, using Synopsys HSPICE with the standard 32 nm-CNFET technology in various situations and different supply voltages. Simulation results demonstrate the correct and high-performance operation of the proposed circuits even in the presence of process, voltage and temperature variations.

Carbon nanotube based ultra-low voltage integrated circuits: Scaling down to 0.4 V

Abstract: Carbon nanotube (CNT) based integrated circuits (ICs) including basic logic and arithmetic circuits were demonstrated working under a supply voltage low as 0.4 V, which is much lower than that used in conventional silicon ICs. The low limit of supply voltage of the CNT circuits is determined by the degraded noise margin originated from the process inducing threshold voltage fluctuation. The power dissipation of CNT ICs can be remarkably reduced by scaling down the supply voltage, and it is of crucial importance for the further developments of nanoelectronics ICs with higher integration density.

Two‐Dimensional Dielectric Nanosheets: Novel Nanoelectronics from Nanocrystal Building Blocks

Abstract: Two-dimensional (2D) nanosheets, which possess atomic or molecular thickness and infinite planar lengths, are regarded as the thinnest functional nanomaterials. The recent development of methods for manipulating graphene (carbon nanosheet) has provided new possibilities and applications for 2D systems; many amazing functionalities such as high electron mobility and quantum Hall effects have been discovered. However, graphene is a conductor, and electronic technology also requires insulators, which are essential for many devices such as memories, capacitors, and gate dielectrics. Along with graphene, inorganic nanosheets have thus increasingly attracted fundamental research interest because they have the potential to be used as dielectric alternatives in next-generation nanoelectronics. Here, we review the progress made in the properties of dielectric nanosheets, highlighting emerging functionalities in electronic applications. We also present a perspective on the advantages offered by this class of materials for future nanoelectronics.

The Piezotronic Effect of Zinc Oxide Nanowires Studied by In Situ TEM

Abstract: Piezotronics is a new field integrating piezoelectric effect into nanoelectronics, which has attracted much attention for the fundamental research and potential applications. In this paper, the piezotronic effect of zinc oxide (ZnO) nanowires, including the response of the electrical transport and photoconducting behaviors on the nanowire bending, has been investigated by in situ transmission electron microscopy (TEM), where the crystal structure of ZnO nanowires were simultaneously imaged. Serials of consecutively recorded current-voltage (IV) curves along with an increase of nanowire bending show the striking effect of bending on their electrical behavior. With increasing the nanowire bending, the photocurrent of ZnO nanowire under ultraviolet illumination (UV) drops dramatically and the photo response time becomes much shorter. In addition, the dynamic nanomechanics of ZnO nanowires were studied inside TEM. These phenomena could be attributed to the piezoelectric effect of ZnO nanowires, and they suggest the potential applications of ZnO nanowires on piezotronic devices.

Large-scale parallel arrays of silicon nanowires via block copolymer directed self-assembly.

Abstract: Extending the resolution and spatial proximity of lithographic patterning below critical dimensions of 20 nm remains a key challenge with very-large-scale integration, especially if the persistent scaling of silicon electronic devices is sustained. One approach, which relies upon the directed self-assembly of block copolymers by chemical-epitaxy, is capable of achieving high density 1 : 1 patterning with critical dimensions approaching 5 nm. Herein, we outline an integration-favourable strategy for fabricating high areal density arrays of aligned silicon nanowires by directed self-assembly of a PS-b-PMMA block copolymer nanopatterns with a L0 (pitch) of 42 nm, on chemically pre-patterned surfaces. Parallel arrays (5 × 106 wires per cm) of uni-directional and isolated silicon nanowires on insulator substrates with critical dimension ranging from 15 to 19 nm were fabricated by using precision plasma etch processes; with each stage monitored by electron microscopy. This step-by-step approach provides detailed information on interfacial oxide formation at the device silicon layer, the polystyrene profile during plasma etching, final critical dimension uniformity and line edge roughness variation nanowire during processing. The resulting silicon-nanowire array devices exhibit Schottky-type behaviour and a clear field-effect. The measured values for resistivity and specific contact resistance were ((2.6 ± 1.2) × 105 Ωcm) and ((240 ± 80) Ωcm2) respectively. These values are typical for intrinsic (un-doped) silicon when contacted by high work function metal albeit counterintuitive as the resistivity of the starting wafer (∼10 Ωcm) is 4 orders of magnitude lower. In essence, the nanowires are so small and consist of so few atoms, that statistically, at the original doping level each nanowire contains less than a single dopant atom and consequently exhibits the electrical behaviour of the un-doped host material. Moreover this indicates that the processing successfully avoided unintentional doping. Therefore our approach permits tuning of the device steps to contact the nanowires functionality through careful selection of the initial bulk starting material and/or by means of post processing steps e.g. thermal annealing of metal contacts to produce high performance devices. We envision that such a controllable process, combined with the precision patterning of the aligned block copolymer nanopatterns, could prolong the scaling of nanoelectronics and potentially enable the fabrication of dense, parallel arrays of multi-gate field effect transistors.

AlN nanowires: synthesis, physical properties, and nanoelectronics applications

Abstract: One-dimensional aluminum nitride (AlN) nanostructures, especially AlN nanowires, have been subjected to numerous investigations due to their unique physical properties and applications ranging from electronics to biomedical. This article reviews the synthesis of AlN nanowires and studies their physical properties and potential nanoelectronics applications. First, the different fabrication techniques used to synthesize AlN nanowires and their growth mechanisms are discussed. Next, the physical properties of AlN nanowires, such as the field emission, transport, photoluminescence, as well as the mechanical and piezoelectric properties are summarized. Finally, the potential applications of AlN nanowires in the field of nanoelectronics are described. Furthermore, this review summarizes the perspectives and outlooks on the future development of AlN nanowires.