Nanoelectronics

About: Nanoelectronics is a research topic. Over the lifetime, 3684 publications have been published within this topic receiving 156829 citations.

Carbon Nanotube Single-Electron Transistors at Room Temperature

Abstract: Room-temperature single-electron transistors are realized within individual metallic single-wall carbon nanotube molecules. The devices feature a short (down to ∼20 nanometers) nanotube section that is created by inducing local barriers into the tube with an atomic force microscope. Coulomb charging is observed at room temperature, with an addition energy of 120 millielectron volts, which substantially exceeds the thermal energy. At low temperatures, we resolve the quantum energy levels corresponding to the small island. We observe unconventional power-law dependencies in the measured transport properties for which we suggest a resonant tunneling Luttinger-liquid mechanism.

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

Hysteresis caused by water molecules in carbon nanotube field-effect transistors

Abstract: Carbon nanotube field-effect transistors commonly comprise nanotubes lying on SiO2 surfaces exposed to the ambient environment. It is shown here that the transistors exhibit hysteresis in their electrical characteristics because of charge trapping by water molecules around the nanotubes, including SiO2 surface-bound water proximal to the nanotubes. Hysteresis persists for the transistors in vacuum since the SiO2-bound water does not completely desorb in vacuum at room temperature, a known phenomenon in SiO2 surface chemistry. Heating under dry conditions significantly removes water and reduces hysteresis in the transistors. Nearly hysteresis-free transistors are obtainable by passivating the devices with polymers that hydrogen bond with silanol groups on SiO2 (e.g., with poly(methyl methacrylate) (PMMA)). However, nanotube humidity sensors could be explored with suitable water-sensitive coatings. The results may have implications to field-effect transistors made from other chemically derived materials.

Two‐Dimensional Dielectric Nanosheets: Novel Nanoelectronics From Nanocrystal Building Blocks

Abstract: Two-dimensional (2D) nanosheets, which possess atomic or molecular thickness and infinite planar lengths, are regarded as the thinnest functional nanomaterials. The recent development of methods for manipulating graphene (carbon nanosheet) has provided new possibilities and applications for 2D systems; many amazing functionalities such as high electron mobility and quantum Hall effects have been discovered. However, graphene is a conductor, and electronic technology also requires insulators, which are essential for many devices such as memories, capacitors, and gate dielectrics. Along with graphene, inorganic nanosheets have thus increasingly attracted fundamental research interest because they have the potential to be used as dielectric alternatives in next-generation nanoelectronics. Here, we review the progress made in the properties of dielectric nanosheets, highlighting emerging functionalities in electronic applications. We also present a perspective on the advantages offered by this class of materials for future nanoelectronics.

Ultrahigh-Density Nanowire Lattices and Circuits

Abstract: We describe a general method for producing ultrahigh-density arrays of aligned metal and semiconductor nanowires and nanowire circuits. The technique is based on translating thin film growth thickness control into planar wire arrays. Nanowires were fabricated with diameters and pitches (center-to-center distances) as small as 8 nanometers and 16 nanometers, respectively. The nanowires have high aspect ratios (up to 106), and the process can be carried out multiple times to produce simple circuits of crossed nanowires with a nanowire junction density in excess of 1011 per square centimeter. The nanowires can also be used in nanomechanical devices; a high-frequency nanomechanical resonator is demonstrated.