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Negative impedance converter

About: Negative impedance converter is a research topic. Over the lifetime, 5801 publications have been published within this topic receiving 87636 citations.


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Patent
29 Dec 1980
TL;DR: In this article, a switch-regulated push pull converter with voltage and current feedback loops was proposed to provide a highly regulated output voltage throughout a 100 percent load range with no minimum load requirement on the output voltage.
Abstract: A switching regulated push pull converter which includes voltage and current feedback loops to provide a highly regulated output voltage throughout a 100 percent load range. This circuit also provides a semi-regulated auxiliary output voltage which can be loaded beyond 100 percent of its load range with no minimum load requirement on the highly regulated output voltage. A direct current drive circuit for the push-pull power switches provides a transformerless proportional drive and means are provided to compensate for transformer asymmetry.

42 citations

Journal ArticleDOI
TL;DR: A new interleaved non-isolated bidirectional dc–dc converter with capability of zero voltage switching and high voltage gain is proposed and the accuracy performance of the proposed converter is verified through simulation results in EMTDC/PSCAD software.
Abstract: Summary In this paper, a new interleaved non-isolated bidirectional dc–dc converter with capability of zero voltage switching and high voltage gain is proposed In the proposed converter by using two coupled inductors and one capacitor, the voltage gain is extended Moreover, by using only an auxiliary circuit that includes an inductor and two capacitors, the zero voltage switching (ZVS) of two used switches in the first phase of converter can be achieved The ZVS operation of two used switches in the second phase is always obtained without using any extra auxiliary circuit This converter similar to other interleaved converters has low input current ripple and low current stress on switches In this paper, the proposed converter is analyzed in all operating modes, and also the voltage gain, required conditions for ZVS operation of switches, voltage and current stresses of all switches, and the value of input current ripple in both boost and buck operations are obtained Finally, the accuracy performance of the proposed converter is verified through simulation results in EMTDC/PSCAD software Copyright © 2017 John Wiley & Sons, Ltd

42 citations

Patent
03 May 1996
TL;DR: In this article, a negative voltage generator is connected to an FET amplifier in order to supply a gate bias voltage to each FET in the FET, so that an unwanted spurious component that may be contained in an output of the amplifier can be removed.
Abstract: An output voltage of a negative voltage generator contains a ripple because of a ripple occurring in a voltage produced by a charge pump circuit in the negative voltage generator. When the negative voltage is supplied to an FET amplifier, there arises a possibility that an unwanted spurious component occurs in an output of the FET amplifier. Since each of pair of circuits, that generate a negative voltage, are made mutually complementary, two charge pump circuits are used to cancel ripples. A ripple appearing in an output voltage can therefore be suppressed, and a negative voltage can eventually be supplied more stably. When the negative voltage generator is connected to, for example, an FET amplifier in order to supply a gate bias voltage to each FET in the FET amplifier, an unwanted spurious component that may be contained in an output of the FET amplifier can be removed.

41 citations

Journal ArticleDOI
TL;DR: In this article, a negative capacitance field effect transistor (FET) with sub-60 mV/decade subthreshold slope (SS) at different temperatures was experimentally demonstrated.
Abstract: A negative capacitance field-effect transistor (FET) with sub-60 mV/decade subthreshold slope (SS) at different temperatures (i.e. 14.8 mV/decade at 300 K, 15.7 mV/decade at 360 K and 24.3 mV/decade at 400 K) is experimentally demonstrated. A detailed account of the fabrication process of a negative capacitor is first introduced, followed by the measurement setup for the negative capacitance FET. The impact of temperature on negative capacitance FETs is investigated: (i) the equation for the internal voltage gain in the FET as a function of temperature is derived using Gibbs free energy and (ii) internal voltage against gate voltage (V Int against V G), internal voltage gain against gate voltage (dV Int/dV G against V G) and drain current against gate voltage (I D against V G) curves at different temperatures are measured. It is confirmed that internal voltage amplification can be achieved using the ferroelectric capacitor. However, the magnitude of the step-up voltage transformation is reduced, i.e. from 9.5 at 300 K to 2.6 at 400 K. Additionally, the SS is slightly increased (i.e. degrading from 14.8 mV/decade at 300 K to 24.3 mV/decade at 400 K) with increasing temperature; however, all SS values are better than the physical limits of SS as dictated by Boltzmann statistics.

41 citations

Journal ArticleDOI
TL;DR: A piezoelectric vibration power conditioning integrated circuit for energy autonomous sensor applications that is able to harness power from short-duration vibration and self starts up with a minimum 0.9-V input voltage.
Abstract: This brief presents a piezoelectric vibration power conditioning integrated circuit for energy autonomous sensor applications. The proposed circuit includes a negative voltage converter, a noninverting buck-boost converter working in discontinuous conduction mode (DCM), and a switching clock generator. Optimum load resistance is synthesized by the DCM buck-boost converter to achieve maximum power extraction, and system conduction loss is reduced by a novel arrangement of a current rectification diode within the buck-boost converter. This circuit is able to harness power from short-duration vibration and self starts up with a minimum 0.9-V input voltage. The proposed circuit has been implemented in a standard 0.18-μm CMOS process with 0.05-mm2 active area and achieved a maximum power conversion efficiency value of 54%.

41 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202330
2022104
2021120
2020131
2019134
2018155