Topic
Negative impedance converter
About: Negative impedance converter is a research topic. Over the lifetime, 5801 publications have been published within this topic receiving 87636 citations.
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TL;DR: In order to boost input impedance, various on- and off-chip parasitic capacitances are cancelled using an active shield and negative capacitance technique and a self-calibration scheme with active shield replica is proposed for positive feedback-basednegative capacitance.
Abstract: This paper presents circuit techniques for ultra-high input impedance analog front end (AFE). In order to boost input impedance, various on- and off-chip parasitic capacitances are cancelled using an active shield and negative capacitance technique. To maximize the cancellation, a self-calibration scheme with active shield replica is proposed for positive feedback-based negative capacitance, which settles at the boundary between stable and unstable states in calibration mode. A prototype IC fabricated in 0.18- $\mu \text{m}$ CMOS achieves an input impedance of 50 $\text{G}\Omega$ at 50 Hz, equivalent to 60-fF capacitance, while consuming 289 nW from 0.8-V supply. The proposed AFE is applied to heart-rate monitoring using 1-cm2 dry electrodes over clothes without any straps.
41 citations
Patent•
30 Aug 2001TL;DR: An unregulated inductorless direct current to direct current converter comprising a first voltage to current converter and a second voltage-to-current converter was proposed in this paper. But the converter was not considered in this paper.
Abstract: An unregulated inductorless direct current to direct current converter comprising a first voltage-to-current converter configured to convert a first voltage to a first current and a second voltage-to-current converter configured to convert a second voltage to a second current. A regulation circuit is coupled to the first and second voltage-to-current converters and configured to generate an output current proportional to the difference between the first and second currents. Also a variable frequency oscillator is coupled to the regulation circuit, the oscillator receiving as a control current the output current therefrom and outputting a clock signal having a frequency proportionate to the control current. The converter further comprises an output stage coupled to receive the clock signal and receiving an input voltage and outputting an output voltage, the output voltage and the input voltage having a ratio that is determined by the clock signal.
41 citations
Patent•
18 Oct 1991TL;DR: In this paper, the center frequency of the oscillation frequency is not a factor of control voltage V CN and is controlled only by an offset voltage V B 2, which is particularly significant in zone bit recording, which requires a wide frequency band.
Abstract: The voltage controlled oscillator in a phase-locked loop comprises a voltage-current converter (62) and a current frequency converter (34). The voltage-current converter (62) comprises a voltage differential-current converter (64), a current-current converter (66) and a current adder-subtracter (68). In the voltage differential-current converter (64), only the voltage fluctuation or difference ΔV CN with respect to one half a power supply voltage V DD /2, and not the absolute value of a control voltage V CN , undergoes current conversion as a control current I CN . Therefore, the center frequency of the oscillation frequency is not a factor of control voltage V CN and is controlled only by an offset voltage V B2 . Accordingly, the center frequency can be independently set by changing offset voltage VB 2 . This is particularly significant in zone bit recording, which requires a wide frequency band.
41 citations
Patent•
05 Apr 2013
TL;DR: In this paper, a converter is configured such that the converter operates at a first constant-gain resonant frequency during a normal operation condition wherein a voltage gain of the converter is essentially insensitive to an output load change and the converter operated at a minimum-gain damping frequency during an abnormal operation condition, where a voltage loss of a converter was approximately equal to zero.
Abstract: A converter comprises a bridge and a resonant tank coupled between the bridge and an isolation transformer. The converter is configured such that the converter operates at a first constant-gain resonant frequency during a normal operation condition wherein a voltage gain of the converter is essentially insensitive to an output load change and the converter operates at a minimum-gain damping frequency during an abnormal operation condition wherein a voltage gain of the converter is approximately equal to zero.
41 citations
Patent•
12 Apr 1991TL;DR: A reference voltage generating circuit in a CMOS integrated circuit comprises a first reference voltage circuit for generating a first-reference voltage by means of a MOS transistor having a first channel type, a second-and third-reference voltages for comparing the first and second reference voltages and feeding back the output corresponding to the result of the comparison.
Abstract: A reference voltage generating circuit in a CMOS semiconductor integrated circuit comprises a first reference voltage circuit for generating a first reference voltage by means of a MOS transistor having a first channel type, a second reference voltage circuit for generating a second reference voltage by means of a MOS transistor having a second channel type, and a comparator circuit for comparing the first and second reference voltages and feeding back the output corresponding to the result of the comparison, to the first reference voltage circuit to produce a third reference voltage.
41 citations