Negative impedance converter

About: Negative impedance converter is a research topic. Over the lifetime, 5801 publications have been published within this topic receiving 87636 citations.

Transient override circuit for a voltage regulator circuit

Abstract: A circuit for providing a regulated voltage to a load. The circuit includes a power converter coupled to the load and including at least one pulse-width modulated switching device, a control circuit for providing a pulse-width modulated control signal to the pulse-width modulated switching device of the power converter based on an output voltage of the power converter, and a transient override circuit responsive to a load voltage for biasing the pulse-width modulated switching device conductive during certain load voltage conditions.

β-Ga2O3 Nanomembrane Negative Capacitance Field-Effect Transistors with Steep Subthreshold Slope for Wide Band Gap Logic Applications.

Abstract: Steep-slope β-Ga2O3 nanomembrane negative capacitance field-effect transistors (NC-FETs) are demonstrated with ferroelectric hafnium zirconium oxide in the gate dielectric stack. Subthreshold slope less than 60 mV/dec at room temperature is obtained for both forward and reverse gate-voltage sweeps with a minimum value of 34.3 mV/dec at the reverse gate-voltage sweep and 53.1 mV/dec at the forward gate-voltage sweep at VDS = 0.5 V. Enhancement-mode operation with a threshold voltage of ∼0.4 V is achieved by tuning the thickness of the β-Ga2O3 membrane. Low hysteresis of less than 0.1 V is obtained. The steep-slope, low hysteresis, and enhancement-mode β-Ga2O3 NC-FETs are promising as an nFET candidate for future wide band gap complementary metal-oxide-semiconductor logic applications.

Negative voltage generator for flash EPROM design

Abstract: A circuit is provided for supplying a negative high voltage to an integrated circuit from a high positive voltage source Vpp. The negative voltage is applied to a plurality of FLASH electrically erasable programmable read only memory (EPROM) cells. The circuit includes an oscillator coupled to a voltage converter which provides a periodic signal. The periodic signal is coupled to a charge pump (3) including three P-channel type transistors to produced the negative voltage. The source and drain of the first transistor (41) is coupled to the periodic signal. The second transistor's (43) gate and drain is coupled to a reference ground potential with the source coupled to the first transistor's gate. Finally, the third transistor's drain and gate is coupled to the first transistor's gate and the third transistor's source outputs negative voltage to floating gates of the plurality of FLASH EPROM cells during an erase operation. Further, the negative voltage generated is relatively precise, so no regulation is required.

A Closed Form Analytical Model of Back-Gated 2-D Semiconductor Negative Capacitance Field Effect Transistors

Abstract: Steep slope ( $SS mV/dec at room temperature) negative capacitance (NC) FETs, based on the 2-D transition metal dichalcogenide semiconductor channel materials, may have a promising future in low-power electronics because of their high on-state current and very high on/off ratio. In this paper, we develop an analytically compact drain current model for long-channel back-gated 2-D NC-FETs by solving the classical drift-diffusion equations. The equations describe the transition from depletion to accumulation regimes of operation as a continuous function of gate/drain voltages. The continuity ensures time-efficient simulation of large systems. Several key features of the model are verified by comparing with the experimental data. Specifically, the negative drain induced barrier lowering effect and negative differential resistance effect predicted by the model are successfully observed in our experiments.