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NetFPGA

About: NetFPGA is a(n) research topic. Over the lifetime, 286 publication(s) have been published within this topic receiving 4768 citation(s).

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Papers
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Open accessProceedings Article
Minlan Yu1, Lavanya Jose2, Rui Miao1Institutions (2)
02 Apr 2013-
Abstract: Most network management tasks in software-defined networks (SDN) involve two stages: measurement and control. While many efforts have been focused on network control APIs for SDN, little attention goes into measurement. The key challenge of designing a new measurement API is to strike a careful balance between generality (supporting a wide variety of measurement tasks) and efficiency (enabling high link speed and low cost). We propose a software defined traffic measurement architecture OpenSketch, which separates the measurement data plane from the control plane. In the data plane, OpenSketch provides a simple three-stage pipeline (hashing, filtering, and counting), which can be implemented with commodity switch components and support many measurement tasks. In the control plane, OpenSketch provides a measurement library that automatically configures the pipeline and allocates resources for different measurement tasks. Our evaluations of real-world packet traces, our prototype on NetFPGA, and the implementation of five measurement tasks on top of OpenSketch, demonstrate that OpenSketch is general, efficient and easily programmable.

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Topics: Forwarding plane (56%), NetFPGA (55%), Pipeline (software) (53%) ...read more

527 Citations


Proceedings ArticleDOI: 10.1109/MSE.2007.69
John W. Lockwood1, Nick McKeown1, G. Watson1, Glen Gibb1  +4 moreInstitutions (1)
03 Jun 2007-
Abstract: The NetFPGA platform enables students and researchers to build high-performance networking systems in hardware. A new version of the NetFPGA platform has been developed and is available for use by the academic community. The NetFPGA 2.1 platform now has interfaces that can be parameterized, therefore enabling development of modular hardware designs with varied word sizes. It also includes more logic and faster memory than the previous platform. Field Programmable Gate Array (FPGA) logic is used to implement the core data processing functions while software running on embedded cores within the FPGA and/or programs running on an attached host computer implement only control functions. Reference designs and component libraries have been developed for the CS344 course at Stanford University. Open-source Verilog code is available for download from the project website.

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Topics: NetFPGA (80%), Open platform (59%), Field-programmable gate array (54%)

339 Citations


Proceedings ArticleDOI: 10.1145/1477942.1477944
Jad Naous1, David Erickson1, G. Adam Covington1, Guido Appenzeller1  +1 moreInstitutions (1)
06 Nov 2008-
Abstract: We describe the implementation of an OpenFlow Switch on the NetFPGA platform. OpenFlow is a way to deploy experimental or new protocols in networks that carry production traffic. An OpenFlow network consists of simple flow-based switches in the datapath, with a remote controller to manage several switches. In practice, OpenFlow is most often added as a feature to an existing Ethernet switch, IPv4 router or wireless access point. An OpenFlow-enabled device has an internal flow-table and a standardized interface to add and remove flow entries remotely.Our implementation of OpenFlow on the NetFPGA is one of several reference implementations we have implemented on different platforms. Our simple OpenFlow implementation is capable of running at line-rate and handling all the traffic that is going through the Stanford Electrical Engineering and Computer Science building. We compare our implementation's complexity to a basic IPv4 router implementation and a basic Ethernet learning switch implementation. We describe the OpenFlow deployment into the Stanford campus and the Internet2 backbone.

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Topics: OpenFlow (66%), NetFPGA (63%), Network switch (53%) ...read more

259 Citations


Journal ArticleDOI: 10.1109/MM.2014.61
25 Jul 2014-IEEE Micro
Abstract: The demand-led growth of datacenter networks has meant that many constituent technologies are beyond the research community's budget. NetFPGA SUME is an FPGA-based PCI Express board with I/O capabilities for 100 Gbps operation as a network interface card, multiport switch, firewall, or test and measurement environment. NetFPGA SUME provides an accessible development environment that both reuses existing codebases and enables new designs.

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Topics: NetFPGA (70%), PCI Express (50%)

201 Citations


Open accessProceedings ArticleDOI: 10.1145/3098822.3098825
Mark Handley1, Costin Raiciu2, Alexandru Agache2, Andrei Voinescu2  +3 moreInstitutions (3)
07 Aug 2017-
Abstract: Modern datacenter networks provide very high capacity via redundant Clos topologies and low switch latency, but transport protocols rarely deliver matching performance. We present NDP, a novel data-center transport architecture that achieves near-optimal completion times for short transfers and high flow throughput in a wide range of scenarios, including incast. NDP switch buffers are very shallow and when they fill the switches trim packets to headers and priority forward the headers. This gives receivers a full view of instantaneous demand from all senders, and is the basis for our novel, high-performance, multipath-aware transport protocol that can deal gracefully with massive incast events and prioritize traffic from different senders on RTT timescales. We implemented NDP in Linux hosts with DPDK, in a software switch, in a NetFPGA-based hardware switch, and in P4. We evaluate NDP's performance in our implementations and in large-scale simulations, simultaneously demonstrating support for very low-latency and high throughput.

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  • Figure 4: Delivery Latency with various traffic matrices.
    Figure 4: Delivery Latency with various traffic matrices.
  • Figure 16: Incast performance vs number of senders, 432-node FatTree.
    Figure 16: Incast performance vs number of senders, 432-node FatTree.
  • Figure 19: Collateral damage caused by 64-flow incast with DCTCP (top), DCQCN (center), NDP (bottom).
    Figure 19: Collateral damage caused by 64-flow incast with DCTCP (top), DCQCN (center), NDP (bottom).
  • Figure 18: Experimental setup to measure collateral damage of incast on nearby flows.
    Figure 18: Experimental setup to measure collateral damage of incast on nearby flows.
  • Figure 15: FCT for 90KB flows with random background load, 432 node FatTree.
    Figure 15: FCT for 90KB flows with random background load, 432 node FatTree.
  • + 13

Topics: Clos network (54%), NetFPGA (54%), Latency (engineering) (52%) ...read more

187 Citations


Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20217
202010
201917
201815
201717
201619

Top Attributes

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Topic's top 5 most impactful authors

Gianni Antichi

15 papers, 343 citations

Andrew W. Moore

11 papers, 323 citations

Jad Naous

9 papers, 1K citations

Noa Zilberman

9 papers, 380 citations

Olga Ormond

8 papers, 45 citations

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