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Neuromorphic engineering

About: Neuromorphic engineering is a research topic. Over the lifetime, 6617 publications have been published within this topic receiving 140486 citations. The topic is also known as: Neuromorphic computing.


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01 Jan 2009
TL;DR: In this paper, the authors extend the notion of memristive systems to capacitive and inductive elements, namely, capacitors and in- ductors whose properties depend on the state and history of the system.
Abstract: We extend the notion of memristive systems to capacitive and inductive elements, namely, capacitors and in- ductors whose properties depend on the state and history of the system. All these elements typically show pinched hyster- etic loops in the two constitutive variables that define them: current-voltage for the memristor, charge-voltage for the memcapacitor, and current-flux for the meminductor .W e argue that these devices are common at the nanoscale, where the dynamical properties of electrons and ions are likely to depend on the history of the system, at least within certain time scales. These elements and their combination in circuits open up new functionalities in electronics and are likely to find applications in neuromorphic devices to simulate learning, adaptive, and spontaneous behavior.

689 citations

Journal ArticleDOI
TL;DR: In this article, a mathematical definition of a memristive device provides the framework for understanding the physical processes involved in bipolar switching and also yields formulas that can be used to compute and predict important electrical and dynamical properties of the device.
Abstract: Memristive devices are promising components for nanoelectronics with applications in nonvolatile memory and storage, defect-tolerant circuitry, and neuromorphic computing. Bipolar resistive switches based on metal oxides such as TiO2 have been identified as memristive devices primarily based on the “pinched hysteresis loop” that is observed in their current-voltage (i-v) characteristics. Here we show that the mathematical definition of a memristive device provides the framework for understanding the physical processes involved in bipolar switching and also yields formulas that can be used to compute and predict important electrical and dynamical properties of the device. We applied an electrical characterization and state-evolution procedure in order to capture the switching dynamics of a device and correlate the response with models for the drift diffusion of ionized dopants (vacancies) in the oxide film. The analysis revealed a notable property of nonlinear memristors: the energy required to switch a me...

688 citations

Journal ArticleDOI
TL;DR: This paper quantifies tradeoffs faced in allocating bandwidth, granting access, and queuing, as well as throughput requirements, and concludes that an arbitered channel design is the best choice.
Abstract: This paper discusses connectivity between neuromorphic chips, which use the timing of fixed-height fixed-width pulses to encode information. Address-events (log/sub 2/(N)-bit packets that uniquely identify one of N neurons) are used to transmit these pulses in real time on a random-access time-multiplexed communication channel. Activity is assumed to consist of neuronal ensembles-spikes clustered in space and in time. This paper quantifies tradeoffs faced in allocating bandwidth, granting access, and queuing, as well as throughput requirements, and concludes that an arbitered channel design is the best choice. The arbitered channel is implemented with a formal design methodology for asynchronous digital VLSI CMOS systems, after introducing the reader to this top-down synthesis technique. Following the evolution of three generations of designs, it is shown how the overhead of arbitrating, and encoding and decoding, can be reduced in area (from N to /spl radic/N) by organizing neurons into rows and columns, and reduced in time (from log/sub 2/(N) to 2) by exploiting locality in the arbiter tree and in the row-column architecture, and clustered activity. Throughput is boosted by pipelining and by reading spikes in parallel. Simple techniques that reduce crosstalk in these mixed analog-digital systems are described.

674 citations

Journal ArticleDOI
TL;DR: It is shown that the proposed TEAM, ThrEshold Adaptive Memristor model is reasonably accurate and computationally efficient, and is more appropriate for circuit simulation than previously published models.
Abstract: Memristive devices are novel devices, which can be used in applications ranging from memory and logic to neuromorphic systems. A memristive device offers several advantages: nonvolatility, good scalability, effectively no leakage current, and compatibility with CMOS technology, both electrically and in terms of manufacturing. Several models for memristive devices have been developed and are discussed in this paper. Digital applications such as memory and logic require a model that is highly nonlinear, simple for calculations, and sufficiently accurate. In this paper, a new memristive device model is presented-TEAM, ThrEshold Adaptive Memristor model. This model is flexible and can be fit to any practical memristive device. Previously published models are compared in this paper to the proposed TEAM model. It is shown that the proposed model is reasonably accurate and computationally efficient, and is more appropriate for circuit simulation than previously published models.

666 citations

Journal ArticleDOI
TL;DR: An analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials is presented and shows bidirectional continuous weight modulation behaviour, consolidating the feasibility of analogue synaptic array and paving the way toward building an energy efficient and large-scale neuromorphic system.
Abstract: Conventional hardware platforms consume huge amount of energy for cognitive learning due to the data movement between the processor and the off-chip memory. Brain-inspired device technologies using analogue weight storage allow to complete cognitive tasks more efficiently. Here we present an analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials. The device shows bidirectional continuous weight modulation behaviour. Grey-scale face classification is experimentally demonstrated using an integrated 1024-cell array with parallel online training. The energy consumption within the analogue synapses for each iteration is 1,000 × (20 ×) lower compared to an implementation using Intel Xeon Phi processor with off-chip memory (with hypothetical on-chip digital resistive random access memory). The accuracy on test sets is close to the result using a central processing unit. These experimental results consolidate the feasibility of analogue synaptic array and pave the way toward building an energy efficient and large-scale neuromorphic system.

661 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20231,237
20222,362
20211,033
20201,130
2019893
2018692