About: Noise margin is a(n) research topic. Over the lifetime, 1167 publication(s) have been published within this topic receiving 15235 citation(s).
21 Sep 2003-Nature Materials
Abstract: There is ample evidence that organic field-effect transistors have reached a stage where they can be industrialized, analogous to standard metal oxide semiconductor (MOS) transistors. Monocrystalline silicon technology is largely based on complementary MOS (CMOS) structures that use both n-type and p-type transistor channels. This complementary technology has enabled the construction of digital circuits, which operate with a high robustness, low power dissipation and a good noise margin. For the design of efficient organic integrated circuits, there is an urgent need for complementary technology, where both n-type and p-type transistor operation is realized in a single layer, while maintaining the attractiveness of easy solution processing. We demonstrate, by using solution-processed field-effect transistors, that hole transport and electron transport are both generic properties of organic semiconductors. This ambipolar transport is observed in polymers based on interpenetrating networks as well as in narrow bandgap organic semiconductors. We combine the organic ambipolar transistors into functional CMOS-like inverters.
01 Jun 1983-IEEE Journal of Solid-state Circuits
TL;DR: A new dynamic CMOS technique which is fully racefree, yet has high logic flexibility, and logic inversion is provided, which means higher logic flexibility and less transistors for the same function.
Abstract: Describes a new dynamic CMOS technique which is fully racefree, yet has high logic flexibility. The circuits operate racefree from two clocks /spl phi/ and /spl phi/~ regardless of their overlap time. In contrast to the critical clock skew specification in the conventional CMOS pipelined circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C/SUP 2/MOS logic functions. Static CMOS functions can also be employed. Logic composition rules to mix dynamic CMOS, C/SUP 2/MOS, and conventional CMOS will be presented. Different from Domino technique, logic inversion is also provided. This means higher logic flexibility and less transistors for the same function. The effects of charge redistribution, noise margin, and leakage in the dynamic CMOS blocks are also analyzed. Experimental results show the feasibility of the principles discussed.
TL;DR: Experimental results show that the proposed method is very efficient as well as suitable for both DC and transient analysis of power grids, and reduced to a coarser structure, and the solution is mapped back to the original grid.
Abstract: Modern submicron very large scale integration designs include huge power grids that are required to distribute large amounts of current, at increasingly lower voltages. The resulting voltage drop on the grid reduces noise margin and increases gate delay, resulting in a serious performance impact. Checking the integrity of the supply voltage using traditional circuit simulation is not practical, for reasons of time and memory complexity. The authors propose a novel multigrid-like technique for the analysis of power grids. The grid is reduced to a coarser structure, and the solution is mapped back to the original grid. Experimental results show that the proposed method is very efficient as well as suitable for both de and transient analysis of power grids.
18 Jul 2006-Advanced Materials
Abstract: To date there are two demonstrated technologies for the fabrication of organic integrated circuits: the unipolar and the complementary technology. Unipolar architectures consist of p-channel organic field-effect transistors (OFETs), which are simple to fabricate since they require a single, high-workfunction metal (e.g., gold) and a single semiconductor material, which can be either evaporated or solution-processed.[1–4] Despite this great advantage, unipolar circuits have poor performance, exhibiting a narrow noise margin, low yield, and high power consumption. In order to improve their performance, more sophisticated architectures are usually employed. Although beneficial, such an approach increases circuit complexity by nearly 100 %. Complementary architectures, adopted from silicon microelectronics, solve this bottleneck by providing major advantages in circuit performance, including wide noise margin, robustness, and low power dissipation.[6,7] Unlike silicon technology, however, fabrication of discrete organic n- and p-channel transistors with lateral dimensions of a few micrometers, typically required for largescale integration, is still very challenging.
25 Apr 2005-IEEE Journal of Solid-state Circuits
Abstract: A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-/spl mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep transistor. SRAM virtual ground in standby is controlled by programmable bias transistors to achieve good voltage control with fine granularity under process skew. It also has a built-in programmable defect "screen" circuit for high volume manufacturing. The measurements showed that the SRAM leakage can be reduced by 3-5/spl times/ while maintaining the integrity of stored data.