Noise margin

About: Noise margin is a research topic. Over the lifetime, 1167 publications have been published within this topic receiving 15235 citations.

Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis

Abstract: In this paper, the DC behavior of subthreshold CMOS logic is analyzed in a closed form for the first time in the literature. To this aim, simplified large-signal and small-signal models of MOS transistors in subthreshold region are first developed. After replacing transistors with these equivalent models, analysis of the main DC parameters of CMOS logic gates is presented. In particular, the change in the DC characteristics shape due to operation at ultra-low voltages is analyzed in detail, evaluating analytically the degradation in the logic swing, the symmetry and the steepness of the transition region, as well as the change in the unity-gain points position. The resulting expressions permit to gain an insight into the basic dependence of DC behavior on design and device parameters. The noise margin is explicitly evaluated and modeled with a very simple expression. Interestingly, analysis shows that the noise margin deviates from the ideal half-swing value by an amount that linearly depends on the logarithm of the pn -ratio. Analysis permits to evaluate the minimum supply voltage that ensures correct operation of CMOS logic (i.e., positive noise margin). Previously proposed rule of thumbs to evaluate minimum voltage are also theoretically justified. Moreover, the impact of pMOS/nMOS unbalancing on DC characteristics is analyzed from a design perspective. Considerations on the impact of process/voltage/temperature variations are also introduced. Results are validated through extensive simulations in a 65-nm CMOS technology.

Efficient coupled noise estimation for on-chip interconnects

Abstract: Noise analysis and avoidance is an increasingly critical step in deep submicron design. Ever increasing requirements on performance have led to widespread use of dynamic logic circuit families and its other derivatives. These aggressive circuit families trade off noise margin for timing performance making them more susceptible to noise failure and increasing the need for noise analysis. Currently, noise analysis is performed either through circuit or timing simulation or through model order reduction. These techniques in use are still inefficient for analyzing massive amount of interconnect data found in present day integrated circuits. This paper presents efficient techniques for estimation of coupled noise in on-chip interconnects. This noise estimation metric is an upper bound for RC circuits, being similar in spirit to Elmore delay in timing analysis. Such an efficient noise metric is especially useful for noise criticality pruning and physical design based noise avoidance techniques.

Oxide Thin-Film Electronics using All-MXene Electrical Contacts.

Abstract: 2D MXenes have shown great promise in electrochemical and electromagnetic shielding applications. However, their potential use in electronic devices is significantly less explored. The unique combination of metallic conductivity and hydrophilic surface suggests that MXenes can also be promising in electronics and sensing applications. Here, it is shown that metallic Ti3 C2 MXene with work function of 4.60 eV can make good electrical contact with both zinc oxide (ZnO) and tin monoxide (SnO) semiconductors, with negligible band offsets. Consequently, both n-type ZnO and p-type SnO thin-film transistors (TFTs) have been fabricated entirely using large-area MXene (Ti3 C2 ) electrical contacts, including gate, source, and drain. The n- and p-type TFTs show balanced performance, including field-effect mobilities of 2.61 and 2.01 cm2 V-1 s-1 and switching ratios of 3.6 × 106 and 1.1 × 103 , respectively. Further, complementary metal oxide semiconductor (CMOS) inverters are demonstrated. The CMOS inverters show large voltage gain of 80 and excellent noise margin of 3.54 V, which is 70.8% of the ideal value. Moreover, the operation of CMOS inverters is shown to be very stable under a 100 Hz square waveform input. The current results suggest that MXene (Ti3 C2 ) can play an important role as contact material in nanoelectronics.

Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory

Abstract: With the appealing storage-density advantage, multilevel-per-cell (MLC) NAND Flash memory that stores more than 1 bit in each memory cell now largely dominates the global Flash memory market. However, due to the inherent smaller noise margin, the MLC NAND Flash memory is more subject to various device/circuit variability and noise, particularly as the industry is pushing the limit of technology scaling and a more aggressive use of MLC storage. Cell-to-cell interference has been well recognized as a major noise source responsible for raw-memory-storage reliability degradation. Leveraging the fact that cell-to-cell interference is a deterministic data-dependent process and can be mathematically described with a simple formula, we present two simple yet effective data-processing techniques that can well tolerate significant cell-to-cell interference at the system level. These two techniques essentially originate from two signal-processing techniques being widely used in digital communication systems to compensate communication-channel intersymbol interference. The effectiveness of these two techniques have been well demonstrated through computer simulations and analysis under an information theoretical framework, and the involved design tradeoffs are discussed in detail.

The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI

Abstract: Circuit requirements of scaled devices based on noise margin, parameter variation, parasitic resistance and drift velocity saturation lead to non-constant field scaling, which predict a maximum in performance as devices are scaled. This maximum occurs at a smaller length for p-channel than for n-channel for a given scaling rule, and causes the performance of the two to approach each other at L<0.3µm. The p-channel devices under these conditions are shown to be 100x less effected by hot carriers induced reliability problems than n-channel devices.