Topic
Noise margin
About: Noise margin is a research topic. Over the lifetime, 1167 publications have been published within this topic receiving 15235 citations.
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IBM1
TL;DR: The results show that the proposed robustness metrics can be used to estimate cell failure probabilities in an efficient and accurate manner.
Abstract: The impact of process variation on SRAM yield has become a serious concern in scaled technologies. In this paper, we propose a methodology to analyze the stability of an SRAM cell in the presence of random fluctuations in the device parameters. First, we develop a theoretical framework for characterizing the dc noise margin of a memory cell. The framework is based on the concept that an SRAM cell is on the verge of instability when the gain across the loop formed by the cross-coupled inverters in the cell is unity. The noise margin criteria developed in this manner can be used to verify a cell stability in the presence of arbitrary DC noise offsets at the two storage nodes in the cell. We also develop metrics for estimating the cell stability during read and write operations and verify these models by extensive Monte Carlo simulations in a 65-nm CMOS process. Our results show that the proposed robustness metrics can be used to estimate cell failure probabilities in an efficient and accurate manner.
137 citations
TL;DR: A novel P-P-N-based 10T SRAM cell, in which the latch is formed essentially by a cross-coupled P-p-N inverter pair, which is especially suitable for an SRAM macro with long bitlines - a property often desirable in order to achieve high density.
Abstract: SRAM has been under its renovation stage recently, aiming to withstand the ever-increasing process variation as well as to support ultra-low-power applications using even subthreshold supply voltages. We present in this paper a novel P-P-N-based 10T SRAM cell, in which the latch is formed essentially by a cross-coupled P-P-N inverter pair. This type of cell can operate at a voltage as low as 285 mV while still demonstrating high resilience to process variation. Its noise margin has been elevated in not only the hold state, but also the read operations. As compared to previous 10T SRAM cells, our cell excels in particular in two aspects: 1) ultra-low cell leakage, and 2) high immunity to the data-dependent bitline leakage. The second merit makes it especially suitable for an SRAM macro with long bitlines - a property often desirable in order to achieve high density. We have fabricated and validated its performance through a 16 Kb SRAM test chip using the UMC 90 nm process technology.
137 citations
TL;DR: In this article, it is argued that the most reliable and reasonable criterion is to maximize the product of the two noise margins, which is equivalent to maximizing the area of a rectangle embedded within the loop formed by the transfer curves of an inverter pair.
Abstract: Techniques for evaluating the noise margin for families of digital logic circuits are discussed and evaluated. It is shown that the technique of evaluating the -1 slope points on the inverter transfer function as used in most modern textbooks is not a valid and reliable approach to evaluating noise margin values. It is argued that the most reliable and reasonable criterion is to maximize the product of the two noise margins. This is equivalent to maximizing the area of a rectangle embedded within the loop formed by the transfer curves of an inverter pair. Most of the material presented can be found in the early literature on noise margin. However, because of the widespread use of the -1 slope criterion in modern textbooks, it is believed that a reexamination of basic approaches to noise margins is in order. >
131 citations
TL;DR: In this article, a low power SRAM using hierarchical bit line and local sense amplifiers (HBLSA-SRAM) was proposed to reduce both capacitance and write swing voltage of bit lines.
Abstract: This paper proposes a low power SRAM using hierarchical bit line and local sense amplifiers (HBLSA-SRAM). It reduces both capacitance and write swing voltage of bit lines by using the hierarchical bit line composed of a bit line and sub-bit lines with local sense amplifiers. The HBLSA-SRAM reduces the write power consumption in bit lines without noise margin degradation by applying a low swing signal to the high capacitive bit line and by applying a full swing signal to the low capacitive sub-bit line. The HBLSA-SRAM reduces the swing voltage of bit lines to V/sub DD//10 for both read and write. It saves 34% of the write power compared to the conventional SRAM. An SRAM chip with 8 K/spl times/32 bits is fabricated in a 0.25-/spl mu/m CMOS process. It consumes 26 mW read power and 28 mW write power at 200 MHz with 2.5 V.
131 citations
IBM1
TL;DR: In this paper, the effects of oxide soft breakdown (SBD) on the stability of CMOS 6T SRAM cells were investigated, and it was shown that gate-to-diffusion leakage currents of 20-50 /spl mu/A at the source can result in a 50% reduction of noise margin.
Abstract: We have investigated the effects of oxide soft breakdown (SBD) on the stability of CMOS 6T SRAM cells. Gate-to-diffusion leakage currents of 20-50 /spl mu/A at the n-FET source can result in a 50% reduction of noise margin. Breakdown at other locations in the cell may be less deleterious depending on n-FET width. This approach gives targets for tolerable values of leakage caused by gate-oxide breakdown.
128 citations