Topic
NQS
About: NQS is a research topic. Over the lifetime, 337 publications have been published within this topic receiving 4226 citations.
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TL;DR: In this article, the parasitic resistances, inductances, and intrinsic parameters of a small-signal FET equivalent circuit model including the non-quasi-static (NQS) charging time-constants associated with the gate and drain charges, respectively, were simultaneously extracted.
Abstract: We present analytic formulas for simultaneously extracting the parasitic resistances, inductances, and the intrinsic parameters of a small-signal FET equivalent circuit model including the non-quasi-static (NQS) charging time-constants associated with the gate and drain charges, respectively. For the NQS equivalent circuit topology considered, there exists a continuum of solutions for the circuit parameters, as a function of the source resistance, giving exactly the same frequency response fit. A multi-bias analysis is used to determine the final source resistance. Realistic results are obtained for power LDMOSFETs despite the very small value of the parasitics in these power RF devices.
9 citations
TL;DR: This paper presents an efficient formulation of a channel segmentation based approach to non-quasi-static modelling of the MOS transistor, in the context of a charge-based MOSFET model, where only the essential charge equations are evaluated for each channel segment.
Abstract: This paper presents an efficient formulation of a channel segmentation based approach to non-quasi-static modelling of the MOS transistor, in the context of a charge-based MOSFET model. In this minimal channel segmentation approach, only the essential charge equations are evaluated for each channel segment while other effects are handled at device level. As a result, simulation time is drastically reduced compared to a full channel segmentation approach. The model is validated versus measurement up to 10 GHz and passes relevant benchmark tests.
9 citations
01 Jan 2010
TL;DR: Two simple, sensitive and reproducible colorimetric methods have been developed for the estimation of Memantine in bulk and in pharmaceutical formulations and have been found to be precise andaccurate.
Abstract: Two simple, sensitive and reproducible colorimetric methods have been developed for the estimation of Memantine (MEM) in bulk and in pharmaceutical formulations. Method A is based on the reduction of Folin‐Ciocalteau (F.C) reagent by the drug and the reduced species posses a characteristic intense blue color (λmax 760 nm). Method B is based on the condensation of Memantine with 1,2‐Napthaquinone‐4‐sulphonate(NQS) in an alkaline medium to form an orange colored product (λmax 460 nm). Beers law is obeyed in the concentration range of 4‐12 µg/ml (Method A) and 7.5‐17.5 µg/ml (Method B) with good correlation coefficients of 0.997 and 0.999 respectively for Methods A and B respectively. These methods have been statistically evaluated and found to be precise and accurate.
9 citations
TL;DR: In this paper, the authors developed a basic concept for a nonquasi-static (NQS) metal-oxide-semiconductor field effect transistor (MOSFET) model for circuit simulation.
Abstract: We have developed a basic concept for a non-quasi-static (NQS) metal-oxide-semiconductor field-effect transistor (MOSFET) model for circuit simulation. The model is based on a carrier-response delay, and incorporates the time and position dependence of the carrier density along the channel. This is the exact origin of the NQS effect. By comparing model results with 2D device simulation results, solving the continuity equation explicitly, we found that the carrier-response delay consisted of a conductive delay and a charging delay. The developed model was successfully applied to test transient behavior of the drain current.
9 citations
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TL;DR: In this article, the level shift of the gate of the second and the first MOS transistors at the beginning of a level shift is turned off, so that the source-gate voltage of the third or the fourth MOS transistor becomes lower than its threshold voltage.
Abstract: An output circuit for a memory device has four MOS transistors. A first MOS transistor and a second MOS transistor comprise an output stage of the output circuit, and a control circuit controls the voltages of the gates of the first and the second MOS transistors. A third MOS transistor has its source connected to the gate of the second MOS transistor, and a fourth MOS transistor has its source connected to the gate of the first MOS transistor. When the data which are supplied to the control circuit are changed, the third or the fourth MOS transistor assists the level shift of the gate of the second and the first MOS transistor at the beginning of the level shift. By continuing the level shift, the third or the fourth MOS transistor is turned off. As a result, the source-gate voltage of the third or the fourth MOS transistor becomes lower than its threshold voltage, so that the switching noise or ground noise is reduced.
9 citations