Topic
Operational transconductance amplifier
About: Operational transconductance amplifier is a research topic. Over the lifetime, 14358 publications have been published within this topic receiving 158733 citations.
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TL;DR: In this paper, the operation of an MOS transistor as a lateral bipolar is described and analyzed qualitatively, and it yields a good bipolar transistor that is fully compatible with any bulk CMOS technology.
Abstract: Operation of an MOS transistor as a lateral bipolar is described and analyzed qualitatively. It yields a good bipolar transistor that is fully compatible with any bulk CMOS technology. Experimental results show that high /spl beta/-gain can be achieved and that matching and 1/f noise properties are much better than in MOS operation. Examples of experimental circuits in CMOS technology illustrate the major advantages that this device offers. A multiple current mirror achieves higher accuracy, especially at low currents. An operational transconductance amplifier has an equivalent input noise density below 0.1 /spl mu/V//spl radic/Hz for frequencies as low as 1 Hz and a total current of 10 /spl mu/A. A bandgap reference yields a voltage stable within 3 mV from -40 to +80/spl deg/C after digital adjustment at ambient temperature. Other possible applications are suggested.
257 citations
TL;DR: In this article, a highly sensitive CMOS chopper amplifier for low-frequency applications is described, which is realized with a second-order low-pass selective amplifier using a continuous-time filtering technique.
Abstract: A highly sensitive CMOS chopper amplifier for low-frequency applications is described. It is realized with a second-order low-pass selective amplifier using a continuous-time filtering technique. The circuit has been integrated in a 3-/spl mu/m p-well CMOS technology. The chopper amplifier DC grain is 38 dB with a 200-Hz bandwidth. The equivalent input noise is 63 nV//spl radic/Hz and free from 1/f noise. The input offset is below 5 /spl mu/V for a tuning error less than 1%. The amplifier consumes only 34 /spl mu/W.
248 citations
TL;DR: In this article, a multistage operational transconductance amplifier with a feedforward compensation scheme which does not use Miller capacitors is introduced, which uses the positive phase shift of left-halfplane (LHP) zeros caused by the feedforward path to cancel the negative phase shifting of poles to achieve a good phase margin.
Abstract: A multistage operational transconductance amplifier with a feedforward compensation scheme which does not use Miller capacitors is introduced. The compensation scheme uses the positive phase shift of left-half-plane (LHP) zeroes caused by the feedforward path to cancel the negative phase shift of poles to achieve a good phase margin. A two-stage path increases further the low frequency gain while a feedforward single-stage amplifier makes the circuit faster. The amplifier bandwidth is not compromised by the absence of the traditional pole-splitting effect of Miller compensation, resulting in a high-gain wideband amplifier. The capacitors of a capacitive amplifier using the proposed techniques can be varied more than a decade without significant settling time degradation. Experimental results for a prototype fabricated in an AMI 0.5-/spl mu/m CMOS process show DC gain of around 90 dB and a 1% settling time of 15 ns for a load capacitor of 12 pF. The power supply used is /spl plusmn/1.25 V.
235 citations
TL;DR: A monolithic SiGe BiCMOS envelope-tracking power amplifier is demonstrated for 802.11g OFDM applications at 2.4 GHz with off-chip digital predistortion employed to improve EVM performance.
Abstract: A monolithic SiGe BiCMOS envelope-tracking power amplifier (PA) is demonstrated for 802.11g OFDM applications at 2.4 GHz. The 4-mm2 die includes a high-efficiency high-precision envelope amplifier and a two-stage SiGe HBT PA for RF amplification. Off-chip digital predistortion is employed to improve EVM performance. The two-stage amplifier exhibits 12-dB gain, <5% EVM, 20-dBm OFDM output power, and an overall efficiency (including the envelope amplifier) of 28%.
232 citations
TL;DR: In this paper, the design of a low-voltage and low-power /spl Delta/spl Sigma/ analog-to-digital (A/D) converter is presented.
Abstract: The design of a low-voltage and low-power /spl Delta//spl Sigma/ analog-to-digital (A/D) converter is presented. A third-order single-loop /spl Delta//spl Sigma/ modulator topology is implemented with the differential modified switched op-amp technique. The modulator topology has been transformed as to accommodate half-delay integrators. Dedicated low-voltage circuit building blocks, such as a class AB operational transconductance amplifier, a common-mode feedback amplifier, and a comparator are treated, as well as low-voltage design techniques. The influence of very low supply voltage on power consumption is discussed. Measurement results of the 900-mV /spl Delta//spl Sigma/ A/D converter show a 77-dB dynamic range in a 16-kHz bandwidth and a 62-dB peak signal-to-noise ratio for a 40-/spl mu/W power consumption.
226 citations