Optical proximity correction

About: Optical proximity correction is a research topic. Over the lifetime, 3149 publications have been published within this topic receiving 34749 citations.

Fundamental principles of optical lithography : the science of microfabrication

Abstract: Preface. 1. Introduction to Semiconductor Lithography. 1.1 Basics of IC Fabrication. 1.2 Moore's Law and the Semiconductor Industry. 1.3 Lithography Processing. Problems. 2. Aerial Image Formation - The Basics. 2.1 Mathematical Description of Light. 2.2 Basic Imaging Theory. 2.3 Partial Coherence. 2.4 Some Imaging Examples. Problems. 3. Aerial Image Formation - The Details. 3.1 Aberrations. 3.2 Pupil Filters and Lens Apodization. 3.3 Flare. 3.4 Defocus. 3.5 Imaging with Scanners Versus Steppers. 3.6 Vector Nature of Light. 3.7 Immersion Lithography. 3.8 Image Quality. Problems. 4. Imaging in Resist: Standing Waves and Swing Curves. 4.1 Standing Waves. 4.2 Swing Curves. 4.3 Bottom Antirefl ection Coatings. 4.4 Top Antirefl ection Coatings. 4.5 Contrast Enhancement Layer. 4.6 Impact of the Phase of the Substrate Refl ectance. 4.7 Imaging in Resist. 4.8 Defi ning Intensity. Problems. 5. Conventional Resists: Exposure and Bake Chemistry. 5.1 Exposure. 5.2 Post-Apply Bake. 5.3 Post-exposure Bake Diffusion. 5.4 Detailed Bake Temperature Behavior. 5.5 Measuring the ABC Parameters. Problems. 6. Chemically Amplifi ed Resists: Exposure and Bake Chemistry. 6.1 Exposure Reaction. 6.2 Chemical Amplifi cation. 6.3 Measuring Chemically Amplifi ed Resist Parameters. 6.4 Stochastic Modeling of Resist Chemistry. Problems. 7. Photoresist Development. 7.1 Kinetics of Development. 7.2 The Development Contrast. 7.3 The Development Path. 7.4 Measuring Development Rates. Problems. 8. Lithographic Control in Semiconductor Manufacturing. 8.1 Defi ning Lithographic Quality. 8.2 Critical Dimension Control. 8.3 How to Characterize Critical Dimension Variations. 8.4 Overlay Control. 8.5 The Process Window. 8.6 H-V Bias. 8.7 Mask Error Enhancement Factor (MEEF). 8.8 Line-End Shortening. 8.9 Critical Shape and Edge Placement Errors. 8.10 Pattern Collapse. Problems. 9. Gradient-Based Lithographic Optimization: Using the Normalized Image Log-Slope. 9.1 Lithography as Information Transfer. 9.2 Aerial Image. 9.3 Image in Resist. 9.4 Exposure. 9.5 Post-exposure Bake. 9.6 Develop. 9.7 Resist Profi le Formation. 9.8 Line Edge Roughness. 9.9 Summary. Problems. 10. Resolution Enhancement Technologies. 10.1 Resolution. 10.2 Optical Proximity Correction (OPC). 10.3 Off-Axis Illumination (OAI). 10.4 Phase-Shifting Masks (PSM). 10.5 Natural Resolutions. Problems. Appendix A. Glossary of Microlithographic Terms. Appendix B. Curl, Divergence, Gradient, Laplacian. Appendix C. The Dirac Delta Function. Index.

Optical proximity correction method and apparatus

Abstract: Disclosed is a method for correcting a layout design using a design rule checker. The method includes providing a layout design file having the layout design that is to be corrected for optical proximity by the design rule checker. Providing a run set to the design rule checker. The run set includes a plurality of correction values that are used to correct a plurality of features of the layout design that have a selected space dimension. Identifying each of the plurality of features that have the selected space dimension. The method further includes correcting each of the plurality of features that have the selected space dimension with one correction value of the plurality of correction values of the run set. Preferably, the run set is generated from a correction table that has the plurality of correction values.

Performing optical proximity correction with the aid of design rule checkers

Abstract: A method is disclosed for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only. More specifically, the method includes the following steps: (a) analyzing an integrated circuit layout design with a design rule checker to locate features of the integrated circuit layout design meeting predefined criteria; and (b) performing optical proximity correction on the features meeting the criteria in order to generate a reticle design. The criteria employed by the design rule checker to select features include outside corners on patterns, inside corners on features, feature size, feature shape, and feature angles.

Fast optical and process proximity correction algorithms for integrated circuit manufacturing

Abstract: In this thesis, we first look at the Optical Proximity Correction (OPC) problem and define the goals, constraints, and techniques available. Then, a practical and general OPC framework is built up using concepts from linear systems, control theory, and computational geometry. A simulation-based, or model-based, OPC algorithm is developed which simulates the optics and processing steps of lithography for millions of locations. The key contributions to the OPC field made in this thesis work include: (1) formulation of OPC as a feedback control problem using an iterative solution, (2) an algorithm for edge movement during OPC with cost function criteria, (3) use of fast aerial image simulation for OPC, which truly enables full chip model-based OPC, and (4) the variable threshold resist (VTR) model for simplified prediction of CD based off aerial image. A major contribution of this thesis is the development of a fast aerial image simulator which is tailored to the problem of OPC. In OPC applications, it is best to compute intensity at sparse points. Therefore, our fast aerial image simulator is tailored to computing intensity at sparse points, rather than on a regular dense grid. The starting point for the fast simulation is an established decomposition of the Hopkins partially coherent imaging equations, originally proposed by Gamo (14). Within this thesis, the decomposition is called the Sum of Coherent Systems (SOCS) structure. The numerical implementation of this decomposition using Singular Value Decomposition (SVD) is described in detail. Another contribution of this thesis is the development of a variable threshold resist model (VTR). The model uses the aerial image peak intensity and image slope along a cutline to deduce the development point of the resist, and has two primary benefits: (1) it is fast, (2) it can be fit to empirical data. We combine the fast aerial image simulator and the VTR model in an iterative feedback loop to formulate OPC as a feedback control problem. (Abstract shortened by UMI.)

Data hierarchy layout correction and verification method and apparatus

Abstract: A method and apparatus for the correction of integrated circuit layouts for optical proximity effects which maintains the original true hierarchy of the original layout is provided. Also provided is a method and apparatus for the design rule checking of layouts which have been corrected for optical proximity effects. The OPC correction method comprises providing a hierarchically described integrated circuit layout as a first input (205), and a particular set of OPC correction criteria as a second input (260). The integrated circuit layout is then analyzed to identify features of the layout which meet the provided OPC correction criteria (210, 240). After the areas on the mask which need correction have been identified (310), optical proximity correction data (320) is generated in response to the particular set of correction criteria. Finally, a first program data is generated which stores the generated optical proximity correction data in a hierarchical structure (320) that corresponds to the hierarchical structure of the integrated circuit layout (310). As the output correction data is maintained in true hierarchical format, layouts which are OPC corrected according to this method are able to be processed through conventional design rule checkers with no altering of the data.