Showing papers on "Output impedance published in 1999"

Power transfer circuit for implanted devices

Abstract: An external power transfer circuit (12) couples ac power having a fixed frequency into an implantable electrical circuit (14), e.g., an implantable tissue stimulator, while automatically maintaining optimum power transfer conditions. Optimum power transfer conditions exist when there is an impedance match between the external and implanted circuits. The external transfer circuit includes a directional coupler (42) and an impedance matching circuit (44). The directional coupler senses the forward power being transferred to the implant device, as well as the reverse power being reflected form the implant device (as a result of an impedance mismatch). The impedance matching circuit includes at least one variable element controlled by a control signal. The sensed reverse power is used as a feedback signal to automatically adjust the variable element in the impedance matching circuit, and hence the output impedance of the external power transfer circuit, so that it matches the input impedance of the implant device, despite variations that occur in the input impedance of the implant device due to variations in implant distance and implant load.

SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters

Abstract: Although very high update rates are achieved in recent publications on high resolution D/A converters, the bottleneck in the design is to achieve a high spurious free output signal bandwidth. The influence of the dynamic output impedance on the chip performance has been analyzed and has been identified as an important limitation for the spurious free dynamic range (SFDR) of high resolution DAC's. Based on the presented analysis an optimized topology is proposed.

Individual load impedance specification for a stable DC distributed power system

Abstract: This paper continues the effort to define load impedance specification for a stable DC distributed power system. To improve the existing load impedance specification, an alternative forbidden region for Z/sub 0//Z/sub i/ is proposed, based on which individual impedance specification for each load is defined. Theoretical verification, accompanied with simulation results, shows that the proposed impedance specification is a sufficient condition for small signal system stability. Finally, conservativeness in load impedance specification is discussed.

Effect of voltage sags on adjustable-speed drives: a critical evaluation and an approach to improve performance

Abstract: In this paper, a critical evaluation of the effect of voltage sags on adjustable-speed drives (ASDs) is presented. In particular, the DC-link voltage variation under voltage sag and its dependence on source impedance, DC-link inductance and output load is computed. It is shown that, for larger source impedance, the DC-link voltage variation under a voltage sag is also large and increases the susceptibility of an ASD and may result in a nuisance trip. The results from the analysis are plotted in per-unit quantities and serve as a design guide to assess ASD performance for a variety of sags. In order to improve the performance of ASDs, this paper proposes an integrated boost converter approach. This approach provides ride-through to critical ASD load during voltage sags without any additional energy storage device. Upon detection of a voltage sag, the boost converter operates with suitable duty ratio and maintains the DC-link voltage within acceptable limits. This prevents nuisance tripping and facilitates continuous operation of critical ASD load at rated torque. The proposed integrated boost converter does not introduce any additional semiconductors in the series path of the power flow and is low in cost. A commercially available 480 V 22 kVA ASD is modified with the integrated boost converter approach, and details are discussed. Analysis, simulation, and experimental performance of the ride-through approach are presented.

Modeling of CMOS digital-to-analog converters for telecommunication

Abstract: This paper gives an overview of some of the effects caused by circuit mismatch and parasitics in binary weighted digital-to-analog converters (DACs), and, as a special case, a current-steering CMOS converter. Matlab is used as a behavior-level simulator. In telecommunications applications, the frequency-domain parameters are of the greatest importance. Therefore, the characterization of the device and its performance is determined by frequency parameters such as the signal-to-noise ratio, spurious-free dynamic range, multitone power ratio, etc. In this paper, we show how these frequency-domain parameters are affected when mismatch errors and finite output impedance are applied to a current-steering CMOS DAC. We discuss how static performance is affected when changing the size of the errors and fundamental circuit parameters. The impact of dynamic errors such as glitches, slewing, and bit skew is discussed. Measurement results from 14-bit DACs are also shown to illustrate the correlation with the modeling.

On-chip termination

Abstract: Integrated circuits include an impedance control circuit having at least one output terminal coupled to an on-chip reference termination device in order to control output impedance of the reference termination device such that it matches that of an external resistance. The impedance control circuit outputs are also coupled to the on-chip impedance-controlled termination devices which are coupled to each of the external transmission lines to be terminated. In this way, a single reference resistance allows many transmission lines to be properly terminated. The impedance-controlled termination devices are may be implemented as pairs of binary weighted p-channel and n-channel field effect transistors.

Internal impedance of conductors of rectangular cross section

Abstract: It is shown that the resistance and internal inductive reactance of a conductor of rectangular cross section are not equal when skin effect is well developed, i.e., when the cross-sectional dimensions are much larger than a skin depth, unlike the case of a conductor of circular cylindrical cross section. Hence, the high-frequency internal inductance cannot be determined from the resistance and must be computed separately. Also, the widely used time-domain representation of the internal impedance B/spl radic/s is not valid. Numerical results are given for conductors of various cross-sectional aspect ratios and dimensions.

Rechargeable hearing aid system

Abstract: A contactless rechargeable hearing aid system in which a rechargeable hearing aid may be optically or inductively recharged by an optical or an inductive recharger. The optically rechargeable hearing aid may have a dual purpose optical fiber that may act as a light conduit for the recharging light, and that may also act as a draw string for the hearing aid. The rechargeable hearing aid may use a high energy nickel metal-hydride rechargeable battery or a high energy, high voltage lithium based rechargeable battery, in conjunction with a DC to DC voltage regulating circuit for converting the rechargeable battery's declining DC output voltage to the fixed DC input voltage needed by the hearing aid's audio related circuitry. The DC to DC voltage regulating circuit may also help to present a supply impedance that matches the input impedance of the audio related circuitry in the hearing aid. The rechargeable battery may have an alternately folded cell stack, a spiral wound cell stack or an accordion folded cell stack, in order to provide, in a minimized volume, the large anode, cathode and electrolyte areas that may be needed to reduce the rechargeable battery's output impedance, in order to help reduce internal resistance losses during use of the battery.

Impedance specification and impedance improvement for DC distributed power system

Abstract: In a DC distributed power system, the interaction between individually designed power modules/subsystems may cause the instability of the whole system In the small-signal sense, these kinds of interactions can be predicted by checking impedance ratio Z/sub o//Z/sub i/ and can also be prevented by making impedance specification for power modules/subsystems Many efforts have been made in defining impedance specification and improving I/O impedance for converters and filters This paper summarizes work in these two areas

Shared-bus current sharing parallel connected current-mode DC to DC converters

Abstract: A power system consisting of parallel connected current-mode power converters combined with a voltage error signal on a shared-bus used in common for controlling all of the power stages for improved consistency, reliability, and performance in both transient and steady states. Near uniform current sharing is achievable without sacrificing the voltage regulation performance. The improved system offers faster settling time under step loads, consistent small signal characteristics and large signal responses regardless of mismatches of components values such as reference voltages, and reduced output impedance variations in magnitude and phase even during various modes of operation.

Dynamic performance of PWM DC-DC boost converter with input voltage feedforward control

Abstract: Small-signal characteristics are studied for a pulse-width modulated (PWM) boost converter with input voltage feedforward control. The characteristics are valid for the continuous conduction mode (CCM). A small-signal circuit model is used to derive the input-to-output voltage transfer function (audio-susceptibility), the input impedance, and the output impedance. A response of the output voltage to a step change in the input voltage is also computed. The measured Bode plots of the input-to-output voltage transfer function agreed with that predicted theoretically. It is shown that the feedforward control may reduce the magnitude of the input-to-output voltage transfer function by 40 dB. The input resistance of the converter with feedforward control is negative at low frequencies. The output impedance is not affected by feedforward control.

Transformer coupled stacked FET power amplifiers

Abstract: The development of high-power linear ultrahigh-frequency amplifiers is made difficult by the low impedance of the devices used in the output stage, which causes matching difficulties and high radio-frequency current levels. A stacked field-effect transistor (FET) configuration is shown to reduce these problems with its increased output impedance and lower current required for a given output power. A linear analysis of the stacked FET configuration is given. Two class A monolithic microwave integrated circuit amplifiers are developed and subjected to one- and two-tone tests to demonstrate the performance of the stacked FET as a power amplifier at 900 MHz.

Input filter interaction in three phase AC-DC converters

Abstract: It is well known that the addition of an input filter preceding a switched mode regulator poses a problem of performance degradation and potential instability due to its negative input impedance at low frequencies. Three phase converters are essentially multivariable systems. The objective of this paper is to analyze the problem of input filter interaction in three phase AC-DC converters from a multivariable perspective and to establish criteria that guarantee stability and satisfactory performance of the converter with an input filter. The dq average model of a three phase boost rectifier is used for the analysis. The minor loop, the stability of which has to be guaranteed is identified. A sufficient condition for stability, based on the singular values of the filter output impedance and converter input admittance matrices is derived. Simulation results are presented to illustrate the results.

Analysis and design of three-phase AC-to-DC converters with high power factor and near-optimum feedforward

Abstract: This paper presents a three-phase pulsewidth modulated AC-to-DC power converter with unity power factor and near-optimum dynamic regulation. A general mathematical model of the converter has been established to lead to a comprehensive analysis. The averaged small-signal technique is used to obtain the near-optimum feedforward compensator, thus resulting in the output impedance, and the audio susceptibility become zero, that is, the output voltage of the converter presented in this paper is independent of variations of the DC load current and the utility voltage. The proposed procedure of analysis is simple and effective, and it is also easy to implement. Finally, the theoretical formulations are verified both by simulated and experimental results in a 5 kW laboratory prototype system.

Modeling of the high-power-factor discontinuous boost rectifiers

Abstract: This paper presents a modeling approach to obtain a small-signal model for a single-switch single-phase and three-phase discontinuous boost high-power-factor rectifiers. Such converters present nonlinear characteristics, and an approximation of them is used to derive the models. The most important result obtained is that the small-signal output impedance is not equal to the load impedance. The analysis is validated by experimental results.

Sampled-data modeling and analysis of closed-loop PWM DC-DC converters

Abstract: General block diagram models are proposed for PWM DC-DC converters in continuous and discontinuous conduction modes with fixed switching frequency. Both current mode control and voltage mode control are addressed in these models. Based on these models, detailed nonlinear and linearized sampled-data dynamics are derived. Asymptotic orbital stability is analyzed. Audio-susceptibility and output impedance are derived. In this approach, discontinuous conduction mode and current mode control can be analyzed systematically without special effort.

Dynamic impedance compensation circuit and method

Abstract: An impedance compensation circuit and method for an input/output buffer provides dynamic impedance compensation by using programmable impedance arrays and a dynamically adjustable on-chip load. Accordingly, among other advantages, only a single off-chip or external calibrated impedance resistor is used and only a single test pad is necessary.

Interaction between EMI filter and power factor preregulators with average current control: analysis and design considerations

Abstract: The effects of a nonnegligible source impedance, due to the presence of an input EMI filter, on the stability of power factor preregulators (PFPs) with average current control are analyzed by using a state-space averaged model. Different from previous approaches, it allows us to derive a simple expression for the loop gain in terms of the converter current loop gain. The overall system stability was studied for boost, Cuk, and SEPIC PPP topologies. Based on this model, a simple modification of the standard current control loop is proposed which increases the converter robustness against instabilities. Comparison between model forecasts and experimental measurements was carried out using two prototypes, one based on the boost topology and the other based on the SEPIC topology, both rated at 600 W. Finally, the model accuracy was investigated with measurements at different current loop bandwidths.

Novel MMIC source-impedance tuners for on-wafer microwave noise-parameter measurements

Abstract: Novel monolithic-microwave integrated-circuit source-impedance tuners for use in on-wafer noise-parameter measurement systems are reported, which can be incorporated into a wafer probe tip. These eliminate the effect of cable and probe losses on the magnitude of a reflection coefficient that can be presented to the input of an on-wafer test device, thus enabling higher magnitudes to be synthesized than for conventional tuners, and with the potential of increasing noise-parameter measurement accuracy.

Impedance adapting system

Abstract: PROBLEM TO BE SOLVED: To supply an impedance adapting system realizing precise impedance adaptation based on the actual impedance of a transmission line. SOLUTION: A CPU 2 sequentially turns on the switch elements 7a to 7n of a resistor selection controller 3. The resistors R1 to Rn of a resistor array block 5 are connected in series to a damping resistor Rt in series between the output terminal A of a transmission side signal source 11 and the output terminal B of the resistor array block 5 as sequential adjustment resistors. An adjusting resistor by which the voltage Vb of the output terminal B becomes 1/2 of the voltage Va of the output terminal A is selected at every connection. When Vb=Va/2 is not satisfied, a resistor value where Vb/Va is most close to 1/2 is selected. The characteristic impedance of the transmission line 12 connected to the output terminal B and the sum of the output impedance of the transmission side signal source 11, the damping resistor Rt and the adjusting resistor are approximately impedance-adapted and the reflection noise of the signal of the transmission line 12 can be prevented or can remarkably be reduced.

Multiple output converter having a low power dissipation cross regulation compensation circuit

Abstract: A compensation circuit for a DC—DC converter having a low voltage output line and a plurality of high voltage output lines applied to a plurality of loads includes an adjustable impedance source connected to the low voltage output line. The impedance source generates a feedback control signal to the DC—DC converter used to control the transformer duty cycle. A sensing circuit is connected to the plurality of high voltage output lines for generating a control signal which represents variations in the output voltages of the high voltage output lines. The control signal is applied to the impedance source to thereby regulate the feedback control signal which in turn provides regulation for the high voltage output lines.

Current-mode universal filter using unity gain cells

Abstract: A new universal current-mode biquad filter circuit suitable for integrated circuit implementation is presented. The circuit uses three two-output current followers, two voltage buffers, two grounded capacitors and four virtually grounded resistors to realise all the standard biquad filters without changing the circuit topology. The proposed circuit can be used to achieve independent control of the natural frequency and the bandwidth. Also, the filter exhibits a low input impedance, high output impedance as well as low active and passive sensitivities. Simulation results using CMOS unity gain cells are also presented.

Variable impedance output driver circuit using analog biases to match driver output impedance to load input impedance

Abstract: A programmable variable impedance output driver circuit uses analog biases to match driver output impedance to load input impedance. A current mirror is used to obtain a measurement of an external resistance value for matching the impedance of a driven load. The mirrored current generates the voltage "NBIAS" when passed through the resistively connected NFET. Similarly, the current is again mirrored and passed through a resistively connected PFET resulting in the voltage "PBIAS". The analog bias voltages, NBIAS and PBIAS are used to vary the impedance of complementary FETs in an impedance matched driver for a high degree of dI/dt control. The driver provides a high degree of flexibility because its turn-on and turn-off characteristics do not depend on a combination of digital control signals connected directly to the driving FETs as in the prior art. Instead, the PBIAS and NBIAS signals provide analog controls which may be applied to single transistors whose impedance changes as PBIAS and NBIAS increase or decrease.

Interconnect coupling noise in CMOS VLSI circuits

Abstract: AbstmctInterconnect between a CMOS driver and receiver can be modeled as a lossy transmission line in high speed CMOS VLSI circuits as transition times become comparable to or lass than the time of flight delay of the signal through the low resistivity interconnect. In this paper, closed form expressions for the coupling noise between adjacent interconnect are presented to estimate the coupling noise voltage on a quiet line. These expressions are based on an assumption that the interconnections are loosely coupled, where the effect of the coupling noise on the waveform of the active line is small and can be neglected. It is demonstrated that the output impedance of the CMOS driver should preferably be comparable to the interconnect impedance in order to reduce the propagation delay of the CMOS driver stage.

Constant impedance, low noise CMOS buffer

Abstract: A low noise CMOS buffer has been provided which includes the advantages of having a stable load impedance and a linear-ramped current waveform at the output. The buffer adds waveform shaping transistors to delay the turn on of the driver circuits, and to shape the voltage and current waveforms of the drivers. These critically placed waveform shaping transistors accomplish the function of turning off the drivers in a manner to encourage an opposite polarity linear ramp current waveform at the buffer output. A method of using waveform shaping transistors to form a stable output impedance and a linear-ramped current waveform at the output of a buffer is also provided.

Implantable stimulator with battery status measurement

Abstract: There is provided an implantable device system such as a battery-powered pacemaker system, with an improved capability of measuring battery internal impedance, thereby providing the means to determine anticipated device End of Life. Within one pacemaker cycle following a sensed beat or a delivered stimulus, and before delivery of a next stimulus, three battery measurements are taken at equally spaced time intervals. Due to the RC nature of the battery internal impedance, the first two battery voltage measurements can be used to calculate what the voltage would be at the third time, assuming no change in current load. At the third time, a predetermined incremental current load is added, and the battery voltage at the time of the added current load is measured. The voltage differential between the calculated battery voltage and the measured battery voltage at the third time, together with the predetermined incremental current load, is used to calculate the battery impedance.

Frequency-dependent interface capacitance of Al–Al2O3–Al tunnel junctions

Abstract: Four-terminal ac impedance measurements have been used to characterize Al–Al2O3–Al tunnel-junction capacitors over the frequency range of 10 Hz–100 kHz. The insulating barriers are thin enough to assure that the response can be modeled by a frequency-dependent interface capacitance in parallel with a frequency-independent tunnel junction resistor R0. The data reveal no sign of loss peaks down to 10 Hz and the impedance curves for a single junction, annealed to give different tunnel-junction resistance, collapse onto a single curve when R0 is used as a scaling parameter. The loss mechanism is ascribed to interface traps and is found to give an unusual asymptotic phase angle response when the real and imaginary parts of the complex capacitance are plotted against each other.

Dual band tuning

Abstract: A dual band RF tuning circuit ( 1 ) has a first impedance element ( 4 ) and a second impedance element ( 5 ) between an RF input port ( 2 ) and an RF output port ( 3 ), tuning being provided by the impedance elements ( 4, 5 ) to a first RF signal, and a switching transistor ( 9 ) connected to the second impedance element ( 5 ) to open circuit the second impedance element ( 5 ) for tuning to a second RF signal by the first impedance element ( 4 ) alone.

Peak crosstalk noise estimation in CMOS VLSI circuits

Abstract: Interconnect between a CMOS driver and receiver can be modeled as a lossy transmission line in high speed CMOS VLSI circuits as transition times become comparable to or less than the time of flight delay of the signal through the interconnect. In this paper, a linear resistor model is used to approximate the CMOS driver stage, and the CMOS receiver is modeled as a capacitor. A closed form expression for the coupling noise between adjacent interconnect is presented to estimate the coupling noise voltage on a quiet line based on the assumption that these interconnections are loosely coupled, where the effect of the coupling noise on the waveform of the active line is small and can be neglected. It is demonstrated that the output impedance of the CMOS driver should be comparable to the interconnect impedance in order to reduce the propagation delay of the CMOS driver stage.

Impedance detection apparatus and method of physical variable

Abstract: An apparatus for detecting an impedance variable in response to a sensed physical amount of a sensor is provided which comprises an impedance-frequency conversion unit and a counter. The impedance-frequency conversion unit converts the sensor impedance to an oscillation signal a frequency of which corresponds to the sensor impedance. The impedance-frequency conversion unit comprises an impedance-voltage converter for providing a voltage corresponding to the sensor impedance, and a Wien bridge oscillator including an element an impedance of which varies in response to the voltage from the impedance-voltage converter, for generating the oscillation signal. The Wien bridge oscillator is capable of generating a square wave signal as the oscillation signal. The counter counts the number of waves (or wave number) of the oscillation signal in a predetermined time period to output a count value which can be handled as a digital signal.