Showing papers on "Output impedance published in 2004"

Wide-band CMOS low-noise amplifier exploiting thermal noise canceling

Abstract: Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative feedback can be used to break this tradeoff, however, at the price of potential instability. In contrast, this paper presents a feedforward noise-canceling technique, which allows for simultaneous noise and impedance matching, while canceling the noise and distortion contributions of the matching device. This allows for designing wide-band impedance-matching amplifiers with NF well below 3 dB, without suffering from instability issues. An amplifier realized in 0.25-/spl mu/m standard CMOS shows NF values below 2.4 dB over more than one decade of bandwidth (i.e., 150-2000 MHz) and below 2 dB over more than two octaves (i.e., 250-1100 MHz). Furthermore, the total voltage gain is 13.7 dB, the -3-dB bandwidth is from 2 MHz to 1.6 GHz, the IIP2 is +12 dBm, and the IIP3 is 0 dBm. The LNA drains 14 mA from a 2.5-V supply and the die area is 0.3/spl times/0.25 mm/sup 2/.

Impedance measurement for improved power quality-Part 1: the measurement technique

Abstract: This paper introduces an improved power system impedance measurement technique. The technique injects a short duration current spike into the supply, and derives the impedance from the measured current and voltage. The method is shown to work extremely well under most conditions, by experimental evaluation using a 45-kVA laboratory prototype. Degradation is observed when a voltage-source-type power-electronic load is connected directly to the measurement equipment. An alternative signal processing strategy, based upon the Prony method is proposed to improve the estimation under these conditions. This method also reduces the overall transient data capture time, thus allowing a faster, online calculation of the impedance.

Output impedance design of parallel-connected UPS inverters

Abstract: This paper deals with the design of the output impedance of UPS inverters with parallel-connection capability. The inner control loops are considered in the design of the controllers that makes possible the power sharing among the UPS modules. In these paralleled units, the power-sharing outer control loops are based on the P/Q droop method in order to avoid any communication among the modules. The power sharing accuracy is highly sensitive to the output impedance of the inverters, making necessary the tight adjustment of this impedance. Novel control loops are proposed to achieve stable output impedance value, and, therefore, proper power balance is guarantee when sharing both linear and nonlinear loads.

Measurement of noise source impedance of SMPS using a two probes approach

Abstract: A novel approach to determine common-mode (CM) and differential-mode (DM) noise source impedances of a low-power switched mode power supply (SMPS) has been developed using a two current probes approach. The proposed approach allows measurement of noise source impedance of a SMPS without interrupting its normal operation. With proper setup calibration, the proposed approach can derive an equivalent circuit model, consisting of resistive and reactive components, to represent the noise source impedance with reasonable accuracy. Once the equivalent circuit model of the noise source impedance is obtained through the measurement, the most effective filter configuration and suitable component values for the built-in power line electromagnetic interference (EMI) filter of the SMPS could be designed with ease.

Adaptive voltage position design for voltage regulators

Abstract: This paper proposes a general design guideline for the voltage regulator (VR) to achieve adaptive voltage position (AVP). All existing control methods are covered for different kinds of output filter capacitors. Based on the small-signal model analysis, the output impedance and system control bandwidth are discussed. Following the proposed design guidelines, simulation and experimental results demonstrate very good VR transient response.

Determination of the impedance matching domain of impedance matching networks

Abstract: This paper investigates the impedance boundary of impedance matching networks analytically, graphically representing the resultant impedance matching domains. A set of explicit equations is derived to allow the rapid development of the impedance boundary of such networks. The equations are analyzed thoroughly, such that the impact each component has upon the resultant domain may be obtained. These equations are then developed further to provide a design procedure enabling a matching network to be designed to achieve impedance matching in a specific impedance domain given the source impedance and operating frequency.

Diagnosis for expected life of emergency power apparatus

Abstract: This invention measures the exact value of impedance voltage(Vis) from AC actual waveform(VSM) which includes ripple noise voltage, and suggests the inventive circuits and softwares capable of acquiring the effective resistance of battery internal impedance and the operational algorithm of the diagnosis for the expected life of battery string. In accordance with a series of functional operations and the execution of the program in MPU, this diagnostic system can find the cause of aging progress in advance and settle by unmanned monitoring the healthiness of emergency power system always in real time at remote site.

Semiconductor integrated circuit device capable of controlling impedance

Abstract: A semiconductor integrated circuit device is connected to an external reference resistor, including an impedance control circuit for generating impedance control codes variable with impedances established by the external reference resistor. An input circuit receives an external signal through an input transfer line and forwards the external signal to an internal circuit. A termination circuit terminates the input transfer line in response to at least one of the impedance control code. An output circuit drives an output transfer line in accordance with an output signal. Impedance is variable with the control codes.

A 4–18-GHz reconfigurable RF MEMS matching network for power amplifier applications

Abstract: We have developed a novel reconfigurable matching network based on the loaded-line technique. The network is composed of N-switched capacitors (N = 4–8) with a capacitance ratio of 4–5:1 and is suitable for power amplifiers at 4–18 GHz, or as an impedance tuner for noise parameter and load-pull measurements at 10–28 GHz. The networks are very small, and offer better performance than double or triple stub matching networks. Extensive loss analysis indicates that the 8-element network has a loss of 0.5 dB at 4–12 GHz, and less than 1.5 dB at 18 GHz, even when matching a 10Ω output impedance to a 50Ω load. As expected, the 4-element matching network has about half the loss of the 8-element network, but with much less impedance coverage. Both networks were simulated and measured in high VSWR conditions and can handle at least 500 mW of RF power at 4–18 GHz. The application areas are in phased array antennas, reconfigurable power amplifiers, and wideband noise-parameter and load-pull measurement systems. © 2004 Wiley Periodicals, Inc. Int J RF and Microwave CAE 14: 356–372, 2004.

Review of narrowband impedance-matching limitations

Abstract: Many antennas can be characterized by their radiation Q (the ratio of reactance to radiation resistance). A classic problem is determining the maximum possible bandwidth, constrained by the maximum permissible reflection magnitude, and the number of tuned circuits in the impedance-matching circuit. This paper presents a review on theoretical limitations of narrowband impedance matching.

Impedance Matching Circuit for a Mobile Communication Device

Abstract: Position sensors (18) detect the position of a user's hand position on a mobile communication device (10). A controller (12) dynamically adjusts the source impedance of a transmitter (32) and/or receiver (34) in the mobile communication device (10) based on the user's hand position to compensate for variations in the load impedance caused by the user's hand position.

Fully integrated distributed power amplifier in CMOS technology, optimized for UWB transmitters

Abstract: A power amplifier (PA) using the distributed amplifier technique for the ultra wideband (UWB) standard is presented. The amplifier is fabricated in a standard 0.13 /spl mu/m CMOS technology and comes with on-chip biasing circuitry and a non-distributed input stage. Measurement results are given for a chip-on-board module to take any influence of product assembly into account. It achieves a transmission coefficient S/sub 21/ = 17 dB, a corner frequency of f/sub c/ = 8 GHz and a 1 dB compression point of A/sub 1dB/ = 3.5 dBm. The output impedance is matched to 50 /spl Omega/ so that external matching circuitry can be omitted. With these features, it is customized to be integrated with other building blocks to a fully integrated CMOS UWB transmitter product.

Plasma production device and method and rf driver circuit with adjustable duty cycle

Abstract: An RF driver circuit and an orthogonal antenna assembly/configuration, are disclosed as part of a method and system for generating high density plasma. The antenna assembly is an orthogonal antenna system that may be driven by any RF generator/circuitry with suitable impedance matching to present a low impedance. The disclosed RF driver circuit uses switching type amplifier elements and presents a low output impedance. The disclosed low-output impedance RF driver circuits eliminate the need for a matching circuit for interfacing with the inherent impedance variations associated with plasmas. Also disclosed is the choice for capacitance or an inductance value to provide tuning for the RF plasma source. There is also provided a method for rapidly switching the plasma between two or more power levels at a frequencies of about tens of Hz to as high as hundreds of KHz.

A 20-50 GHz reconfigurable matching network for power amplifier applications

Abstract: A reconfigurable matching network has been developed and it is based on loaded line techniques. It consists of 8 switched MEMS capacitors producing 256 (2/sup 8/) different impedances and is only 1/spl times/2.5 mm in size on a glass substrate. The network is ideally suited to match power amplifiers with 10-20 /spl Omega/ output impedance to 50-60 /spl Omega/ systems at 20-50 GHz. The estimated loss of the network is only 1-1.5 dB at 40 GHz while matching a 10-20 /spl Omega/ load to a 50 /spl Omega/ load. The reconfigurable network can also be used as an impedance tuner in noise parameter and load-pull measurements of active devices at 30-65 GHz.

Kink effect in short-channel polycrystalline silicon thin-film transistors

Abstract: Excess current, induced by impact ionization (kink effect) has been investigated in short-channel polysilicon thin-film transistors (TFTs). We have shown, both experimentally and by using two-dimensional (2-D) numerical simulations, that the output characteristics are substantially degraded by the kink effect as the channel length is reduced. In particular, we have shown that the excess current, triggered by the impact ionization and enhanced by the parasitic bipolar transistor action, scales nearly as L−2, thus making very difficult the downscaling of polysilicon TFTs. Such L dependence has been clarified through a detailed analysis of the current components obtained from 2-D numerical simulations. The analysis demonstrates that there are fundamental issues with the output characteristics, and it appears that the introduction of appropriate drain field relief structures will be necessary for the fabrication of short-channel polysilicon TFTs with high output impedance.

Output buffer with time varying source impedance for driving capacitively-terminated transmission lines

Abstract: An output buffer for driving a capacitively-terminated transmission line produces a waveform which comprises a first portion during which the waveform transitions from a voltage V1 to a voltage V2; a second portion during which it remains fixed at V2; a third portion during which it transitions to a voltage V3; and a fourth portion during which it remains fixed at V3. The waveform is created within a unit interval whenever successive data bits transition between logic states. The first and second portions are generated with circuitry arranged such that V2 is maximized by reducing the buffer's output impedance. The fourth portion is generated with circuitry which has a non-zero output impedance preferably equal to the transmission line's characteristic impedance, to absorb transitions reflected back to the source circuitry by the capacitive termination.

A reconfigurable 6-20 GHz RF MEMS impedance tuner

Abstract: A 6-20 GHz reconfigurable triple-stub impedance tuner has been developed. It is based on a 11-switched MEMS capacitor network producing 2/sup 11/ different impedances. The measured and simulated impedance coverage is the widest ever measured to-date from any RF MEMS tuner. This network is most suitable for noise parameters and load-pull measurements of transistors at 6-20 GHz.

Source-gated transistors in hydrogenated amorphous silicon

Abstract: Source-gated transistors form a new class of transistors in which the current is controlled entirely by the source. As such, they have properties that are fundamentally different from their nearest relative the field-effect transistor. Instead of using the field-effect to modulate the conductance of a channel it is used to change to electric field at a reverse biased source barrier thereby changing the source current. Saturation of the current occurs when the source is depleted of carriers by the reverse biased barrier. This feature contrasts markedly with saturation in a standard field-effect transistor that occurs when the drain end of the channel is depleted of charge. A model describing the characteristics of a source-gated transistor is outlined and compared with characteristics measured on transistors made using hydrogenated amorphous silicon. Good agreement is found between theory and experiment. It is shown that the saturation voltage of the SGT can be very much smaller than it is in a FET leading to lower voltage operation and power dissipation. Furthermore, the output impedance of the SGT can exceed that of an FET. Transistors covering a wide range of currents have been made by modifying a Schottky barrier source using ion implantation.

Identification of grid impedance for purposes of voltage feedback active filtering

Abstract: A voltage feedback active filter is vulnerable to unknown grid impedance. To overcome this problem we propose an identification method, which uses the control system of a frequency selective active filter to measure the grid impedance at selected frequencies. The usefulness of the method is experimentally demonstrated with a 19 kVA active rectifier with a voltage feedback active filtering function. The voltage feedback active filtering is performed in a case in which the active filter control is not stable before the impedance is identified with the method proposed. It is shown that the use of the measured grid impedance in the control system greatly enhances the dynamic stability of the system. Also, the grid impedance measurements are provided in two cases.

Self-tuning variable impedance circuit for impedance matching of power amplifiers

Abstract: A self-tuning variable impedance circuit provides improved performance. A variation in the power applied to the variable impedance circuit causes a corresponding change in the impedance of the circuit, resulting in improved performance. For example, the variable impedance circuit may be a matching circuit that “follows” the output power of a power amplifier, thereby increasing the power efficiency of the power amplifier.

Modeling and measurements of parasitic parameters for integrated power electronics modules

Abstract: In this paper, the parasitic inductance and capacitance of integrated power electronics modules (IPEMs) were modeled using Maxwell Q3D extractor. The IPEMs were then measured using impedance analyzer. A set of impedance curves was obtained under different measurement conditions, such as different DC bias voltages. Together with the device model, the Maxwell Q3D extractor results were simulated in Saber to get the impedance curves, which were compared with impedance measurement results. The comparison showed good agreement between simulation and measurement results.

Output impedance performance for parallel operation of UPS inverters using wireless and average current-sharing controllers

Abstract: This paper encompasses the study of the output impedance impact of parallel-connected UPS inverters. Two novel nonlinear control strategies are proposed. The first one is based on the single-wire current-sharing scheme, which is well known in parallel dc-to-dc converter systems. The second one is a wireless control technique derived from the droop method. The output impedance of the inverters is investigated in both cases. Results of two parallel-connected 1-kVA UPS inverters show the feasibility of the proposed approach. Finally, the two proposed controllers are compared between them and those with the existing solutions.

Hybrid type working machine

Abstract: The output of an engine driven generator G is directly supplied to a motor 7 for travel without the intermediary of a battery. The output capacity of each of the generator G and motor 7 is determined so that the maximum output of the generator G may substantially coincide with the maximum control electric power that is supplied to the motor 7. The over-current with respect to the motor is suppressed by the output impedance of the generator G. A CPU 102 performs output control so as for the output to conform to the load according to the electric current with respect to the motor. If the electric current increases, the voltage is varied to a level thereof that conforms to that electric current for ensuring sufficient torque.

Circulating current's characteristics analysis and the control strategy of parallel system based on double close-loop controlled VSI

Abstract: Real and reactive power circulation is produced because of the differences of amplitude and phase of each module's output voltage in parallel inverter system. The expression of equivalent output impedance is acquired through the close-loop transfer functions of double close-loop controlled inverter, then the characteristics of circulating current of parallel system are well researched from the point of view of equivalent output impedance. Theoretic analysis and experimental results prove that the magnitude of circulating current is proportional to the voltage difference and to the reciprocal of equivalent output impedance's modulus, the ratio of reactive and real power circulation is determined by the tangent of output impedance's angle. Finally a new control strategy for this kind of parallel inverter system is proposed and verified by simulation and experimental results.

Integrated power supply frequency domain impedance meter (IFDIM)

Abstract: IFDIM is an integrated and self-checking on-die current throttling method that accurately measures CPU's power delivery impedance profile from the die up to the voltage regulator. Impedance profile characterization in 100Hz-600MHz frequency ranges is demonstrated.

Biometric sensor and biometric method

Abstract: Using a cloth (6) between a metal electrode (2) and the body surface of a subject as a capacitance, a biometric sensor (1) is touched to the body surface through capacitive coupling, a bioelectric signal is extracted from the metal electrode (2), and an electrocardiographic waveform is outputted using an impedance converter having a high input impedance and a low output impedance from the out put of the biometric sensor (1).

SITO High Output Impedance Transadmittance Filter Using FTFNs

Abstract: FTFN based single input and three outputs transadmittance filter topology supporting simultaneously three filtering signals LP, BP, and HP without any passive component matching conditions is presented. The filter uses three PFTFNs and five passive components and realizes all current signals at high impedances, lending feature of cascadibility to the circuit. The circuit enjoys low sensitivity figures. PSPICE simulation results confirming the theoretical calculations are included.

Series terminated CMOS output driver with impedance calibration

Abstract: A differential line driver includes a plurality of driver cells Control logic outputs positive and negative control signals to the driver cells so as to match a combined output impedance of the driver cells at (Vop, Von) Each driver cell includes an input Vip and an input Vin, an output Vop and an output Von, a first PMOS transistor and a first NMOS transistor having gates driven by the input Vip, and a second PMOS transistor and a second NMOS transistor having gates driven by the input Vin A source of the first PMOS transistor is connected to a source of the second PMOS transistor A source of the first NMOS transistor is connected to a source of the second NMOS transistor First and second resistors are connected in series between the first PMOS transistor and the first NMOS transistor, and connected together at Von Third and fourth resistors are connected in series between the second PMOS transistor and the second NMOS transistor, and connected together at Vop A first output switch is driven by a corresponding positive control signal and connected between a supply voltage and the sources of the first and second PMOS transistors A second output switch driven by a corresponding negative control signal and connected between a ground and the sources of the first and second PMOS transistors

Multi-mode power amplifier

Abstract: A power amplifier includes an input network, output stages, coupled in parallel and configured to output power optimally in corresponding power-ranges, the output stages coupled to the input network, an output impedance matching network, coupled to the output stages and not containing a switching element, and a bias-control network, coupled between the output impedance matching network, the input network, and the output stages. In some amplifiers the output impedance matching network does not contain a switching element corresponding to the output stage configured to output power in the highest range. In other amplifiers the bias-control network is configured to isolate output stages by providing a hard shut-off to transistors of the isolated output stages.