Showing papers on "Output impedance published in 2011"

Impedance-Based Stability Criterion for Grid-Connected Inverters

Abstract: Grid-connected inverters are known to become unstable when the grid impedance is high. Existing approaches to analyzing such instability are based on inverter control models that account for the grid impedance and the coupling with other grid-connected inverters. A new method to determine inverter-grid system stability using only the inverter output impedance and the grid impedance is developed in this paper. It will be shown that a grid-connected inverter will remain stable if the ratio between the grid impedance and the inverter output impedance satisfies the Nyquist stability criterion. This new impedance-based stability criterion is a generalization to the existing stability criterion for voltage-source systems, and can be applied to all current-source systems. A single-phase solar inverter is studied to demonstrate the application of the proposed method.

Modeling and Analysis of Grid Harmonic Distortion Impact of Aggregated DG Inverters

Abstract: This paper proposes an impedance-based analytical method for modeling and analysis of harmonic interactions between the grid and aggregated distributed generation (DG) inverters. The root cause of harmonic interaction/resonance problems is the impedance-network quasi-resonance between the effective output impedance of the inverter and the equivalent grid impedance at the connection point. Starting with the output impedance modeling of an inverter, a Norton model of the inverter is derived. Comparing with the switching model and the average model of the inverter, simulation results show the effectiveness of the model. This paper proposes that impedance limits should be specified and used as an extra design constraint for DG inverters in order to minimize the harmonic distortion impact on the grid. Assuming the impedance models of individual inverters and local loads within a distribution grid are known, especially in the case of new grids under construction, harmonic interactions between the grid and a certain number of DG inverters can be preliminarily estimated.

Design of Highly Efficient Broadband Class-E Power Amplifier Using Synthesized Low-Pass Matching Networks

Abstract: A new methodology for designing and implementing high-efficiency broadband Class-E power amplifiers (PAs) using high-order low-pass filter-prototype is proposed in this paper. A GaN transistor is used in this work, which is carefully modeled and characterized to prescribe the optimal output impedance for the broadband Class-E operation. A sixth-order low-pass filter-matching network is designed and implemented for the output matching, which provides optimized fundamental and harmonic impedances within an octave bandwidth (L-band). Simulation and experimental results show that an optimal Class-E PA is realized from 1.2 to 2 GHz (50%) with a measured efficiency of 80%-89%, which is the highest reported today for such a bandwidth. An overall PA bandwidth of 0.9-2.2 GHz (84%) is measured with 10-20-W output power, 10-13-dB gain, and 63%-89% efficiency throughout the band. Furthermore, the Class-E PA is characterized through measurements using constant-envelop global system for mobile communications signals, indicating a favorable adjacent channel power ratio from -40 to -50 dBc within the entire bandwidth.

Modeling and mitigation of harmonic resonance between wind turbines and the grid

Abstract: Harmonic resonance can happen in traditional power systems between power factor correction (PFC) capacitors and transformer leakage inductance. In a distribution network with high penetration of renewable generation sources, inverter PWM harmonic currents can be a source of harmonic excitation for system resonance. This paper discusses harmonic resonance problems caused by impedance interactions between the wind inverter and the grid. An impedance-based analysis approach is used to characterize such resonance. Modeling of inverter output impedance directly in the phase domain to enable such analysis is presented. Possible mitigation methods by active damping and grid synchronization design are presented, and their effectiveness demonstrated by simulations and experiments.

A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application

Abstract: A 2.4 GHz outphasing power amplifier (PA) is implemented in a 32 nm CMOS process. An inverter-based class-D PA topology is utilized to obtain low output impedance and good linearity in the outphasing system. MOS switch non-idealities, such as finite on-resistance and finite rise and fall times are analyzed for their impact on outphasing linearity and efficiency. Outphasing combining is performed via a transformer configured to achieve reduced loss at power backoff. The fabricated class-D outphasing PA delivers 25.3 dBm peak CW power with 35% total system Power Added Efficiency (includes all drivers). Average OFDM power is 19.6 dBm with efficiency 21.8% when transmitting WiFi signals with no linearization required. The PA is packaged in a flip-chip BGA package. Good linearity performance (ACPR and EVM) demonstrates the applicability of inverter-based class-D amplifiers for outphasing configurations.

Current mode DC/DC converter with controlled output impedance

Abstract: A DC/DC converter has an output voltage and sources an output current to a load. The DC/DC converter includes an error amplifier with a reference input and a summing input. The reference input is electrically connected to a reference voltage. The summing input is electrically connected to the output voltage and the output current. The summing input is configured for adding together the output voltage and the output current. The error amplifier issues an error signal and adjusts the error signal dependent at least in part upon the output voltage and the output current. A comparator receives the error signal. The comparator has a ramp input electrically connected to a voltage ramp signal. The comparator issues an output signal that is based at least in part upon said error input. A power switch has an on condition and an off condition, and supplies dc current to the load when in the on condition. The power switch has a control input electrically connected to the comparator output signal. The power switch is responsive to the control input to change between the on condition and the off condition to thereby adjust the output current of the DC/DC converter.

T-section dual-band impedance transformer for frequency-dependent complex impedance loads

Abstract: A simple and successful design for matching complex impedance loads with different values at two different frequencies is presented. The explicit closed-form equations for the transformer parameters are derived analytically. The validity of the proposed design is verified by a numerical example of designing the input matching network of an amplifier.

A Novel UHV/EHV Transmission-Line Pilot Protection Based on Fault Component Integrated Impedance

Abstract: Based on the ratio of the sum of the fault component voltage phasors across the two terminals in the transmission line to the sum of the current phasors through the same line, which is defined as fault component integrated impedance in this paper, a new transmission-line pilot protection principle is proposed. When an external fault occurs, the amplitude of the fault component integrated impedance that reflects the capacitance impedance of the line becomes large; When an internal fault occurs, the amplitude of the fault component integrated impedance which reflects the impedance of the system source and the line, becomes relatively small. Therefore, the fault in the line can be detected according to this characteristic. The criterion is not affected by the current through the capacitance and is not affected by the fault resistance. It can be applied to the line with or without shunt reactor. Also, it can be easily set. Both the simulation results with Electromagnetic Transients Program and dynamic model data verify the validity of the proposed principle.

Hybrid-Source Impedance Networks: Layouts and Generalized Cascading Concepts

Abstract: Hybrid-source impedance networks have attracted attention among researchers because of their flexibility in performing buck-boost energy conversion. To date, three distinct types of impedance networks can be summarized for implementing voltage-type inverters with another three types summarized for current-type inverters. These impedance networks can in principle be combined into two generic network entities, before multiple of them can further be connected together by applying any of the two proposed generalized cascading concepts. The resulting two-level and three-level inverters implemented using the cascaded networks would have a higher output voltage gain and other unique advantages that currently have not been investigated yet. It is anticipated that these advantages would help the formed inverters find applications in photovoltaic and other renewable systems, where a high voltage gain is usually requested. Experimental testing for validating the extra boosting has already been conducted with some representative results presented at the end of this paper.

Optimal Damping of EMI Filter Input Impedance

Abstract: Damping of EMI filter input impedance to avoid resonance with the source output impedance is presented. Optimization of the damping resistor to maximize the damping effects for a given damping capacitor or inductor while minimizing the power loss is proposed. Three different damping circuits are studied, and for each, an analytical model defining the optimal damping resistance is presented. Performances of these damping circuits are compared in terms of achievable damping effects and power dissipation, as well as size and volume of damping capacitors and inductors. A case study is also presented to illustrate the application of the proposed design.

Adaptive Droop Resistance Technique for Adaptive Voltage Positioning in Boost DC–DC Converters

Abstract: In this paper, an adaptive droop resistance (ADR) technique can compensate for the adaptive voltage positioning (AVP) control in a boost dc-dc converter. A loop analysis is derived with the AVP technique to show the effects of the right-half-plane (RHP) zero. When the value of RHP zero is above the equivalent series resistance (ESR) zero, constant output impedance can be guaranteed by the proposed compensation method. Once the value of RHP zero is below five times of ESR zero, the proposed ADR technique can vary the droop resistance to track the variation of the load current to increase the system stability. In case of load current variation, the output impedance is proven constant due to the implementation of the AVP technique in the boost converter. The transient response time is 22 μS when a 200-mA load current step occurs, which is faster than that of a conventional boost converter. Even at heavy loads, the ADR technique can ensure a fast and stable transient response without being affected by the RHP zero. The experimental results demonstrate that the proposed method can increase system stability and guarantee a fast transient response in the design of a boost converter with the AVP technique.

Impedance matching device, and control method

Abstract: In an impedance matching device, a storage unit stores a control value representing a load value and a value equivalent to input impedance in advance. The control value identifies inductance and capacitance values matching a predetermined impedance value by use of either a first or second matching circuit. An impedance estimation unit estimates input impedance of the power transmission antenna. The load value estimation unit estimates load value of a circuit connected to a power reception antenna and consuming transmitted electric power. A circuit selection unit electrically connects the first matching circuit, the second matching circuit, or a through circuit per the load value and the input impedance equivalent value. A control value output unit reads out the control value stored in the storage unit based on the load value and the input impedance equivalent value, and outputs the control value to the circuit selected by the circuit selection unit.

Optimum Design of Asymmetrical Multisection Two-Way Power Dividers With Arbitrary Power Division and Impedance Matching

Abstract: A general analysis and design procedure is developed for the asymmetrical multisection power divider with arbitrary power division ratio and arbitrary specifications of input and output impedance matching over any desired frequency bandwidth. The even- and odd-mode analysis, which was previously applied to the design of multisection Gysel power dividers, required that the unequal power division ratios be accompanied with appropriately proportional output impedances. This requirement is relaxed here. The equivalent circuits are first obtained for the divider and then their scattering parameters are determined. Some error functions are then constructed by the method of least squares. Their minimization determines the geometrical dimensions of the optimum divider. An approximate method based on the even and odd modes is developed for its initial design of the divider. Two examples of single- and double-section dividers are designed. Their frequency responses of isolation and transmission coefficients are obtained by the proposed method, HFSS software, fabrication, and measurement. They agree within the approximate assumptions. A two-section and two-way power divider is designed and fabricated by the proposed method for the case of unequal port impedances in the L-band. The measured isolation between the outputs is better than -22 dB in 44% of the band.

Adaptive tuning of an impedance matching circuit in a wireless device

Abstract: Techniques for adaptively tuning an impedance matching circuit are disclosed. In an aspect, the impedance matching circuit is pre-characterized. The performance of the impedance matching circuit is determined for multiple settings of the impedance matching circuit, stored in memory, and used to tune the impedance matching circuit. In another aspect, the impedance matching circuit is tuned based on measurements for one or more parameters such as delivered power, return loss, power amplifier current, antenna/load impedance, etc. In an exemplary design, an apparatus includes a memory and a control unit. The memory stores information for multiple settings of an impedance matching circuit. The control unit selects one of the multiple settings of the impedance matching circuit based on the information for the multiple settings and measurements for the impedance matching circuit. The impedance matching circuit performs impedance matching for a load circuit (e.g., an antenna) based on the selected setting.

A new, improved CMOS realization of CDTA and its filter applications

Abstract: This paper presents a high-performance current differencing transconductance amplifier (CDTA), a re- cently reported active element, especially suitable for analog signal processing applications. A high linearity CMOS configuration for a CDTA is made up of high linearity input and output stages. The proposed CDTA provides high output impedance at port X and excellent input/output current tracking. A biquad filter cir- cuit was chosen as an application example in order to demonstrate the performance of the CDTA. PSpice simulation results using a TSMC 0.35-μ m CMOS process model were included to verify the expected values.

Ultralow-noise chopper amplifier with low input charge injection

Abstract: A chopper amplifier is presented that achieves an ultralow voltage noise of 0.73 nV/√Hz down to a few millihertz. Excess white and 1/f current noise was observed, which increases with the chopping frequency. At the lowest chopping frequency of 570 Hz, a noise level of 40 fA/√Hz with a 1/f corner at 3 mHz is obtained, corresponding to a noise temperature around 1 K at the optimum source impedance of 18 kΩ. Special care was taken to compensate the effect of switching spikes in the input chopper, resulting in a low charge injection into the signal source. The amplifier has a fixed gain of 1000. Postamplification and postfiltering with a wide range of settings, as well as optical output isolation based on a highly linear voltage-to-frequency converter, make the instrument well suited for demanding applications in metrology.

A Novel Method for Synthesizing an Automatic Matching Network and Its Control Unit

Abstract: We present a novel method simplifying matching network synthesis and design based on a tunable low-pass π matching network topology. This method exploits the Smith chart in a novel way. Analytic expressions for calculating the optimal matching network for automatically adapting the load to the source impedance are derived. This work is applied to a new antenna tuning unit concept able to calibrate the system in a single iteration process reducing strongly both the speed and the overall consumption of the antenna calibration module. The obtained matching network nodal and load quality factors are analyzed and the matching network efficiency is evaluated to highlight the impact of the imperfection in the design. The simulation and experimental results are presented to validate the proposed method and to evaluate the obtained matching efficWe present a novel method simplifying matching network synthesis and design based on a tunable low-pass π matching network topology. This method exploits the Smith chart in a novel way. Analytic expressions for calculating the optimal matching network for automatically adapting the load to the source impedance are derived. This work is applied to a new antenna tuning unit concept able to calibrate the system in a single iteration process reducing strongly both the speed and the overall consumption of the antenna calibration module. The obtained matching network nodal and load quality factors are analyzed and the matching network efficiency is evaluated to highlight the impact of the imperfection in the design. The simulation and experimental results are presented to validate the proposed method and to evaluate the obtained matching efficiency. We perform reflection coefficients less than -30 dB, high efficiency matching networks with only 258 μs to calculate the proper state of the tunable matching network under a processor delivering 40 MIPS of performance.iency. We perform reflection coefficients less than -30 dB, high efficiency matching networks with only 258 μs to calculate the proper state of the tunable matching network under a processor delivering 40 MIPS of performance.

Design of Impedance Measuring Circuits Based on Phase-Sensitive Demodulation Technique

Abstract: Impedance measuring circuits play a crucial role in an electrical impedance tomography system, in which capacitance and resistance need to be measured accurately at a high speed. Several impedance measuring circuits based on phase-sensitive demodulation (PSD) have been designed, tested, and presented in this paper. The measurement error is analyzed, and the mismatch of the measured capacitance and resistance is considered to be the main cause of the measurement error. A new impedance measuring circuit with dual-frequency PSD has been designed to solve this problem. It has been proven by experiment that this circuit can be used to measure both capacitance and resistance with an uncertainty of less than 0.5%.

Scalable high-swing transmitter with rise and/or fall time mismatch compensation

Abstract: Disclosed is a high-swing voltage-mode transmitter or line driver. The transmitter can operate over a wide range of supply voltages. Increasing the available output swing merely involves increasing the supply voltage; the circuit adapts to maintain the desired output impedance. This allows for a tradeoff between output amplitude and power consumption. Another advantage of the proposed architecture is that it compensates for process, voltage, and temperature (PVT) and mismatch variations so as to keep rise and fall times matched. This feature reduces common-mode noise and hence EMI in systems in which the transmitter is used.

Digital hybrid ripple-based constant on-time control for voltage regulator modules

Abstract: This paper presents a digital hybrid ripple-based constant on-time control scheme for voltage regulator modules (VRMs). Due to the sampling effects of the digital implementation, the stability issue becomes worse than the analog ripple-based control schemes, especially when low-ESR decoupling capacitors are used as the output filter. In order to stabilize the system and to fulfill the output impedance requirement of adaptive voltage positioning (AVP), a hybrid ramp compensation strategy, which includes the external ramp and the estimated current ramp, is proposed. The small-signal model of the proposed architecture is derived to provide the design guideline for the ramp compensation gains and the number of output and decoupling capacitors. Besides, only low sampling-rate Analog-to-Digital Converters (ADCs) are required to sample the input voltage, the output voltage, and the average current making the proposed architecture compatible with the cost/complexity constraints of VRM applications. Simulation and experimental results show that the ripple-based control can achieve high-bandwidth performance, and the proposed digital control architecture can fulfill the AVP design requirements of single-phase VRMs.

Extracting characteristic impedance in low-loss substrates

Abstract: A method to determine the characteristic impedance of transmission lines considering the substrate loss is presented. The extracted data shows that at microwave frequencies the finite loss tangent parameter impacts the characteristic impedance even in a low-loss substrate.

Design and control of the phase shift full bridge converter for the on-board battery charger of the electric forklift

Abstract: This paper describes the design and control of phase shift full bridge converter with a current doubler, which can be used for the on-board charger for the lead-acid battery of the electric forklift. Unlike the common resistance load the battery has a large capacitance element and it absorbs the entire converter output ripple current thereby shortening the battery life and degrading the system efficiency. In this paper the phase shift full bridge converter with a current doubler has been adopted to decrease the output ripple current and the transformer rating of the charger. The charge controller is designed by using small signal model of the converter considering the internal impedance of the battery. The stability and performance of the battery charger is then verified by the constant current(CC) and constant voltage(CV) charge experiments using an actual lead-acid battery bank for the electric forklift.

Stationary frame control scheme for a stand-alone doubly fed induction generator system with effective harmonic voltages rejection

Abstract: A novel stationary frame control scheme for harmonic voltages rejection in a stand-alone doubly fed induction generator (DFIG) with non-linear loads is proposed in this study. The distortion in the stator output voltage of the stand-alone DFIG is mainly because of the non-linear voltage drop in the internal impedance of the generator caused by the non-linear load current. The proposed control scheme directly regulates the instantaneous rotor current in the rotor-side converter (RSC) to reject the fifth and seventh harmonics in the stator output voltage at the point of common coupling (PCC). The main contribution of this study is the development of a novel reference rotor current generator implemented in the stationary reference frame. In this frame, the rotor current controller is developed based on a proportional and three resonant regulators (P3R) that is capable of directly regulating the fundamental, fifth and seventh components of rotor currents without involving decompositions of sequential components. Simulations and experimental results with a 2.2 kW DFIG supplying non-linear loads are presented to demonstrate advanced features of the proposed control scheme.

Power transfer for a running automobile

Abstract: We herein propose power transfer through a capacitor composed of a steel belt in a tire and a metal plate attached to the road. In the present study, metal plates were arranged above and below a tire, and the complex impedance between these plates was measured. A matching circuit bridging the large impedance gap between the tire and 50-ohm lines was designed, and the transmission property was simulated. The measurement revealed that the real and imaginary parts of the complex impedance at 1 MHz were approximately 700 ohm and–2,000 ohm, respectively. For the matching, S 21 was confirmed to be approximately −0.1 dB

Front-end rf filters with embedded impedance transformation

Abstract: Front-end radio frequency (RF) filters with embedded impedance transformation are disclosed. In an exemplary design, an apparatus includes an active circuit and an RF filter. The active circuit receives an input signal and provides an output signal. The RF filter is operatively coupled to an antenna and the active circuit and performs filtering for the input signal or output signal. The RF filter is impedance matched to the active circuit and includes a non-LC filter. In an exemplary design, the active circuit includes a low noise amplifier (LNA), and the RF filter includes a receive (RX) filter having an output impedance that is matched to an input impedance of the LNA. In another exemplary design, the active circuit includes a power amplifier, and the RF filter includes a transmit (TX) filter having an input impedance that is matched to an output impedance of the power amplifier.

Suppression of common-mode input electromagnetic interference noise in DC–DC converters using the active filtering method

Abstract: This study introduces a technique that combines passive and active electromagnetic interference (EMI) filtering methods to attenuate the common mode conducted noise in the input bus of the DC/DC converter and to minimise the size and the cost of the existing passive EMI filters. The technique presented can be implemented in all DC/DC converters topologies to provide a level of compliance with the electromagnetic directives. The circuit analysis and the attenuation curves showing the performance and the viability of this technique is provided. The filter input/output impedance criterion is verified to ensure the stability of the converter, by measuring the gain and the phase margins of the open-loop frequency response of the converter. The proposed technique provides a valuable design solution for compliance engineers where the Printed Circuit Board real-estate is an issue. Experimental results reveal more than 30 dB attenuation across the electromagnetic compatibility spectrum. This method contributes to the reduction of the size and weight of the input passive EMI filter. The proportion of the passive filter as compared to the DC/DC converter device can vary from 5 to 3%, depending on the converter specifications. Experimental results to demonstrate the performance and the effectiveness of the input active EMI filter in DC/DC converters are presented.

Current/voltage-mode third order quadrature oscillator employing two multiple outputs CCIIs and grounded capacitors

Abstract: A new quadrature oscillator circuit using two multiple outputs second-generation current conveyors (CCIIs), three grounded capacitors and three resistors is presented. Two high output impedance current-mode signals and two voltagemode signals each pair with 90 ° phase difference are available in the proposed circuit. The oscillation condition and oscillation frequency are independently controllable through grounded resistors. The use of only grounded capacitors makes the proposed circuit attractive for integrated circuit implementation.

Electronic devices with adjustable bias impedances and adjustable bias voltages for accessories

Abstract: Electronic devices may provide microphone bias voltages to accessories. The accessories may include circuitry powered from the microphone bias voltages. The output impedances and the voltages of the microphone bias voltages may be adjusted during operation of the electronic devices. An electronic device may provide a bias voltage to an accessory, may lower the output impedance of the bias voltage, and may increase the voltage of the bias voltage during operation of the electronic device. Accessories that received bias voltages with lowered impedances or raised voltage levels may exhibit greater tolerance to faults such as moisture-based shorts and may be able to continue operating even in the presence of some faults.