Output impedance

About: Output impedance is a research topic. Over the lifetime, 11185 publications have been published within this topic receiving 134949 citations.

Controlling for variable impedance and voltage in a memory system

Abstract: A memory interface device, system, method, and design structure for controlling for variable impedance and voltage in a memory system are provided. The memory interface device includes a calibration cell configurable to adjust an output impedance relative to an external reference resistor, and driver circuitry including multiple positive drive circuits and multiple negative drive circuits coupled to a driver output in a memory system. The memory interface device further includes impedance control logic to adjust the output impedance of the calibration cell and selectively enable the positive and negative drive circuits as a function of a drive voltage and a target impedance.

Level shifter circuit and semiconductor device including the same

Abstract: A circuit is disclosed that can output signals from different circuit blocks at a common output terminal with a smaller number of transistors than conventional approaches. When a level shifter circuit receives a high voltage level at a control terminal ( 2 ), a level shifter unit ( 12 ) is placed in the operational state to provide an output signal from a low voltage system block, and a clocked inverter ( 106 ) is placed in the non-operational state. When a level shifter circuit receives a low voltage level at a control terminal ( 2 ), a clocked inverter ( 106 ) is placed in the operational state to provide an output signal from a high voltage system block. At the same time, PMOS transistor ( 105 ) can be turned on, resulting in PMOS transistors ( 5 ) being turned off. Further, NMOS transistors ( 109 and 110 ) are turned off. This can result in an output impedance of a level shifter unit ( 12 ) being set to a high impedance state. Thus, an output from a level shifter unit ( 12 ) can have essentially no influence on an output signal of clocked inverter ( 106 ).

Multi-band high-efficiency doherty amplifier

Abstract: The present invention relates to a Multi-Band Doherty amplifier. Embodiments of the present invention provide an amplifying structure including a main amplifier configured to amplify a first signal, a peak amplifier configured to amplify a second signal, a tunable impedance inverter configured to perform impedance inversion to modulate a load impedance of the main amplifier, and a combining node configured to receive the amplified second signal from the peak amplifier and an output of the tunable impedance inverter. The tunable impedance inverter includes a tuner configured to tune the impedance inversion over at least one broad frequency band. The tuner is (i) at least one capacitor, (i) at least one varactor, or (ii) at least one open stub shunted by a diode.

High-Frequency Power Gain of Junction Transistors

Abstract: The purpose of this paper is three-fold. First, the subject of maximum available power gain at high frequencies is discussed briefly. Also, maximum gain for a four-terminal network driven by a generator having a purely resistive internal impedance is calculated in terms of small-signal parameters of the network. Then a theoretical model of a junction transistor comprising the ideal one-dimensional model plus a base impedance, which may be complex and frequency-dependent as in the case of grown-junction transistors, is introduced for the network to obtain an expression for maximum available power gain in terms of fundamental device parameters. Experimental results, which are given for a number of grown-junction transistors, tend to confirm the theoretical expression. Finally, an idealized model of a grown-junction transistor is introduced, and theoretical power gain is calculated in terms of physical parameters. Such calculations show, for example, that 30 db of gain should be available at 5 mc and that such transistors should be capable of oscillating up to several hundred mc.

CMOS switch with linearized gate capacitance

Abstract: A CMOS switch with compensation circuitry that maintains linearized gate capacitance, said switch capable of selectively processing a signal independent of changes to gate capacitance current. The switch passes signals which are substantially insensitive to changes in source impedance. Thus, the switch processes an analog signal with a minimum of distortion as a result of gate capacitance currents.