Topic
Output impedance
About: Output impedance is a research topic. Over the lifetime, 11185 publications have been published within this topic receiving 134949 citations.
Papers published on a yearly basis
Papers
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TL;DR: Extensive simulation results verify that the proposed high-precision low-voltage adaptively biased low-dropout regulator with extended loop bandwidth achieves high loop bandwidth, fast line and load transient responses, high power supply rejection, and low output impedance.
Abstract: A high-precision low-voltage adaptively biased (AB) low-dropout regulator (LDR) with extended loop bandwidth is proposed. The multistage output-capacitor-free LDR is stabilized by Miller compensation and Q-reduction techniques to reduce the required minimum load current. Adaptive biasing is achieved by using direct current feedback from a simple current mirror. The dynamics of both the main feedback loop (MFL) and the adaptive biasing loop are thoroughly analyzed. Tradeoffs between the adaptive biasing factor and the MFL stability are discussed. The AB LDR is designed using a standard 0.35- ?m CMOS technology ( Vtn ? 0.52 V and Vtp ? -0.72 V). The output is 1.0 V, which delivers a maximum current of 100 mA. The minimum input voltage is 1.2 V, and the minimum load current required is reduced to 50 ?A . Extensive simulation results verify that the proposed LDR achieves high loop bandwidth, fast line and load transient responses, high power supply rejection, and low output impedance.
105 citations
TL;DR: This paper describes an 8-channel gel-free EEG/electrode-tissue impedance (ETI) acquisition system, consisting of nine active electrodes (AEs) and one back-end (BE) analog signal processor, capable of recording 8- Channel EEG and ETI signals.
Abstract: This paper describes an 8-channel gel-free EEG/electrode-tissue impedance (ETI) acquisition system, consisting of nine active electrodes (AEs) and one back-end (BE) analog signal processor. The AEs amplify the weak EEG signals, while their low output impedance suppresses cable-motion artifacts and 50/60 Hz mains interference. A common-mode feed-forward (CMFF) scheme boosts the CMRR of the AE pairs by 25 dB. The BE post-processes and digitizes the analog outputs of the AEs, it also can configure them via a single-wire pulse width modulation (PWM) protocol. Together, the AEs and BE are capable of recording 8-channel EEG and ETI signals. With EEG recording enabled, ETIs of up to 60 kΩ can be measured, which increases to 550 kΩ when EEG recording is disabled. Each EEG channel has a 1.2 GΩ input impedance (at 20 Hz), 1.75 μVrms (0.5-100 Hz) input-referred noise, 84 dB CMRR and ±250 mV electrode offset rejection capability. The EEG acquisition system was implemented in a standard 0.18 μm CMOS process, and dissipates less than 700 μW from a 1.8 V supply.
104 citations
TL;DR: A new three inputs and single output voltage-mode universal biquadratic filter with high-input and low-output impedance using three plus-type differential difference current conveyors, two grounded capacitors and two grounded resistors is presented.
Abstract: A new three inputs and single output voltage-mode universal biquadratic filter with high-input and low-output impedance using three plus-type differential difference current conveyors, two grounded capacitors and two grounded resistors is presented. The proposed circuit offers the following features: realization of all the standard filter functions, that is, high-pass, bandpass, low-pass, notch, and all-pass filters, no requirements for component matching conditions, the use of only grounded capacitors and resistors, high-input and low-output impedance and low active and passive sensitivities.
103 citations
04 May 2004
TL;DR: In this paper, the P/Q droop method is used to avoid any communication among the modules in order to achieve stable output impedance value, and therefore, proper power balance is guaranteed when sharing both linear and nonlinear loads.
Abstract: This paper deals with the design of the output impedance of UPS inverters with parallel-connection capability. The inner control loops are considered in the design of the controllers that makes possible the power sharing among the UPS modules. In these paralleled units, the power-sharing outer control loops are based on the P/Q droop method in order to avoid any communication among the modules. The power sharing accuracy is highly sensitive to the output impedance of the inverters, making necessary the tight adjustment of this impedance. Novel control loops are proposed to achieve stable output impedance value, and, therefore, proper power balance is guarantee when sharing both linear and nonlinear loads.
103 citations
01 Nov 2011
TL;DR: In this paper, an impedance-based analysis approach is used to characterize the harmonic resonance caused by impedance interactions between the wind inverter and the grid and possible mitigation methods by active damping and grid synchronization design are presented, and their effectiveness demonstrated by simulations and experiments.
Abstract: Harmonic resonance can happen in traditional power systems between power factor correction (PFC) capacitors and transformer leakage inductance. In a distribution network with high penetration of renewable generation sources, inverter PWM harmonic currents can be a source of harmonic excitation for system resonance. This paper discusses harmonic resonance problems caused by impedance interactions between the wind inverter and the grid. An impedance-based analysis approach is used to characterize such resonance. Modeling of inverter output impedance directly in the phase domain to enable such analysis is presented. Possible mitigation methods by active damping and grid synchronization design are presented, and their effectiveness demonstrated by simulations and experiments.
103 citations