Output impedance

About: Output impedance is a research topic. Over the lifetime, 11185 publications have been published within this topic receiving 134949 citations.

Data processor having an output terminal with selectable output impedances

Abstract: A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance than the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.

Circuit and method for impedance matching

Abstract: An impedance matching circuit ( 10 ) matches the impedance of a load ( 19 ) coupled to an RF amplifier ( 12 ) to that of the RF amplifier ( 12 ). The impedance matching circuit ( 10 ) samples a transmitted signal from the RF amplifier ( 12 ) and a reflected signal from the load ( 19 ). The amplitude and the phase of the sampled reflected signal are compared with those of the sampled transmitted signal to calculate the impedance mismatch. A control logic circuit ( 80 ) adjusts the capacitance and inductance values of variable capacitance ( 23; 27 ) and inductance ( 35 ) elements in the impedance matching circuit ( 10 ), thereby matching the impedance of the load ( 19 ) to that of the RF amplifier ( 12 ).

Transformer coupled stacked FET power amplifiers

Abstract: The development of high-power linear ultrahigh-frequency amplifiers is made difficult by the low impedance of the devices used in the output stage, which causes matching difficulties and high radio-frequency current levels. A stacked field-effect transistor (FET) configuration is shown to reduce these problems with its increased output impedance and lower current required for a given output power. A linear analysis of the stacked FET configuration is given. Two class A monolithic microwave integrated circuit amplifiers are developed and subjected to one- and two-tone tests to demonstrate the performance of the stacked FET as a power amplifier at 900 MHz.

A Reactive Power Sharing Strategy of VSG Based on Virtual Capacitor Algorithm

Abstract: In the islanded microgrid, distributed generators are controlled with virtual synchronous generator (VSG) strategy to simulate rotor inertia and droop characteristics of synchronous generators, in order to enhance the voltage and frequency support capabilities. Since the capacity and location distribution of each VSG is random, the VSG output impedance, line impedance and its capacity are mismatched, resulting in inaccurate sharing of reactive power. Based on the study of reactive power sharing schemes without communication and system parameters detection, and aiming at the contradiction between reactive power sharing error and voltage control accuracy of existing schemes, a reactive power sharing strategy based on virtual capacitor is proposed. The strategy simulates characteristics of paralleling capacitor at the VSG output terminal, and compensates the output voltage according to adaptive control of VSG output reactive power, thus to reduce reactive power sharing error, and improve the voltage control accuracy meanwhile. The design of virtual capacitor parameters and a two VSG parallel system stability with proposed strategy are analyzed in this paper. The correctness and effectiveness of the proposed strategy is verified by experiments.

Current mode DC/DC converter with controlled output impedance

Abstract: A DC/DC converter has an output voltage and sources an output current to a load. The DC/DC converter includes an error amplifier with a reference input and a summing input. The reference input is electrically connected to a reference voltage. The summing input is electrically connected to the output voltage and the output current. The summing input is configured for adding together the output voltage and the output current. The error amplifier issues an error signal and adjusts the error signal dependent at least in part upon the output voltage and the output current. A comparator receives the error signal. The comparator has a ramp input electrically connected to a voltage ramp signal. The comparator issues an output signal that is based at least in part upon said error input. A power switch has an on condition and an off condition, and supplies dc current to the load when in the on condition. The power switch has a control input electrically connected to the comparator output signal. The power switch is responsive to the control input to change between the on condition and the off condition to thereby adjust the output current of the DC/DC converter.