Showing papers on "p–n junction published in 1969"

p-n junction—Schottky barrier hybrid diode

Abstract: A new fabrication technique for passivated silicon Schottky barrier diodes is described. It is shown that the p-n junction guard ring or "hybrid" approach produces Schottky barriers whose forward and reverse electrical characteristics are in excellent agreement with simple theory, and that the excess noise normally found in passivated Schottky barrier diodes has been significantly reduced. The influence of metal barrier height and diffusion profile on the charge storage characteristics of these devices is discussed and examined experimentally.

TYPE CONVERSION AND p‐n JUNCTION FORMATION IN ION‐IMPLANTED ZnTe

Abstract: Type conversion and p‐n junction formation, produced by the implantation of 400‐keV F+ ions into p‐type ZnTe, have been confirmed by the thermal probe test, photovoltaic effect, I‐V characteristics, Hall effect, and EPR results.

Electron Emission from a ``COLD-CATHODE'' GaAs p-n Junction

Abstract: Electron emission into vacuum has been observed from a forward‐biased Cs‐ and O‐treated GaAs p‐n junction. The device was operated at room temperature with dc bias voltage. The effective efficiency of the device (emission current divided by internal diode current eligible for emission) was 0.05%, while the over‐all efficiency of the device (emission current divided by total diode current) was 10−6. The low over‐all efficiency is explained in terms of sample geometry and surface activation.

Surface depletion layer photodevice

Abstract: A semiconductor photodevice sensitive to blue light is produced by placing an oxide layer containing a selected surface state charge density over one surface of the device. The fixed surface state charge density creates a surface depletion region in the semiconductor material immediately underlying the oxide. Blue light incident on the device, which is normally absorbed before reaching the depletion region associated with a PN junction strikes the surface depletion layer and produces photocurrent therein.

Variable integrated coupler

Abstract: Described is an integrated circuit variable coupler utilizing metal oxide semiconductor (MOS) techniques, wherein the degree of coupling or capacitance of the coupler is a function of the size of the depletion region of a PN junction which can be varied by a voltage applied across a thin film resistor deposited on an oxide layer.

Boundary conditions for the space-charge region of a P-N-junction

Abstract: The purpose of this paper is to show that the controversy concerning the relation of the applied potential difference to the difference across the space-charge region of a P - N -junction is due to a neglect of the non-zero gradients of the electrochemical potentials. By incorporating these quantities and by a suitable modification of the Fletcher boundary conditions, the inconsistencies discovered by Van Vliet and Gummel can be removed.

Method of forming a junction by ion implantation

Abstract: Disclosed is a method of forming a PN junction comprising the steps of implanting impurity ions into an insulating layer formed on the surface of a semiconductor substrate and then diffusing the implanted impurity ions into the surface layer of the semiconductor substrate thereunder.

An integrated complementary transistor circuit chip with polycrystalline contact to buried collector regions

Abstract: An integrated semiconductor device having a monocrystalline semiconductor substrate of one conductivity type, a diffused layer in the substrate of the opposite conductivity type, a vapor deposited layer formed on the substrate, the vapor deposited layer including a monocrystalline region, and a polycrystalline region of high-impurity concentration surrounding the monocrystalline region and extending from the diffused layer to the surface of the vapor deposited layer, a second monocrystalline region surrounding the polycrystalline region, and monocrystalline regions of high-impurity concentration contiguous to both sides of the polycrystalline region, the monocrystalline regions of high-impurity concentration having the same conductivity type as that of the polycrystalline region and forming a PN junction with the adjoining monocrystalline region.

Electroluminescent diode configuration and method of forming the same

Abstract: An electroluminescent diode which includes an electromagnetic radiation emitting PN junction formed by diffusing, into both surfaces of a semiconductor slice of a first conductivity, a dopant material of opposite type conductivity. Contact metallizations are mounted within windows in an insulating barrier which covers said diode so as to form electrical contacts engaging both the N and P type areas of the diode. An annular reflector metallization pad is mounted on the surface of the device over the PN junction and spaced from one surface of the semiconductor material by the insulating coating so as to reflect light out through the surface opposite to that on which an antireflection coating has been placed.

Method for fabricating semiconductor devices by ion implantation

Abstract: A semiconductor body acting as a collector is directed at a predetermined surface area by an inert ion beam from such a direction as not to produce a channeling effect in the body, whereby obtaining an amorphous surface region thereat, then directed at a larger surface area including said predetermined surface area by an active impurity ion beam of the conductivity type opposite to said body from a direction producing the channeling effect in the body, thereby obtaining a base region in the semiconductor body with a PN junction therebetween which has a partial projection in its bottom part, and further directed at said predetermined surface area by an active impurity ion beam of the same conductivity type as that of the body from the channeling-effect-providing direction, thereby obtaining an emitter region, and finally heat-treating, so that a transistor without defects due to the emitter dip effect is obtained.

The saturated photovoltage of a p-n junction

Abstract: This paper explores the relationship between the energy-gap voltage of a p-n junction and the saturation value of the open-circuit photovoltage produced by high-intensity illumination. It is shown that high excess-carrier concentrations in the quasi-neutral regions are accompanied by significant open-circuit drops in the quasi-Fermi voltages of both carriers in these regions. When these drops are accounted for, the open-circuit photovoltage is found to be less than the split between the quasi-Fermi voltages in the space-charge layer (which split is approximately equal to the energy-gap voltage) by an amount which depends on the ratio of the mobilities of the two carriers. This approximate theory reconciles the apparent inconsistencies in previously reported measurements of the saturated photovoltages of silicon and gallium-arsenide p-n junctions.

Surfce stabilization of semiconductor power devices and article

Abstract: EXPOSED SURFACES OF A BODY OF SEMICONDUCTOR MATERIAL HAVING A PORTION OF A PN JUNCTION EXPOSED THEREIN ARE ETCHED AND THEN CLEANED WITH EITHER A SOLUTION OF IODINE OR A SOLUTION OF IODINE AND IODINE PENTOXIDE. IMMEDIATELY PRIOR TO DEPOSITING A DIELECTRIC FILM OF SILICON DIOXIDE-SILICON NITRIDE TO OVERLIE THE CLEANED EXPOSED PN JUNCTIONS, ADSORBED IODINE IS REMOVED FROM THE BODY BY HYDROGEN GAS. A RESINOUS PROTECTIVE COATING MATERIAL IS APPLIED TO THE DIELECTRIC FILM TO AFFORD MECHANICAL AND ELECTRICAL PROTECTION.

Process for a self-isolation monolithic device and pedestal transistor structure

Abstract: A process for forming a self-isolated monolithic device by providing a substrate of a first conductivity type and forming an epitaxial layer of same conductivity type over the substrate. The epitaxial layer and the substrate are subjected to treatment so as to outdiffuse an impurity of opposite conductivity from the substrate and into the epitaxial layer so as to form a region which constitutes an element of the integrated circuit device and also defines an isolation PN junction with the epitaxial layer. Further, a pedestal transistor process forms a pedestal transistor for monolithic circuits by outdiffusing an impurity to form a subcollector region and outdiffusing another impurity having a higher diffusion rate to form the pedestal region. An extrinsic collector region defines an extrinsic junction with a lighter doped extrinsic base region so as to reduce overall base to collector capacitance.

Method of obtaining type conversion in zinc telluride and resultant p-n junction devices

Abstract: A method of making p-n junction devices by bombarding a polished crystal of ZnTe with ions of an element selected from the Group VII A elements and p-n junction devices resulting from this method. When the crystal is held at an elevated temperature during the ion bombardment step, subsequent annealing is usually not necessary. When the crystal temperature is at room temperature or below during the ion bombardment step, type conversion can be obtained only by post implantation annealing. The particular type of p-n junction device and the characteristics thereof are determined by the particular schedule of annealing to which the implanted body is subjected.

Method for producing passivated pn-junctions by ion beam implantation

Abstract: A method for producing tucked-under, passivated PN junctions in semiconductor devices by ion implantation through a layered mask. The mask comprises a first relatively thin dielectric layer and a conductive layer thereover. An aperture is formed in the conductive layer, and the structure is subjected to a beam of dopant ions having energy sufficient to penetrate the dielectric layer but insufficient to penetrate the combined layers. In this fashion a PN junction is formed in the semiconductor body underneath the aperture in the conductive layer. Then the conductive layer is caused to become thicker, e.g., by electroplating, which also causes the aperture in the second layer to become smaller in lateral dimension. Then, using the conductive layer as a mask, the portion of the dielectric layer exposed through the aperture is selectively removed, e.g., by backsputtering. In this manner there is exposed a portion of the surface which is smaller than the implanted zone.

Semiconductor device including a polycrystalline diode

Abstract: A semiconductor device consisting of a single crystal region, a polycrystalline region integrally formed on the single crystal region and a PN junction formed in the polycrystalline region.

Electrochemically controlled shaping of semiconductors

Abstract: A METHOD FOR SELECTIVELY ETCHING A SEMICONDUCTOR PARTICULARLY APPLICABLE TO PRECISION THINNING OF SILICON INTEGRATED CIRCUIT WAFERS. THE SEMICONDUCTOR AND A CATHODE ARE INSERTED IN AN ELECTROLYTE WHICH ETCHES THE SEMICONDUCTOR IN THE ABSENCE OF APPLIED VOLTAGE TO THE CATHODE, AND ALL OF THE SEMICONDUCTOR PORTIONS, WHICH ARE AT A POTENTIAL LESS THAN SOME PASSIVATION POTENTIAL, ARE ETCHED AWAY. THOSE SEMICONDUCTOR PORTIONS WHICH ARE AT A POTENTIAL GREATER THAN THE PASSIVATION POTENTIAL ARE NOT ETCHED. IN PRACTICE, A SUITABLE VOLTAGE DIFFERENTIAL (ABOVE AND BELOW THE PASSIVATION POTENTIAL) CAN EXIST ACROSS A PN JUNCTION, SO THAT THE ETCHING STOPS AUTOMATICALLY AT A JUNCTION THE LOCATION OF WHICH CAN BE ACCURATELY PREDETERMINED. ALTERNATIVELY, SERIES RESISTANCE CAN BE USED TO PROVIDED A SUITABLE VOLTAGE DIFFERENTIAL ACROSS PRESELECTED PORTIONS OF A SEMICONDUCTOR BODY. FOR SILICON, THE PASSIVATION POTENTIAL IS ABOUT 0.5 VOLT WHERE THE ELECTROLYTE IS POTASSIUM HYDROXIDE IN EQUILIBRIUM WITH AIR AND THE CATHODE IS PLATINUM.

Process for the fabrication of light-emitting semiconductor diodes

Abstract: A light-emitting semiconductor diode is made from an N-type crystal of GaAsP or GaP by the selective diffusion of zinc therein to form a PN junction. A special diffusion mask system is employed, to obtain a combination of direct diffusion into an unmasked region, and lateral diffusion beneath a selected portion of the mask. The major, active portion of the junction is formed by lateral diffusion, whereas that portion of the P-region formed by direct diffusion serves primarily as a preferred location for contact metallization.

Electrically focussed laser diode

Abstract: A laser diode for producing focused or defined divergent light comprises a semiconductor crystal having a planar PN junction and two parallel end faces extending perpendicular to the PN junction and conjointly forming a resonator for optical radiation. The end faces comprise portions of two confocal surfaces. The PN junction extends between the two confocal surfaces in a radial plane relative to the focal locus. One of the end faces is impermeable to optical radiation and the other of the end faces is a mirror partially permeable to optical radiation.

Fast switching pnp transistor

Abstract: The on-off switching time of a PNP transistor is significantly decreased by placing a Schottky Barrier diode in parallel with the collector-base PN junction of the transistor.

Varactor-controlled pn junction semiconductor microwave oscillation device

Abstract: A solid state microwave generating device comprising a 3-terminal element having a p-n junction representing a negative resistance and a junction of which the junction capacitance is varied according to a voltage applied thereto. A reverse voltage is imparted to said p-n junction so that the latter is maintained in a negative resistance condition resulting from an avalanche current. The other junction is set to a suitable reactance value so as to produce a microwave of a tuned wavelength, and under such a condition a modulating signal is supplied in superimposition to said other junction to thereby change the reactance value thereof, thus effecting microwave modulation. With this device, the oscillation wave occurring in a resonator circuit is controlled in accordance with lumped constants so that the tuning operation of the resonant circuit, modulation (FM), automatic frequency control (AFC) and so forth can be easily and efficiently performed.

Depletion layer capacitor in particular for monolithic integrated circuits

Abstract: This is a depletion layer capacitor which can be simultaneously formed with other planar transistors on a monolithic integrated circuit. The depletion layer capacitor achieves a high voltage breakdown by producing a PN junction which joins two highly doped regions of opposite conductivity type wherein said junction is established within an epitaxial layer of lower impurity concentration and doesn''t extend to the surface of said epitaxial layer.

Erratum: Numerical analysis of forward and reverse bias potential distribution in a 2-dimensional p-n junction with applications to capacitance calculations

Abstract: A method is described for the calculation of capacitance and potential distribution in a 2-dimensional p-n junction such as that at the edge of stripe transistors. The method uses a numerical solution of a modified 2-dimensional Shockley-Poisson equation on a nonuniform mesh.

Monolithic circuit with high q capacitor

Abstract: 1,213,321. Integrated circuits. TEXAS INSTRUMENTS Inc. 21 March, 1968 [30 June, 1967 (2)], No. 13723/68. Heading H1K.. An integrated circuit e.g. as shown in Fig.. 1 comprises an epitaxial layer on a substrate 12 of the opposite conductivity type with a plurality of diffused isolation rings 38 extending to the substrate and defining pockets in which complementary bi-polar transistors 28, 30 are formed. The collector 32 of one transistor 30 is formed by one isolated part of the epitaxial layer and the base 34 and emitter 36 by diffused inclusions therein, while the collector 22, base 24 and emitter 28 of the complementary transistor 20 are constituted by nested diffused regions in another isolated pocket. The Fig. 1 arrangement which also includes PN junction capacitor 40 is formed by the following steps: (1) N + inclusions 14-16 10 deep are formed in the silicon substrate and the 10 A epitaxial layer deposited over them; (2) isolation rings 38, collector region 22 and region 42 are formed by a masked diffusion step; (3) N-type base region 24 is diffused; (4) P-type base region 34 is diffused; (5) P-type emitter region 28 and the P + region 46 of the capacitor are formed in a common diffusion; (6) N-type emitter 36, base contact region 26 and the N + region 46 of the capacitor are formed in a common diffusion step. The zones of the alternative structure shown in Fig. 7 are formed by diffusion steps in the sequence (1) collector region 116 and capacitor region 142; (2) isolation rings 106; (3) collector region 124 and diode anode region 130; (4) base region 118; (5) junction isolated P-type resistor region 134; (6) base contact region 119, emitter region 126, diode cathode contact region 132 and capacitor region 146; (7) emitter region 120, base contact region 125 and capacitor contact region 144. Details are given of the diffusion steps which involve oxide masking and predeposition from boron tribromide and phosphorus oxychloride respectively.

Schottky barrier pressure sensitive semiconductor device with air space around periphery of metal-semiconductor junction

Abstract: Disclosed is a pressure-sensitive transistor whose emitter or collector junction is formed by use of a Schottky barrier junction and wherein the current through the transistor changes in accordance with the applied pressure when pressure is applied to said junction by pressure applying means. Such a transistor is advantageous in that a high pressure-to-current conversion factor is obtained, little noise is generated at the junction, and the reverse leakage current appearing at the junction is extremely small.

Planar zener diodes having uniform junction breakdown characteristics

Abstract: A high-voltage planar Zener diode in which enhanced switching performance is provided by a unique junction configuration. The junction is configured to provide low-series resistance and uniform conduction across a controlled region of the junction thereby to achieve uniform and sharp voltage breakdown characteristics.

Semiconductor element having surface coating and method of making the same

Abstract: A semiconductor element having a surface coating consisting of, for example, a silicon nitride film and a silicon oxide film covering different surface portions of a semiconductor substrate of, for example, silicon so that such surface coating can be utilized for selective diffusion of impurities such as gallium and antimony. In a semiconductor device thus formed, the surface coating acts as a satisfactory surface protective film against external atmosphere, and the backward characteristics of the PN junction can be improved because the end edge of the PN junction terminating at the substrate surface is covered with the silicon nitride film.

High-speed logic device employing a gunn-effect element and a semiconductor laser element

Abstract: A semiconductor device is described wherein a Gunn effect element is placed in series with the PN junction of a semiconductor laser. A bias potential is applied across the series connection to forwardly bias the PN junction and normally produce lasing action from the laser element. The bias potential is further selected so that current reductions produced by high electric field layers traveling within the Gunn element effectively suppress lasing actions. Several embodiments are shown.