Showing papers on "p–n junction published in 1973"

Microwave oscillations in pnp reach-through BARITT diodes

Abstract: Studies have been made on the microwave oscillations of reach-through p + np + and related structures operated as BARITT diodes (BARrier Injection Transit Time diodes). The mechanisms responsible for the microwave oscillatins are the exponential increase of the local carrier population at the forward-biased pn junction and the transit-time delay of injected carriers transversing the drift region. The small-signal impedance and noise measure of the device are calculated based on (1) the thermionic injection and the space-charge-limited effects and (2) the separation of the drift region into a low-field region and a saturated-velocity region. Microwave CW oscillatins have been obtained from p + np + BARITT diodes made from an epitaxial n on p + silicon substrate with epitaxial layer thickness of 8 μm and doping concentration of 5 × 10 14 cm −3 . Microwave CW power of the order of a few milliwatts has been obtained at 7 GHz with efficiency greater than 1 per cent. Good agreement has been obtained between the measured and the calculated small-signal impedances.

Light emitting diodes of the injection type

Abstract: In a PN junction light emitting diode of the injection type comprising a first semiconductor region having a forbidden band width equal at most, to the width of a PN junction forbidden band, a second semiconductor region having a forbidden band width greater than the width of a PN junction forbidden band, and at least one pair of electrodes affixed to each of a P conductive region and an N conductive region, the light extraction efficiency can be greatly increased by constructing the diode so that the sum of the area SA of the boundary between the first semiconductor region and the second semiconductor region and the bottom area SC of the electrode mounted on the surface of the second semiconductor region (SA + SC) is sufficiently smaller than the area S obtained by subtracting the area (SA + SC) from the total surface area of the second semiconductor region.

High voltage pn junction and semiconductive devices employing same

Abstract: A PN junction having very low concentration gradients on both sides exhibits substantially increased breakdown voltages. A PN junction extending to the surface of a semiconductive body is formed by diffusing material of a first conductivity type into material of a second conductivity type in two stages: in the first stage, the surface concentration of impurity atoms is no higher than about 1016 per cc., and is always two to four orders of magnitude less than conventional junctions. In the second stage, the area of diffusion is smaller, so as to be surrounded by the area of said first stage diffusion, but concentration and depth are at normal levels, roughly 1017 - 1020. The higher the concentration is in the second stage, the greater the concentration difference between the two stages must be. Breakdown voltages of devices employing the junction of the invention are improved: planar transistors with BVcbo = 1000 volts may be produced. Other properties of devices employing the junction of the invention are either not affected or are improved, and employment of the junction is essentially independent of other design parameters. The junction of the invention may be used in both active and passive devices, and is adapted for use in integrated circuits and for PN junction isolation. In dielectrically isolated integrated circuitry, a further improvement is achieved by diffusing into the oxide dielectric and polycrystalline matrix material in areas that will underlie leads, effectively burying the junction in these areas.

Non-volatile diode cross point memory array

Abstract: A dense memory array in which every cross point of two insulated orthogonal sets of lines define a non-volatile memory device is described. Each device utilizes voltage and storage charge to control breakdown characteristics of a PN junction. Basically, the array comprises insulated metallic word lines orthogonal to bit line diffusions in a semiconductor body. The insulation between the word lines and the bit lines has dual charge states and can store charges. Biasing of the word and bit lines causes charges to be injected into the insulation to affect the surface field of the body and thus change the breakdown voltage of the diffusion with respect to the semiconductor body. Both the read and write operations involve voltage breakdown of the PN junction between the diffused bit line and the body. During the write operation, an avalanche breakdown of the junction is caused to occur and charge carriers are injected into the overlying insulator. The charge carriers so injected remain localized in the insulator immediately above the junction and therefore do not disturb the information on adjacent bit lines. To erase, a voltage is applied to cause the injected carriers to be driven out of the insulation into the substrate. Reading consists of sensing the breakdown voltage of the selected bit.

Electron injection into SiO2 from an avalanching p-n junction

Abstract: The current injected into SiO2 as a result of avalanche breakdown of an underlying p-n junction, with doping typically used in MOSTS, has been investigated. By use of a simple model, an expression has been derived for the dependence of this current on the gate and reverse voltages; reasonable agreement with experiment is obtained.

Method of fabricating a scannable light emitting diode array

Abstract: There is disclosed a method of manufacturing a monolithic light display which comprises placing an epitaxial layer of a first conductivity type semiconductor material upon a substrate of semiconductor material having an intrinsic or semi insulating conductivity. Then channels are etched through the epitaxial layer to the semi insulating semiconductor substrate, thereby forming the epitaxial material into a plurality of parallel ribs or ridges. After coating the entire surface of the channels and the ridges with a dielectric layer, a conductive material is deposited over the substrate to fill the channels with the conductive material which may be either a metal or polycrystalline silicon doped to have sufficient conductivity. The surface of the substrate is then lapped to remove the conductive material and the dielectric material from the ridges to expose the first semiconductor material, and following diffusion of a dopant to convert the first semiconductor material to a second conductivity type material thereby forming a PN junction in each of the ridges in spaced locations therealong, suitable metallization is placed on the substrate to connect the first conductivity material to the conductive material in the channels to form column lines and metallization is placed on top a dielectric layer to connect the other conductivity material in a plurality of row lines.

Thermodynamic considerations of p-n junction capacitance

Abstract: Recently, accurate solutions for the hole and electron densities and the electric field in a p-n junction have become available By use of these solutions it is possible to calculate p-n junction capacitance more accurately The literature contains several different viewpoints on the details of the calculation of junction capacitance In this paper several formulations are briefly reviewed and a numerical comparison is given for an asymmetrical p-n step junction Space-charge capacitance and diffusion capacitance are shown to be well-defined quantities even if the depletion approximation is not valid An extension of the so-called “energetic” definition of capacitance is presented In particular, it is shown that the definition involving energy stored in the electrical field of a junction is valid only for large reverse bias The range of validity may be extended to any bias, by consideration of both chemical and electrical energy: ie, the total thermodynamic energy stored in the junction

Method of manufacturing semiconductor devices with local oxidation of silicon surface

Abstract: An improved method of manufacturing a semiconductor device employs a local oxidation process in which an oxide isolation region is formed by locally oxidizing a silicon epitaxial layer, using a nitride-oxide double layer for masking purposes, with a P + type region being formed by the diffusion of an impurity into the silicon epitaxial layer using the oxide isolation region, which has an "oxide beak", as a diffusion mask. An additional region of the same conductivity type as the P + type diffused region is provided to be contiguous to the P + type diffused region, so that a PN junction terminates at a silicon surface remote from the electrode to be connected to the P + diffused region. As a result, disadvantages caused by the oxide beak, such as the imperfect protection of the PN junction and short-circuiting between the electrode and the epitaxial layer through pin holes in the oxide beak can be eliminated.

Strip type radiation detector and method of making same

Abstract: An improved strip detector and a method for making such a detector in which a high resistivity N conduction semiconductor body has electrode strips formed thereon by diffusion which strips are formed so as to be covered by an oxide layer at the surface point of the PN junction and in which the opposite side of the semiconductor body then has a substantial amount of material etched away to form a thin semiconductor upon which strip electrodes which are perpendicular to the electrodes on the first side are then placed.

Automatic P-N junction formation during growth of a heterojunction

Abstract: A process for the preparation of a homojunction in a semiconductor substrate, e.g., a p-n junction, during growth of a heterojunction between the substrate and a second semiconductor consisting of either gallium nitride or aluminum nitride where aluminum atoms from the aluminum nitride or gallium atoms from the gallium nitride diffuse into the substrate in a region of the substrate adjacent the aluminum nitride or gallium nitride to form the homojunction.

Determination of Hole and Electron Traps from Capacitance Measurements

Abstract: A method to evaluate energy levels and densities of electron and hole traps in semiconductors from capacitance measurements on Schottky barriers and pn junction is presented. The occupation function for electrons at the deep level is derived, using Shockley-Read statistics for both forward and reverse biased junctions. The high frequency capacitance change before and after forward bias is applied is derived as a function of reverse voltage both for hole and electron traps. The experimental procedure to determine energy levels and the density of the traps is presented along with experimental results on silicon and gallium arsenide Schottky barriers and p+n junctions demonstrating the validity and limitations of the method.

A practical p‐n junction cold cathode

Abstract: A GaAsP p‐n junction negative‐electron‐affinity cold cathode is described which exhibits adequate stability and life for practical image tube applications. Emission characteristics have been studied in sealed‐off systems to determine stability, angular distribution, and uniformity.

Method of forming PN junctions by liquid phase epitaxy

Abstract: Two layers of a semiconductor material composed of three or more elements are deposited in succession by liquid phase epitaxy on a substrate. The layers may be of different conductivity types to form a PN junction therebetween. The layers are deposited from separate solutions containing the semiconductor material and a suitable dopant. During the deposition of the first layer from one of the solutions, both of the solutions are treated in the same manner so that the composition of the second layer is the same as that of the first layer at the junction between the layers.

Conductor-insulator-junction (cij) optical memory device and a memory system dependent thereon

Abstract: An optically activated (write and read) semiconductor memory employing a conductor-insulator-junction (CIJ) structure is disclosed. The layered memory structure comprises a front transparent conductive layer; insulator means containing a storage interface capable of trapping charges thereat, said insulator means being susceptible to tunneling between the storage interface and a back surface of the insulator means; semiconductor means having a front surface and a rectifying junction, said semiconductor means having an inversion stop grid means associated with the front surface thereof, and contact means for connecting external voltages to both sides of the rectifying junction for biasing the junction. The insulator means preferably comprises a relatively thick silicon nitride layer and a relatively thin silicon oxide layer, where the storage interface is the interface between the nitride and the oxide. The semiconductor means preferably comprises successive n-type and ptype regions with a pn junction therebetween. The inversion stop grid is preferably a grid of more heavily doped semiconductor of the same conductivity type as the front surface of the semiconductor. The grid divides the memory device into individual memory cells. The contact means preferably comprises an ohmic contact to the edge of the front semiconductor region and a back electrode making ohmic contact with the other semiconductor region. To write information into the memory device, a write voltage on the order of eighty volts is established between the transparent conductor and the front semiconductor region. This establishes individual inversion regions along the front surface of the semiconductor, the individual regions being isolated by the high conductivity grid. A light beam for which h 3/4 >Egap of the semiconductor is focused on the individual regions in which a charge (binary one) is to be stored. The light beam generates holeelectron pairs within the front semiconductor region. Because of the inversion region, the carriers which would be minority carriers in the first semiconductor region drift to the semiconductorinsulator interface. These charges cause a tunneling electric field to be established between the storage interface and the insulator back surface. This field induces a tunneling current which neutralizes part of the collected charge and establishes trapped storage charges at the storage interface. No significant tunneling occurs where the writing beam does not impinge. Information is read out by back biasing the pn-junction and establishing a voltage on the order of 3 volts between the transparent conductor and the front semiconductor region. The resulting electric field establishes individual inversion regions in the front semiconductor region behind those storage sites (memory cells) which do not have any significant charge stored at the storage interface. No inversion regions are established under the storage sites which store significant charge. A reading light beam having h 3/4 >Egap is scanned across the structure to read the stored data. The minority carriers generated by the light beam drift in opposite directions in accordance with the existence or nonexistence of an inversion region. Where there is an inversion region, the minority carriers diffuse to the semiconductor-insulator interface and there is a minimum pnjunction current and a minimum output current from the back electrode. Where there is no inversion region the minority carriers drift to the pn-junction and produce a maximum pnjunction current and a maximum output current from the back electrode. This system provides long term storage of data and nondestructive readout. Data is erased by applying an erase voltage of opposite polarity to the write voltage across the insulation means. The opposite polarity of the voltage causes electrons to collect at the semiconductor insulator interface and tunnel to the storage interface so that the charge stored at the storage interface is neutralized, thus erasing the stored data. This process produces block erasing. If it is desired to preserve some of the data within a memory block which is to be erased, then that data must be read out, stored, and rewritten after the memory block has been erased. In the memory system employing the CIJ device the writing beam is digitally controlled to write desired data into the memory structure. Light emitting diodes (LED''s) are the preferred light source, with Ga1-xAlxAs the preferred diode material because of its high energy output. The memory structure is preferably mounted on a rotatable disc so that a limited number of light sources can be used for writing into and reading out of a much greater number of storage cells. A 20 inch diameter disc, having memory units over 350* can store 9.24 X 1010 bits of data using the CIJ memory device.

Method of producing a high voltage PN junction

Abstract: A PN junction having very low concentration gradients on both sides exhibits substantially increased breakdown voltages. A PN junction extending to the surface of a semiconductive body is formed by diffusing material of a first conductivity type into material of a second conductivity type in two stages: in the first stage, the surface concentration of impurity atoms is no higher than about 1016 per cc., and is always two to four orders of magnitude less than conventional junctions. In the second stage, the area of diffusion is smaller, so as to be surrounded by the area of said first stage diffusion, but concentration and depth are at normal levels, roughly 1017 - 1020. The higher the concentration is in the second stage, the greater the concentration difference between the two stages must be. Breakdown voltages of devices employing the junction of the invention are improved: planar transistors with BVcbo 1000 volts may be produced. Other properties of devices employing the junction of the invention are either not affected or are improved, and employment of the junction is essentially independent of other design parameters. The junction of the invention may be used in both active and passive devices, and is adapted for use in integrated circuits and for PN junction isolation. In dielectrically isolated integrated circuitry, a further improvement is achieved by diffusing into the oxide dielectric and polycrystalline matrix material in areas that will underlie leads, effectively burying the junction in these areas.

Analytical approximations for an abrupt pn junction under high-level conditions

Abstract: A simple model is proposed which gives a complete description of the potential and carrier concentration distributions across the space charge region of an abrupt p + − n or p + − p junction where the lightly doped side of the junction is under high-level conditions. The major assumption of the model is that on the lightly doped side of the junction the contribution of the ionized impurities to the space charge is negligible. The predictions of the model are found to agree closely with the ‘exact’ numerical solutions for a p + − p junction, generally more so than those of another model recently proposed by Cornu. Some possible applications of the model are proposed.

Field effect transistor having a pair of gate regions

Abstract: A semiconductor device includes a semiconductor substrate of one conductivity type, two electrodes formed on the substrate, a first gate region formed in the substrate and having an opposite conducitivity to the substrate, and a second gate region formed in the first gate region of the opposite conductivity type of said first region to form a PN junction therebetween. When a control signal is applied to the second gate region and the PN junction is reversely biased, an electric charge is stored within the first gate region.

Semiconductor target with integral beam shield

Abstract: A radiation resistance PN junction diode with a radiation shield which is attached to the semiconductor device and extends over, but is separated from, portions of the device which it is desired to have shielded from radiation. The purpose of the shield is to provide a radiation resistant semiconductor target for use in planar electron bombarded semiconductor devices, electron beam recorders, and other devices requiring periodic or continuous electron beam or other low energy radiation monitoring. In accordance with a preferred method of the invention, the electron beam shield is fabricated simultaneously on each of a plurality of PN junction diodes in an array on a semiconductor wafer.

A model of the p—n junction with exponential doping profile†

Abstract: The exponential p-n junction shows some peculiarities, which make its theoretical study interesting. In this paper some characteristics of the transition layer of such a junction are analysed, taking into account the mobile carriers in this region. Following a method introduced by Sab, the Poisson-Boltzmann equation is linearized using a parameter α, which is a measure of the relative importance of the fixed, ionized impurity space charge compared with the mobile carrier charge in the transition layer of the p-n junction. The width of the transition layer, on the left and on the right of the junction, the built-in voltage, the total potential difference across the transition region and the total capacitance are derived. The d.c. theory of the junction capacitance is compared with experimental data obtained on implanted silicon junctions : ft satisfactory agreement is found.

A technique for the investigation of deep-level states in diffused p—N junction devices: Application to GaAs electroluminescent diodes

Abstract: Analytical equations describing the high-frequency (1 MHz) capacitance-voltage ( C-V ) characteristics have been derived for diffused p-n junction diodes, including the effect of deep-level states within the bandgap. It was found that the C-3versus V curve becomes nonlinear when the density of the deep-level states is large. From the derived C-V equation the density of the deep-level states may be calculated from the slope of the C^{3}V versus C(V- V_{2})/V^{2} curve, where V 2 is related to the energy level of the deep states. The value of V 2 may be determined from the recombination current versus temperature measurements at small bias. The theory has been applied to characterize the dominant deep-level recombination centers in Zn-diffused GaAs light-emitting diodes. The measured deep levels are within 0.2 eV of the midgap energy and the density of these centers is of the order of 1016cm-3.

Semiconductor vidicon and process for fabricating same

Abstract: Disclosed is a semiconductor vidicon target structure and process for fabricating same wherein ohmic contact is made to active PN junction image sensing areas of the structure by means of a novel insulating interlayer through which a large plurality of highly packed metal pin connections extend. A very high packing density for these pin connections is achieved by the use of a selective anisotropic etch-out, metal backfill and lap or etch back process on a single crystal insulating wafer to obtain this thin interlayer. This interlayer eliminates the necessity for selective shielding of the vidicon semiconductor target structure with a dielectric coating or the like.

Influence of recombination in p-n junction space-charge region on photocurrent under parallel illumination

Abstract: (1973). Influence of recombination in p-n junction space-charge region on photocurrent under parallel illumination. International Journal of Electronics: Vol. 35, No. 2, pp. 277-280.

A solid state switch using an improved junction field effect transistor

Abstract: The transistor is especially useful for high frequency switching applications. A conductive path between ohmic contacts will pass high frequency signals with very little impedance. The conductive path is comprised of a doped semiconductor layer of one conductivity type to which ohmic contacts are attached. The substrate of the device which underlies the layer is heavily doped with deep impurities of opposite conductivity type so that it has a high resistivity. The high resistivity of the substrate isolates the driving voltage used to switch the device from the signal passed between the ohmic contacts. The device can be turned "OFF" by reverse biasing the PN junction formed between the substrate and the layer. This is accomplished by imposing a driver voltage between one of the ohmic contacts and a metallic contact connected to the substrate.

Method of making a PN junction device by metal dot alloying and recrystallization

Abstract: A method of making a PN junction device comprising the steps of alloying a metal dot to a semiconductor wafer so as to provide a recrystallization portion, extending the recrystallization portion through the semiconductor wafer, and then providing a semiconductor material to one surface of the semiconductor wafer so as to form a PN junction.

Semiconductor arrangement with current stabilizing resistance

Abstract: A semiconductor arrangement comprises two regions of different types of conductivity in a semiconductor body, one of the regions forming a pn junction which extends to a surface of the semiconductor body on which an insulating layer is provided, a ohmic contact on this said latter region only along its entire edge and a resistance between the ohmic contact and a current feed contact for said latter region

High speed, high power plasma thyristor circuit

Abstract: A plasma thyristor circuit is provided for generating high power, ultra-short duration electrical signals. A silicon semiconductor body has first, second and third impurity regions therein with a PN junction formed at the transition between the first and second or the second and third impurity regions. The second impurity region has an impurity concentration of less than about 5 × 1014 atoms/cm3, and a width of greater than about 80 microns. The ratio of the punch-through voltage of the second impurity region to the reverse breakdown voltage of the PN junction is between 0.3 and 0.7. Power sources apply both a reverse bias voltage across the body greater than said punch-through voltage and less than said reverse breakdown voltage, and a current to the body having a density greater than the saturation current density of the second impurity region.