Showing papers on "p–n junction published in 1980"

Theory of grain-boundary and intragrain recombination currents in polysilicon p-n-junction solar cells

Abstract: The physics controlling recombination in polysilicon p-n-junction solar cells is described. Analytic models characterizing this recombination, whose parameters can be related directly to experiment, are developed. The analysis reveals that, in general, the description of intragrain and grain-boundary recombination in a polysilicon solar cell requires the solution of a nonlinear three-dimensional boundary-value problem. Cases of practical interest for which this problem is tractable are discussed. The analysis predicts an \exp (qV/2kT) dependence (the reciprocal slope factor is exactly two) for carrier recombination at a grain boundary within the junction space-charge region of a nonilluminated, forward-biased cell. This result, and others of the analysis, are consistent with preliminary experimental data.

Admittance spectroscopy: A powerful characterization technique for semiconductor crystals—Application to ZnTe

Abstract: The admittance spectroscopy technique is shown to be a very convenient tool for analyzing majority carrier traps: energy level, capture cross section and concentrations are easily obtained without complicated mathematical treatment. The series resistance in the material underlying the Schottky or pn junction is also detected when the free carriers are freezing out. It allows to get the shallowest level energy and its compensation ratio. The method has been applied to ZnTe material analysis and the effect on the admittance of six different acceptors is demonstrated. When comparing the electrically determined ionization energy of a given impurity with its optical value the former appears as systematically lower but most of the difference can be ascribed to Poole Frenkel or impurity concentration effects.

Diffusion length determination in p‐n junction diodes and solar cells

Abstract: An experimental technique for determining the minority carrier diffusion length in the base region of Si p‐n junction diodes and solar cells is described. The procedure is to operate the device in the photoconductive mode and to measure its photoresponse in the wavelength region near the energy gap. The ratio of incident light intensity to photocurrent is a linear function of reciprocal absorption coefficient for each wavelength; the slope of the set of points directly yields the diffusion length. In addition, a nonlinear least‐squares analysis is also used to determine the diffusion length.

InGaAs avalanche photodiode with InP p-n junction

Abstract: A new InGaAs avalanche photodiode structure that has an InGaAs light absorption region and InP avalanche multiplying region is proposed. A dark-current density of 2.2 × 10-3 A/cm2 at 90% of breakdown voltage and a multiplication factor of 45 were obtained for the new structure diode fabricated from a liquid-phase epitaxially grown wafer.

Blue-Emitting Diodes of 6H-SiC Prepared by Chemical Vapor Deposition

Abstract: Silicon carbide (SiC) blue-light-emitting diodes with an external quantum efficiency of 2×10-5 photons/electron were prepared by the chemical vapor deposition method. Epitaxial growth of 6H-SiC has been carried out at 1800°C on a 6H-SiC substrate using the SiCl4-C3H8-H2 system. Epitaxial layers of the n and p types with appropriate carrier concentrations were obtained by doping N from NH3 and Al from AlCl3, respectively. A pn junction was prepared in one growth run by a double epitaxial process. The peak wavelength of the electroluminescence spectrum was 495 nm.

Use of silicide to bridge unwanted polycrystalline silicon P-N junction

Abstract: Polysilicon lines are utilized for interconnecting the various elements of CMOS devices. The polysilicon lines are doped with whatever dopant conveniently suits the processing step, to form an undesired PN junction. The junction is electrically short-circuited, preferably by a polysilicided section extending across the junction.

Electrical contact connected with a semiconductor region which is short circuited with the substrate through said region

Abstract: Disclosed herein is an improvement for the electrode structure of the MIS type semiconductor integrated circuit, in which the ohmic contact with the Si substrate is formed on the top of the semiconductor chip. The electrodes which consist of an upper Al layer and a lower polycrystalline Si layer are used for a drain electrode and a source electrode. These electrodes should be isolated from the substrate by the underlying PN junction. Another electrode, for connecting to the substrate consists of an Al layer directly in contact with the underlying N type region and which is short circuited with the substrate through the N type region due to the alloy formation between the Al and the substrate material. An MIS type semiconductor device with a grounded substrate or with a back gate bias is obtained in a simple structure by the improved source and drain electrode structure.

Recent developments in amorphous silicon p-n junction devices

Abstract: Amorphous Si p-n junctions with various doping profiles have been prepared by the glow discharge process to investigate the effect of the barrier profile on the electrical properties of the diodes. The highest current densities, up to 40A/cm 2 , are obtained with n + -ν-p + structures. Under AM-I illumination photovoltaic p + -i-n + cells generate open circuit voltages of 0.7V and short-circuit currents up to 10mA/cm 2 , corresponding to efficiencies between 3 and 4%. The diode quality factors have also been investigated.

Efficiency calculations for thin-film polycrystalline semiconductor p-n junction solar cells

Abstract: Numerical calculations have been made of the effect of grain size on the short-circuit current and the AM1 efficiency of polycrystalline thin-film GaAs and InP (2 µm thick) and silicon (25 µm thick) p-n junction solar cells. Junction solar cells are seen to be more efficient than Schottky-barrier cells, due to the higher dark current associated with Schottky diodes. GaAs shows the highest efficiency and both GaAs and InP attain 90 percent of their maximum efficiencies at a grain size of 10 µm, while silicon requires grain sizes of 200 µm to attain 90 percent of maximum efficiency. However, the deleterious effect of poor lifetimes and mobilities is less for silicon polycrystalline cells than for the direct-bandgap devices.

Surface passivation techniques for InP and InGaAsP p-n junction structures

Abstract: Surface passivation techniques developed for InP and InGaAsP avalanche photodiodes have resulted in reductions of dark current as large as four orders of magnitude, to values as low as 1.6 × 10-6A/cm2at 0.9V b . Devices consisting entirely of InP have been passivated with plasma-deposited Si 3 N 4 , and those with a InGaAsP layer but with the p-n junction in InP have been passivated with polyimide. Neither of these techniques successfully reduces dark currents in devices with the p-n junction in the InGaAsP, but a film of photoresist sprayed with SF 6 as the propellant has given excellent results.

Method of making a zener diode utilizing gas-phase epitaxial deposition

Abstract: A method of making a Zener diode having a Zener voltage in the range of 2.4-3.3 volts. The PN junction is preferably formed by selective epitaxial deposition of P-type silicon on a previously oxidized N-type silicon wafer in an opened region where the oxide has been etched away. The N-type wafer may be a uniform silicon wafer with resistivity in the range of 0.004 to 0.006 Ω-cm or a low resistivity N-type wafer having a 5-20 μm thick N-type silicon epitaxial layer with a resistivity in a range of 0.004-0.006 Ω-cm. The selectively deposited P-type layer may have a resistivity of 0.001-0.003 Ω-cm and a thickness of 1.5-3.0 μm. The P-type layer is grown in a gas phase epitaxial reactor by etching the N-type wafer at a first temperature and then depositing heavily-doped silicon at a second, lower temperature.

Process for fabricating solar cells and the product produced thereby

Abstract: An electrically conductive, anti-reflective coating is formed on a base layer of prepared silicon in such a manner as to form a good ohmic contact therewith. If doped, the coating can serve as an impurity source during a following diffusion step, in which a PN junction is formed in the silicon. Undoped coatings may be used when the PN junction has previously been formed in the silicon. Thick film electrical contacts are then formed by screen printing on the top surface of the anti-reflective coating and then fired at high temperature, i.e. 500°-1000° C. The material comprising the coating is such that it acts as a barrier to the diffusion of the metal forming the electrical contacts into the silicon base layer during the firing of the thick film contacts. Since the coating is electrically conductive, a conductive path between the contacts and the silicon is established.

Heterojunction semiconductor laser fabrication utilizing laser radiation

Abstract: A stripe geometry is fabricated in a laser-diode structure having a plurality of epitaxial layers, including in tandem an undoped active semiconductor layer (3), a p-doped semiconductor layer (4), a moderately n-doped semiconductor layer (5) and a heavily p + -doped layer (6) by focusing laser radiation on the n-doped semiconductor layer (5). The laser radiation is chosen to have a wavelength which passes through the p + -doped layer (6) without absorption. When the laser radiation is absorbed in the n-doped layer, heat is generated which causes diffusion of p-dopant from the two adjacent layers to convert the exposed region to p-type. As the laser beam is scanned, a stripe having a forward pn junction for laser action is formed.

Photoelectronic conversion semiconductor device

Abstract: PURPOSE:To obtain a device with a good photoelectronic conversion efficiency at a low cost and promote its mass production by achieving the continuation of the energy band width of the PN junction on a non-single crystal semiconductor layer grown on a substrate by a CVD method. CONSTITUTION:A insulated carrier of Al2O3 having the metalic film of W and others placed on the surface or a metalic conductor of Ti and others is used for a substrate 21 and a non-single semiconductor layer 22 is formed by a CVD method or a glow discharge on the substrate 21. In this case, Si or Ge is used as a reactive gas to form the layer 22, the impurity for defining either the P-type composition or the N-type one is composed of Al, As and others and Si, C, N2, O2, In, Sb and others are used to establish the continuation of the energy band width. Successively, a reflection preventing film 23 is formed over the full surface, a plurality of opposite electrodes 25 are attached, and the light 27 is irradiated to a SiO2 protective film 23 covered over the full surface. By such a method, a recombination center is reduced to keep the life time of a carrier for the non-single crystal semiconductor longer.

Avalanche photo diode

Abstract: An avalanche photo diode in which the guard ring portion and the front of the pn junction of the light receiving portion are formed at the same depth from the surface of an InP layer, so that the guard ring performs its desired function.

InGaAsP/InGaAs heterojunction p-i-n detectors with low dark current and small capacitance for 1.3-1.6 μm fibre optic systems

Abstract: A new long wavelength p-i-n photodetector, consisting of an In0.53 Ga0.47 As absorbing layer and an adjacent InGaAsP p-n junction is demonstrated. These diodes exhibit dark currents as low as 0.2 nA and a capacitance < 0.5 pF at - 10 V for a device area of 1.3 × 10-4 cm2. The external quantum efficiency is - 60% at - = 1.3 μm for front illumination. A systematic study of the background doping of the quaternary layers using different InP sources is also reported.

Photodiode having an InGaAs layer with an adjacent InGaAsP p-n junction

Abstract: A photodetector useful between 1.0 and 1.6 microns and having an InGaAs layer with an adjacent InGaAsP p-n junction disposed on the InGaAs layer is described.

Process for producing a semiconductor device

Abstract: In a process for producing a semiconductor device, particularly an MIS structure semiconductor device, an electrode, which is in ohmic contact with the semiconductor substrate, is usually formed on the surface which is opposite to the surface having MIS FETs. However, in a recently developed process, the electrode mentioned above is formed on the semiconductor substrate surface on which the MIS FETs are formed, and the electrode is in ohmic contact with the substrate through a short-circuit of a PN junction formed on such semiconductor substrate surface. However, a so formed electrode is liable to break. In the present invention, wherein a masking layer covers the substrate-contact region during the production of the MIS FETs, the electrode mentioned above is in an ohmic contact with the electrode not through the PN junction and the problem of breaking occurs seldom.

Compact MOSFET device with reduced plurality of wire contacts

Abstract: A semiconductor device and a method for manufacturing the same are disclosed wherein an insulating thin film is formed on the surface of a semiconductor substrate, a gate electrode region of conductivity type different from that of the semiconductor substrate is selectively formed within the substrate and contiguous with the surface of the substrate, and source and drain regions are formed at the upper portion of the insulating thin film so that the voltage applied to the gate electrode region is below the reverse-breakdown voltage across a PN junction between the semiconductor substrate and the gate electrode region and determines the electrical conductivity of the source and drain regions.

High breakdown voltage semiconductor device

Abstract: A novel structure of a high breakdown voltage semiconductor device has a pair of major surfaces on which a pair of main electrodes are formed and a PN junction formed between the pair of major surfaces with a side surface to which the PN junction is exposed being covered with a passivation material. An auxiliary electrode of a conductive member is provided, which is disposed externally of the peripheral edge of the major surface of the semiconductor substrate, and which contacts to the passivation material and is electrically connected to the main electrode. When a voltage for reverse biasing the PN junction is applied between the pair of main electrodes, ions in the passivation material are collected by an electric field established in the passivation material so that the deterioration of the breakdown on the surface of the semiconductor substrate is prevented.

Field controlled high value resistor with guard band

Abstract: A high resistance region is formed by implanting ions of an impurity of one conductivity type at a low concentration into a surface of a substrate of a semiconductivity type of the opposite conductivity. An electroconductive film is formed on the high resistance region with an electric insulating film therebetween for applying a reverse bias potential to a PN junction between the semiconductor substrate and the high resistance region.

Dual-wavelength light-emitting diode

Abstract: A dual-wavelength light-emitting diode (10) is disclosed wherein at least two quaternary layers (102 and 104) are epitaxially grown on indium phosphide substrate (100) and a top indium phosphide layer (105) of the opposite conductivity type is grown to establish a junction (121) in the topmost quaternary layer. An isolation channel (106) cuts through the epitaxial layers and divides the device into two separate regions. A dopant is diffused into one of the regions in order to establish a pn junction (122) in the bottom quaternary layer. Independent electrical contacts (107 and 108) bonded to the top indium phosphide layer in each of the regions establish an electrical connection to pn junctions in each of the two separate regions. The device can be effectively heat sinked by mounting the epitaxial layer side of the substrate to a beryllium oxide heat sink (200) onto which gold bonding pads (201 and 202) have been plated.

Light detecting photodiode-MIS transistor device

Abstract: A light detector device comprises at least one pair made up of a light sensitive photodiode and a light signal reading MIS transistor switch The pair is formed on an insulating substrate such as sapphire The source region of the MIS transistor switch is contiguous with a photosensitive pn junction of the photodiode The source, drain and channel regions of the MIS transistor switch reach the insulating substrate, thereby reducing the area of pn junction of the MIS transistor and hence the junction capacitance so that high signal output is available from the photodiode with high S/N ratio

Method of making memory cell by selective oxidation of polysilicon

Abstract: A dynamic read/write memory cell of the one transistor N-channel silicon gate type is made by an improved process employing selective oxidation of polysilicon using PN junction capacitors. A relatively flat surface results from the process, which is favorable to patterning small geometries. The PN junction storage capacitors have improved alpha particle protection. Metal-to-polysilicon gate contacts are made at silicide areas over polysilicon gates; the silicide lowers resistance of the poly elements.

Process for producing an electrode on a semiconductor device

Abstract: "' In a process for producing a semiconductor device, particularly an MIS structure semiconductor device, an electrode, which is in ohmic contact with the semiconductor substrate, is usually formed on the surface which is opposite to the surface having MIS FETs However, in a recently developed process, the electrode mentioned above is formed on the semiconductor substrate surface on which the MIS PETs are formed, and the electrode is in ohmic contact with the substrate through a short-circuit of a PN junction formed on such semiconductor substrate surface However, a so formed electrode is liable to break In the present invention, wherein a masking layer covers the substrate-contact region during the production of the MIS FETs, the electrode mentioned above is in an ohmic contact with the electrode not through the PN junction and the problem of breaking occurs seldom

Semiconductor memory device

Abstract: PURPOSE:To reduce the power consumption of static type memory device and achieve high integration by means of a very simple structure. CONSTITUTION:An n -layers 11 and 12 on the surface of p -type semiconductor substrate 10 are made into a drain and a source. Electrode 14 on surface insulating film 13 between these is made into a gate, and thereby switching element 2 is formed. p Epitaxial layer 15 and p -layer 16 are laminated on n-layer 12, and thereby diode 1 is formed. The control output is produced by connecting p -layer 16 and drain 11. n -Layer 12, together with substrate 10, is grounded by grounded electrode 17. In this structure, when FET2 as a switching element is turned off, the barrier voltage of the pn junction is outputted to the anode terminal of diode 1; when FET2 is turned on, the potential difference between both terminals of diode 1 becomes zero, and the output is zero. Consequently, it is possible to store binary information. Further, there is no need for information maintaining current, so that the power consumption is reduced and the occupied area can be made smaller than the conventional device.

Manufacture of semiconductor device

Abstract: PURPOSE:To obtain a good ohmic contact electrode by a method wherein the unnecessary junction produced by the intrusion of P into the window at the time when the open window part of a PSG film is softened by melting is short-circuited by controlling the alloying with the electrode metal. CONSTITUTION:Gate oxide films 22a, 22b, gate electrodes 23a, 23b and source and drain layers 24a-25b are provided on n-type Si substrate 20. p-Layer 26 is provided with respect to the n channel element. This is covered with PSG layer 27 and is selectively opened. Then, softening by melting is operated and thereby wire breakage is prevented. At this time, p enters the window and thereby n layer 29 is formed. Next, P-added poly-Si 30 is selectively formed on the n channel element, and thereby the alloying of Al and Si is prevented, and Al electrode 31 is formed. When poly-Si layer 30 is removed by using electrode 31 as a mask and heat treatment is operated, the alloying of Al and Si in the p channel operates and the pn junction disappears, and at the same time, alloy junction 32 is formed in layers 24a, 24b and a good ohmic contact is formed. Consequently, the depth of the alloy can be controlled by the amount of Si additive in Al.