Showing papers on "p–n junction published in 1983"

Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing deposition of amorphous semiconductor layer

Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor impurity is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction laterally bounded by the island's side boundaries. A highly resistive amorphous semiconductive layer (58) which is irreversibly switchable to a low resistive state is deposited above the region in such a manner as to be electrically coupled to the region. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.

Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing ion implantation

Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction with adjacent semiconductive material of the island. Ions are implanted to convert a surface layer (60) of the region into a highly resistive amorphous form which is irreversibly switchable to a low resistance state. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.

Electro-optical SLS devices for operating at new wavelength ranges

Abstract: An intrinsic semiconductor electro-optical device includes a p-n junction intrinsically responsive, when cooled, to electromagnetic radiation in the wavelength range of 8-12 um. The junction consists of a strained-layer superlattice of alternating layers of two different III-V semiconductors having mismatched lattice constants when in bulk form. A first set of layers is either InAs1-x Sbx (where x is aobut 0.5 to 0.7) or In1-x Gax As1-y Sby (where x and y are chosen such that the bulk bandgap of the resulting layer is about the same as the minimum bandgap in the In1-x Gax As1-y Sby family). The second set of layers has a lattice constant larger than the lattice constant of the layers in the first set.

Heterojunction semiconductor device

Abstract: A semiconductor device is described for sensing radiant energy incorporating a pn junction formed by two layers of materials each having a different energy band gap to form a heterojunction diode and wherein the layer having the greatest energy band gap fully covers the boundaries or perimeter of the layer having a lesser energy band gap to reduce surface leakage current. Further, a semiconductor device is described for sensing radiant energy incorporating a pn junction formed by two layers of materials each having a different energy band gap to form a heterojunction diode wherein the layer having the greatest energy band gap has spaced-apart P regions to form the anode of the heterojunction diode whereby the heterojunction diode is buried below the surface of the layer having the greatest energy band gap. The invention reduces the problem of surface and bulk leakage across heterojunction diodes.

Peripheral photoresponse of a p–n junction

Abstract: A quantitative theory is presented for the enhanced photoresponse of p–n junctions that arises from the lateral diffusion of photogenerated carriers. This mechanism leads to a photoactive area for a photodiode that may be much larger than its p–n junction area. The main theory pertains to the geometry that arises with mesa diodes, the results for which are also applicable to planar junctions that are shallow when compared with the minority‐carrier diffusion length. The solution for infinitely deep planar junctions is obtained by separate analysis. The magnitude of the peripheral photoresponse is sensitive to geometric and physical factors such as semiconductor thickness, surface recombination, optical absorption length, and competition for photogenerated carriers by adjacent photodiodes. The dependence of the response upon all of these features is presented.

Selective Si and Be implantation in GaAs using a 100 kV mass‐separating focused ion beam system with an Au–Si–Be liquid metal ion source

Abstract: Submicron Si and Be ion beams have been implanted into GaAs using a 100 kV maskless ion implantation system with a liquid metal ion source which is capable of emitting double ion species (Si++ and Be++). Both ion beams are implanted at 160 keV with the dose of 1013 to 1014 cm−2. The feasibility of the focusing column was demonstrated by forming the submicron width of line patterns of alternative Si and Be doping in GaAs including a pn junction array. The linewidth of the ion implanted area has been evaluated by SEM, after selective etching of the annealed sample. It has been found that high dose implantation results in considerable lateral impurity spread of more than 1 μm even with the focused ion beams with a diameter of 0.1 μm. However, submicron width implantation turns out to be possible with relatively low doses or with shallow dopings.

Organic P-N Junction Solar Cells

Abstract: A number of solid state organic solar cells have been prepared and tested in simulated sunlight. Photovoltaic effects were consistent with the formation of a rectifying junction at the interface between a triphenylmethane dye (n-type) and a merocyanine dye (p-type). The most efficient device consisted of a sandwich of thin layers of indium-tin oxide/malachite green/a benzothiazole-rhodanine merocyanine/Au on Pyrex. Exposure of the cell to chlorine vapour in the absence of air improved the sunlight efficiency to 0.12%. Investigations of the photocurrent action spectrum, rectification and capacitance have given mechanistic information on the photovoltaic energy conversion processes.

Formation of Shallow p+n Junction by Low Temperature Annealing

Abstract: The formation of shallow p+n junction with B+ implantation in silicon was investigated A rapid diffusion of implanted borons was observed in the initial stage of the annealing for activation (in 10 sec), and it was independent of the annealing temperature (600~1000°C) and determined the shallower limit of B+ implanted p+n junction depth, 025 and 04 microns for the B+ acceleration of 10 and 20 KV, respectively Appropriate Si+ implantation subsequent to B+ implantation enabled the annealing temperature reduction to about 600°C with activation (sheet resistivity) and crystallinity (junction quality) comparable to those of high temperature annealing (900~1000°C) It is suggested that the rapid diffusion and the reduction in the annealing temperature resulted from the excess configuration entropy in the ion implanted layer which corresponded to high temperature situation in effect

Reverse-breakdown PN junction devices

Abstract: A semiconductor device has a PN junction between first and second regions 1, 2 and which includes, adjacent to the junction and in the first region 1 which is of lower impurity concentration than the second region 2, a buried region 3, 3A, 6 of the same conductivity type as the first region and of higher impurity concentration than the first region. The effect of the buried region is such that, in the intended operation of the device with reverse-breakdown of the junction, the breakdown occurs through the buried region in the device bulk rather than where the junction meets the surface of the first region.

Method of fabricating a semiconductor pn junction

Abstract: A method of forming a pn junction with a Group IIB-VIB compound semiconductor containing Zn is disclosed, the method including preparing an n type semiconductor region either locally or entirely in a Group IIB-VIB compound semiconductor crystal obtained by relying on a crystal growth method in liquid phase using a temperature difference technique, and subjecting this crystal to a thermal annealing in a Zn solution or in a Zn atmosphere to produce an n type region. Crystal growth is conducted while controlling the vapor pressure of the constituent Group IVB element to produce a p type region. A combination of all these steps gives a more stable pn junction.

Semiconductor integrated circuit device

Abstract: PURPOSE:To form a thin single crystal semiconductor region by providing a high concentration impurity layer of which bottom is partly thin within an isolation region in a dielectric separation type semiconductor IC. CONSTITUTION:A single crystal semiconductor region is composed of a single crystal layer 1 having comparatively low impurity concentration and a high impurity concentration layer of the same conductivity type as the layer 1, and it is insulatingly separated from a semiconductor substrate 4 because the bottom and side surfaces are surrounded by a dielectric isolation film 3. In this case, a high impurity concentration layer is formed in two kinds of thicknesses. The high impurity concentration layer 2a of them is a thin high concentration impurity layer formed in the vicinity of region where the depletion layer extends from the blocked PN junction of the bottom part of single crystal semiconductor region. The high concentration impurity layer 2b is thicker than the layer 2a. Thereby, the single crystal semiconductor region can be formed as shallow as a difference of the layers 2a and 2b, and a device can be manufactured as much easier.

Light-emitting diode suitable as a pressure sensor

Abstract: A light-emitting diode comprises III-V semiconductor material having a pn junction as its light-active zone from which luminescent radiation is emitted, the radiation having a pressure-dependent characteristic. The diode is characterized in that, for the purpose of pressure-dependent brightness of the light radiation, the composition of the light-active zone at the pn junction comprises a semiconductor material which has a composition which corresponds to a position close to the transition from a direct energy gap to an indirect energy gap and at which a change of the composition would result in a significant change in the brightness of the emission. The invention is particularly useful for potential-free measurement of pressure forces.

Method for making self-aligned lateral bipolar transistors

Abstract: A semiconductor body having surface regions thereof isolated from other such regions by a pattern of dielectric isolation is provided. At least two narrow widths PN junction regions are located within at least one of the surface regions. Each PN junction has a width dimension substantially that of its electrical contact. Substantially vertical conformal conductive layers electrically ohmic contact each of the PN junction regions. The PN junction regions are the emitter and collector regions for a lateral bipolar transistor. A base PN junction region of an opposite conductivity is located between and contiguous to the emitter and the collector junctions. Substantially horizontal conductive layers are in electrical contact with an edge of each of the vertical conductive layers and separated from the surface regions by a first electrical insulating layer. A second insulating layer covers the conformal conductive layers. The horizontal conductive layer is patterned so as to have electrically separated conductive lines from one another. A third electrical insulating layer is located over the patterned horizontal conductive layers. An electrical contact is made to each of the horizontal conductive layers through an opening in the third electrical insulating layer which effectively makes contacts to the emitter and collector regions through the patterned horizontal conductive layers and the vertical conductive layers. An ohmic contact is made to the base region which is separated from the vertical conductive layers by the second insulating layer.

Method and structure for passivating a PN junction

Abstract: A technique for passivating a PN junction adjacent a surface of a semiconductor substrate comprises coating the area of the surface adjacent the PN junction with a layer of hydrogenated amorphous silicon containing between about 5 and about 50 atomic percent of hydrogen.

Manufacturing method for a planar photodiode with hetero-structure

Abstract: In a method for manufacturing an avalanche photodiode with an epitaxial layer sequence on a carrier body, the carrier body is not the substrate for an epitaxy of the photodiode. One of the epitaxial layers is employed as a selectively etchable mask for generating a pn junction of the diode.

Insulating gate type semiconductor device

Abstract: PURPOSE:To obtain a vertical MOSFET advantageous for preventing electrostatic breakdown by electrically connecting an internal impurity introducing layer to a source and integrally connecting an external impurity introducing layer to a semiconductor gate. CONSTITUTION:Since structure in which an internal N diffusion region 7c surrounded by a looped PN junction is connected to a source electrode and an external N diffusion region 7b is connected to a gate electrode is formed in a back-to-back protective diode using a polycrystal Si layer, the protective diode can be formed at the arbitrary position of the substrate of the MOSFET, size and shape can freely be selected as compared to the case when a slender NPN junction is shaped along the periphery of the substrate as seen in the conventional devices, and a layout is also extremely easy. Electrostatic breakdown can effectively be prevented by forming such a protective diode in parallel between the gate and the source.

Improvements in or relating to semiconductor devices, and methods of making same

Abstract: A semiconductor (FET) device includes a channel region (16) of a predetermined doping concentration and thickness so as to form an active pn junction between the gate contact and source region of the semiconductor device. The pn junction creates an active intrinsic junction FET (JFET) which may be pinched off in the operating region of the FET device. The resultant combination is a cascode FET-JFET amplifier arrangement, which comprises operating characteristics of longer gate length devices than the FET device alone, maintaining high saturation output resistance and high d.c. voltage gain.

ZnSe green light emitting diode

Abstract: A green color light emitting ZnSe diode having a pn junction is fabricated by the use of a ZnSe crystal having a good crystal perfection and being obtained by a solution growth method relying on the temperature difference technique using a solvent containing at least Te and Se and using atoms of at least one kind of impurity selected from Group Ib elements of the Periodic Table as a principal impurity for producing a p type region in the crystal.

Theory of the triangular-barrier switch

Abstract: The recently observed, current controlled, negative resistance behaviour in a novel bulk GaAs structure is analysed using the basic charge neutrality and carrier transport equations. The structure is composed of a triangular barrier (TB) diode (formed by creating a plane of ionised impurities in the Crystal bulk using MBE) in the immediate vicinity of a p–n junction in the same crystal. The switching phenomena in this ‘TB switch’ is attributed to a regenerative feedback interaction between the p–n junction and the TB diode. Simple closed-form expressions for the main device parameters are derived.

Preparation of compound semiconductor p-n junction

Abstract: PURPOSE:To obtain statisfactory photo-electric conversion coefficient by implanting ion of any one of Zn, Cd, C, Si, Ge in the equal amount to the GaAs, similar III-V system compound semiconductor or the N layer of mixed crystal of these, forming almost the same concentration distribution and by forming the P layer through the annealing. CONSTITUTION:The N layer 3 is epitaxially formed in the concentration of about 10 /cm on the N TYPE GaAS substrate 1 through the buffer layer 2, and Si of 10 /cm and Zn of 2X10 /cm are implanted with respective energies of 140KeV, 200KeV respectively. The concentration distribution obtained should have the maximal value of Si of 10 /cm for the depth of 0.2mum and that of Zn of 2X10 /cm for the depth of 0.1mum. Distribution of Si hardly changes even after the activation processing for 30min under a temperature of 650 deg.C, but Zn diffusers again during such process. Accordingly, the maximum concentration moves to the depth of about 0.2mum and the P layer 14 is formed in the depth of 0.3mum. According to this structure, the free hole concentration can be improved as much as one digit, the annealing temperature can be lowered, lattice defect can be reduced, an apparatus providing excellent photo-electric conversion coefficient can be obtained and the shape of p-n junction interface can be controlled accurately with good reproducibility.

Manufacturing method for semiconductor device

Abstract: PURPOSE:To obtain a highly integrated, shallow diffused layer by a method wherein a well region on a semiconductor substrate and a region on the substrate lacking such are divided by a field oxide film and the surfaces of the respective regions are provided with gate electrodes across gate oxide films, and the gate oxide films act as masks for the formation of channel regions, and the channel regions are formed by diffusion. CONSTITUTION:A P type well region 202 is diffusedly formed in an N type semiconductor substrate 201 and the resultant PN junction exposed on the surface of the substrate 201 and a part of the portion lacking a PN junction are respectively covered with thick field oxide films 203. Thin gate oxide films 204 are provided to respectively cover the surfaces surrounded by the films 203, and the central portion is provided with a polycrystalline Si made gate electrode 205. They are alternately covered with a mask 206 exemplifiedly of resist for the application of an impurity for the formation of a P channel and an N channel 207. After this, only the superficial layer of the electrode 205 is oxidated for the formation of an oxide film 208 and the entire surface including the film 208 is covered with an oxide film 210. A window is provided and each channel 207 is provided with an Al electrode 212 across a polycrystalline Si layer 209.

The variation of the P/N junction position in GaAs/GaAlAs double heterostructures grown by low pressure mo vpe.

Abstract: A modified contact resistance profiler has been used to determine the dopinq type of the active layer in GaAs/Ga AlAs double heterostructures qrown by low pressure metalorganic vanour phase enitaxy (LP-MO VPE). It was found that under normal growth conditions. The p/n junction is located inside the “p-tyne” Ga0.65Al0.35As confinement layer. SIMS data show that this displacement of the p/n junction is due to electrical compensation of the zinc doping.

Photodiode and photodetector comprising an integrated series of photodiodes

Abstract: A photodiode consists of an undoped light-absorbing region contiguous with one doped region of a pair of doped regions forming a quantum mechanical tunnelling pn junction having a thickness of the order of the mean free path of an electron. A number of the photodiodes are integrated in series with the light absorbing regions being progressively thicker with distance from an incident light receiving surface. For maximum effectiveness with monochromatic light, the thickness and doping of the regions are tailored to produce similar quantities of carriers from the light. A nine section GaAs structure with 50 A thick n and p tunnelling junction regions has a 90% quantum efficiency and delivers a 5 volt output with a 0.35 picosecond transit time.

Formation of compound semiconductor p-n junction

Abstract: PURPOSE:To easily control the distribution shape of impurities by a method wherein silicon atoms which are put into an N type III-V group compound single crystal with a concentration of 10 cm or more is substituted by Vb group element lattice points to form a P type conducting layer. CONSTITUTION:An N gallium arsenide (GaAs) single crystal 2 having donor with a low concentration of 10 cm or so is grown epitaxially on an N gallium arsenide (GaAs) single crystal 1 to form a single crystal substrate, where ion implantation is performed to obtain an Si atom depositing layer 3 having Si with a concentration of 10 -10 cm . Since Si in GaAs is amphoteric impurities, a part or most part of it can be substituted by arsenic (As) lattice points. And a GaAs single crystal where ions are implanted is heated, at relatively low temperature for a long time, independently or together with gallium metal in a vacuum, gallium vapor or gallium melt to transform most of the layer containing Si into a P type layer 5 to form a P-N junction 4 in the crystal. This type of gallium arsenide P-N junction has only a slight damage, if any, and low specific resistance, so that it can be applied to optical devices such as a photodetector and electric devices such as a junction FET.

P-n Junction Capacitance Thermometers

Abstract: Silicon and germanium p-n junction capacitance thermometers making use of the temperature dependence of the junction capacitance were developed. At the temperatures at which the sensitivities are at a maximum, the specific sensitivities of the silicon and germanium capacitance thermometers are experimentally shown to be 0.34 and 1.74, respectively, at a measurement frequency of 1 kHz and are much greater than those of commercially-available strontium titanate glass-ceramic capacitance thermometers. According to the design principle shown here, a gallium arsenide p-n junction capacitance thermometer can measure a very low temperature down to about 2.8 K at a measurement frequency of 0.1 Hz.

Method for contacting a pn junction region

Abstract: The method and resulting structure for making contact to a narrow width PN junction region in any desired semiconductor body utilizes a substantially vertical conformal conductive layer (26) formed over the desired PN junction region (30, 32). The body is heated to a suitable temperature to cause a dopant to diffuse from the vertical conductive layer (26) into the semiconductor body to form the narrow width PN junction region (30, 32). A substantially horizontal conductive layer (22) makes contact to the substantially vertical layer (26) so as to have the horizontal conductive layer (22) in electrical contact to the PN junction region (30, 32). Electrical contacts (34, 36) can be established to the horizontal conductive layer at any convenient location. A lateral PNP transistor is one type of device that can be made.

Effect of steady electric field on the lifetime of minority carriers in p-n junction solar cells

Abstract: The Shockley-Read-Hall (SRH) theory of electron-hole recombination at traps has been modified to include the effect of steady electric field on the minority carriers in p-n junction solar cells. The modified expression predicts enhanced lifetime of minority carriers in the base region.

Integrated circuit contact structure

Abstract: A multi-layer contact structure is described for providing ohmic contact to a shallow semiconductor region (12) forming a PN junction with a silicon semiconductor body (10) The multi-layer structure includes a layer of polycrystalline silicon (22) doped with an impurity of the same conductivity type as that of the semiconductor region (12) A first layer (26) of a refractory metal is deposited over the polycrystalline silicon layer (22) to provide an electrically stable interface therewith A second layer (28) of another refractory metal is deposited over the first refractory metal layer and serves to protect the shallow PN junction against current leakage failure A third layer (34) of interconnect metal such as aluminium is deposited over the refractory metal layer