Showing papers on "p–n junction published in 1986"

Junction termination extension for near-ideal breakdown voltage in p-n junctions

Abstract: Extremely high breakdown voltages with very low leakage current have been achieved in plane and planar p-n junctions by using an ion-implanted junction extension for precise control of the depletion region charge in the junction termination. A theory is presented that shows a greatly improved control of both the peak surface and bulk electric fields in reverse biased p-n junctions. Experimental results show breakdown voltages greater than 95 percent of the ideal breakdown voltage with lower leakage currents than corresponding unimplanted devices. As an example, plane-junction moat-etch-terminated diodes with a normal breakdown voltage of 1050 V and a 0.5-mA leakage current become 1400 V (1450 ideal) devices with a 5-µA leakage current. Planar junctions, which broke down at 300 V, blocked as much as 1400 V if JTE terminated. Since planar junctions are of the greatest interest, we incorporated multiple field ring, field plate, and JTE terminations on a mask set and fabricated and tested thousands of devices. The results clearly showed that the ideal breakdown voltage can be achieved with less than 200 µm with JTE, where the same area would lead to 30 to 45 percent of the ideal with field rings and up to 40 to 50 percent of the ideal when used with field rings combined with field plates. Eight rings, even combined with a field plate, yielded less than 80 percent of the ideal breakdown voltage and required about 400 µm of device periphery.

Quantum well multijunction photovoltaic cell

Abstract: A monolithic, quantum well, multilayer photovoltaic cell comprises a p-n junction comprising a p-region on one side and an n-region on the other side, each of which regions comprises a series of at least three semiconductor layers, all p-type in the p-region and all n-type in the n-region; each of said series of layers comprising alternating barrier and quantum well layers, each barrier layer comprising a semiconductor material having a first bandgap and each quantum well layer comprising a semiconductor material having a second bandgap when in bulk thickness which is narrower than said first bandgap, the barrier layers sandwiching each quantum well layer and each quantum well layer being sufficiently thin that the width of its bandgap is between said first and second bandgaps, such that radiation incident on said cell and above an energy determined by the bandgap of the quantum well layers will be absorbed and will produce an electrical potential across said junction.

3C‐SiC p‐n junction diodes

Abstract: 3C‐SiC p‐n junction diodes are prepared on Si substrates by chemical vapor deposition growth with appropriate impurity doping, and their current‐voltage (I‐V) and capacitance‐voltage (C‐V) characteristics are studied. I‐V curves show good rectifying characteristics with a value of 3.3 for the ideal factor n and a reverse leakage current less than 10 μA at −5 V. The junction area is approximately 0.8 mm2. The built‐in voltage is around 1.4 V by C‐V measurements.

Light-electricity conversion semiconductor device

Abstract: A semiconductor light-electricity conversion device, includes: a Group III-V compound semiconductor region having a pn junction therein and including gallium and arsenic; a silicon region having a pn junction; a zinc selenide layer inserted between said two regions; and a plurality of electrodes for outputting light generated current from said two regions.

Junction leakage in titanium self‐aligned silicide devices

Abstract: Successful utilization of a titanium self‐aligned silicide (salicide) process for reproducible device fabrication with high yield requires junction leakage due to the silicide process to be minimized. The microstructure and microchemistry of titanium salicide shallow junction diodes were studied and correlated with junction leakage. The direct correlation between junction leakage and junction structure was established by using several analytical techniques. The main cause of large leakage current was found to be a loss of p+/n junction under the titanium silicide layer and formation of titanium silicide/n‐silicon Schottky barrier contact at the perimeter of the diodes. Process parameters for low leakage titanium silicide/p+/n diode fabrication were also established.

Flow sensor on insulator

Abstract: A flow sensor on a thermally insulating substrate is provided with improved thermal conductance and ruggedness to hostile environments The flow sensor includes a pn junction temperature sensing element on the substrate, a layer of dielectric material, which provides electric isolation and physical protection, covering the pn junction element, and a thin film heating element covering the dielectric layer and being in close thermal contact with the pn junction element

Pnp GaAs/Ge/Ge phototransistor grown by molecular beam epitaxy: Implications for bipolar and hot‐electron transistors

Abstract: In order to exploit the potential of GaAs/Ge heterojunctions for high‐speed heterojunction bipolar transistors and hot‐electron transistors, a Pnp GaAs/Ge floating base phototransistor, sensitive to 1.1–1.55‐μm wavelength range, was made. The gallium‐doped Ge substrate was first exposed to the As2 flux in the growth chamber of a molecular beam epitaxy system to form a pn junction in Ge. This was followed by the growth of a p‐type Be‐doped GaAs layer which served as the emitter. The fabricated mesa devices showed an optical gain of 85 at 1.15 μm incident wavelength. The gain was found to be nearly independent of the incident light power indicating good quality of the GaAs/Ge heterointerface.

p-n junction formation using laser induced donors in silicon

Abstract: The generation of high concentration defect‐related donor states during laser annealing of silicon with surface melting is found. Using these donors, p‐n junctions are fabricated on p‐type silicon substrate and good diode characteristics are obtained. Oxygen concentration increase in the laser annealed region is observed and suggests that the laser induced donors may be oxygen related. However, these donors are not oxygen thermal donors generally produced at moderate temperatures (<500 °C), because they are not annihilated by annealing at 650 °C. The present method provides for simple, low‐temperature p‐n junction formation without the addition of dopants. This method will be applicable to device fabrication on processed wafers without disturbing pre‐existing device characteristics.

Shallow junction formation by preamorphization with tin implantation

Abstract: Amorphizing n‐type 〈100〉 silicon by tin implantation prior to implanting 10 keV boron and then annealing for 30 min at 800 °C results in a 0.22‐μm‐deep p+/n junction. The implanted tin prevents boron channeling, enhances the quality of the solid phase epitaxial regrowth of the silicon, and shows no measurable diffusion. A discontinuous band of dislocation loops, 20–30 nm in diameter, with a density below 1010 cm−2 remains at the original amorphous‐crystalline interface after annealing. Junctions are nearly ideal and are characterized at −5 V reverse bias by an areal leakage of −5 nA cm−2 and a peripheral leakage less than −0.1 fA μm−1.

Electrical characterization of p+/n shallow junctions obtained by boron implantation into preamorphized silicon

Abstract: Electrical characteristics of p + / n diodes obtained by boron implantation into amorphous silicon layers formed by a prior implantation of Si + ions are presented. The absence of channeling phenomena (preamorphization), the low boron implantation energy (10–20 keV), and the post-implantation low temperature anneal (600–1000°C) or rapid anneal (electron beam) allow to obtain very shallow junctions (0.1–0.3 μm). Particular attention is given to analyse effects on the reverse diode current from dislocation loops which are formed at the amorphous-crystalline interface during annealing. If the dislocation loops are outside of the space charge region, the diodes show a low leakage current (∼ 1 nA/cm 2 at - 1 v), but the reverse current increases strongly when this residual damage falls into the depleted n -region. Experimental I–V characteristics are in excellent agreement with a numerical simulation, which takes into account a strong lifetime degration associated with the dislocation loops.

Semiconductor photo-detector having a two-stepped impurity profile

Abstract: A semiconductor photo-detector having a two-stepped impurity profile comprises a semiconductor substrate, a light absorption layer of a first conductivity type formed on a semiconductor substrate, a multiplication layer of a first conductivity type formed on the light absorption layer to multiply a photocurrent, a semiconductor region of a second conductivity type formed on the multiplication layer and constituting an abrupt pn junction with the multiplication layer, and a guard ring area of a second conductivity type formed around a periphery of the semiconductor region, whereby the carrier concentration profile of the guard ring region is sharp at its surface and flat below that surface.

Minority‐carrier properties of thin epitaxial silicon films fabricated by limited reaction processing

Abstract: Generation lifetimes and diode properties have been measured in epitaxial silicon films grown by limited reaction processing. Generation lifetimes from 1.4 to 94 μs were measured by observing the recovery of MOS capacitors from deep depletion. Planar diodes fabricated in both n‐ and p‐type epitaxial films show excellent behavior in both forward and reverse bias. p‐n junctions formed by growing p‐type epitaxial silicon directly on an n‐type substrate show no evidence of excessive interface defects or traps.

Gaas Pn Junction Studied by Scanning Tunneling Potentiometry

Abstract: The potential distribution across the cleaved end face of a forward‐biased GaAs pn junction was simultaneously mapped with its surface topography. The space‐charge region along the interface is clearly visible at zero bias or small forward bias voltages.

Semiconductor laser device and its manufacture

Abstract: PURPOSE:To make it possible to have a stable transverse mode and high output operation by making the third clad layer, an optical guide layer, a contact layer, the second clad layer which is a region directly under the optical guide layer and an active layer to be of the first conductivity type and the other regions be of the second conductivity type while making the width of a forbidden band near the resonator end face of the active layer be larger than in its inside. CONSTITUTION:In the region distant from the ridge part of an optical guide layer 8, a conductivity type of each layer in the vertical direction to a substrate 1 is in the order of npnp from the side of the substrate 1. Accordingly, when voltage is impressed so that a p-electrode 10 may be positive (+) and an n-electrode 11 may be negative (-), pn junction between a clad layer 5 and a current block layer 6 becomes a reverse bias so that not a current flows in this region. On the contrary, since a contact layer 7 and the optical guide layer 8 are linked together through a p-type diffusion region 9 in the vicinity of the optical guide layer 8, holes are injected from a clad layer 4a to an active layer 3a and electrons are implanted from a clad layer 2 to the active layer 3a in the lower part of the optical guide layer 8 for causing luminescence due to recombination of electrons and holes.

Electrochemical fabrication of a polypyrrole-polythiophene p-n junction diode

Abstract: A p–n junction thin film was fabricated by sequential electrochemical polymerization of pyrrole and thiophene on a Pt substrate, followed by controlled-potential electrochemical doping to make the polypyrrole layer anion-doped and the polythiophene layer cation-doped.

GaInAs junction FET with InP buffer layer prepared by selective ion implantation of Be and rapid thermal annealing

Abstract: GaInAs JFETs were fabricated on VPE-grown GaInAs layers The pn junctions have been realised with Be ion implantation and rapid thermal annealing The devices show a high transconductance of 130 mS/mm and an electron saturation velocity of 18 × 107 cm/s Channel mobilities measured at the complete device are as high as 6800 cm2/Vs These excellent device properties are due to the use of an undoped InP buffer layer which avoids the diffusion of Fe from the substrate into the active layer The data were supported by S-parameter measurements which gave a frequency limit of 20 GHz for gate dimensions of 16 by 200 ?m2

Semiconductor device with a planar junction and self-passivating termination

Abstract: A semiconductor device with a planar junction and self-passivating termination includes: a silicon substrate of one type of conductivity; an epitaxial layer of a second type of conductivity which is opposite to the first type of conductivity, lying on the substrate, so as to form with it a planar PN junction; a first region, of the first type of conductivity, that delimits, in its interior, an active portion of the device and extends transversely, from the surface of the epitaxial layer to the substrate with a portion having a high concentration of impurities and, on the surface, in the epitaxial layer, with a portion having a low concentration of impurities; and another region immersed in the epitaxial layer and of the same type of conductivity, but with a higher concentration of impurities. The latter region and the top portion of the first region extend toward each other with progressively decreasing concentrations of impurities. The first region may consist of a thin surface zone diffused on the walls and on the bottom of a deep groove of the type normally made in mesa devices. However, unlike mesa devices of the prior art the device according to the present invention does not require a thick layer of dielectric material in contact with the junction and its electrical properties are therefore improved and more reliable.

Passivated deep p/n junction

Abstract: A passivated deep p/n junction obtained by ion implantation is disclosed. The passivated deep p/n junction is formed in a wafer, preferably a silicon wafer, thus providing an emitter region that is both lightly doped and extending to a depth of about one micrometer. The emitter region in turn is provided with a surface layer so as to reduce surface recombination. Preferably, the surface layer is a silicon oxide layer of about 0.01 micrometer thickness. The p/n junction is obtained by ion implantation whereby the dopant is introduced at room temperature and then distributed thermally. The surface layer preferably is formed near the end of the thermal distribution by admitting a small amount of dry oxygen to a gas stream, and passing the gas stream along the surface of the wafer.

Semiconductor device with structures of thyristors and diodes

Abstract: It is given a reverse conducting, disconnectable thyristor structure. for breaking currents of 20 A ...> 2000 A and blocking voltages of 600 V ... is> 4500 V in the power electronics for controlling electric vehicle motors for DC-DC converter, inverter, electric filters, etc. applicable. A thyristor (GTO) with a plurality of parallel, disconnectable Einzelthyristoren is of a diode region (D) by a protective zone (S) separated and electrically largely decoupled, so that during the conducting phase of the anti-parallel to the Einzelthyristoren diode few free charge carriers in the thyristor section can get. For this purpose, the distance from the bottom of the recess of the protective zone (S) to a space charge zone (5) is kept low. Preferably, a second pn junction (17) in the region of the protective zone (S) at two points (21, 22) guided up to the bottom (20). On the anode side may be provided to facilitate the switching off of the GTO thyristors plurality of protective rings (14, 15).

Semiconductor light emitting device with vertical light emission

Abstract: A semiconductor light emitting device, such as a light emitting diode or laser, includes a substrate which is provided with a hole and a pn junction extending adjacent to and in parallel with the side wall of the hole. Thus, the side wall of the hole extends in a direction perpendicular to a main surface of the substrate. A pair of electrodes is provided such that current flows across the pn junction so that light emitted in a vertical direction which is perpendicular to the main surface of the substrate. The hole may be either a through hole or a bore hole. With the additional provision of a pair of resonators, there is provided a semiconductor laser.

Influence of hydrogen implantation on properties of n+p polycrystalline silicon solar cells

Abstract: Dark-current voltage curves, photocurrent and photovoltage of polycrystalline silicon solar cells are impaired by grain boundaries, intragrain defects, and recombination centres. Implantations of hydrogen ions passivated most active defects, as verified by EBIC contrast and by light-beam-induced current scan maps. Consequently the junctions are improved, and photovoltage, photocurrent, and electron diffusion lengths are increased. The passivation of the defects, like the main part of the photocurrent enhancement, is stable.

Charge transfer device with pn junction gates

Abstract: A plurality of static induction transistors capable of establishing a controllable potential barrier for charge carriers in the channel region between the source and the drain under the influence of the potentials of the gate and the drain connected in series and integrated in a semiconductor chip to constitute a charge transfer train. The drain of one static induction transistor and the source of the next adjacent static induction transistor are integrated in common into a charge storage region. An insulated electrode is provided on each charge storage region to control the potential thereof. The charge transfer train can be driven by 4-phase, 3-phase or 2-phase signals. The gate electrode and the drain electrode for each transistor may be integrated to form directional 2-phase charge transfer train. Image pick up device of very high operation speed can be materialized with the above charge transfer train.

Semiconductor device with a high breakdown voltage

Abstract: There is disclosed a power transistor comprising a semiconductor substrate having a PN junction exposed on a major surface of the semiconductor substrate, and a semiinsulative polysilicon film formed on the major surface, the polysilicon film covering the PN junction, the polysilicon film containing at least one of carbon, oxygen, and nitrogen, and the polysilicon film having a thickness of about 3000 Å.

Minority carrier lifetime improvement by single strained layer epitaxy of InP

Abstract: By applying a single LPE-grown isoelectronically doped strained layer, on top of a conventional InP wafer, a strong reduction of dislocation and deep level density occurs. As a result an improvement in minority carrier lifetime and diffusion length and a better uniformity across the wafer is achieved. This is demonstrated by the comparison of p-n diodes fabricated with and without the strained layer.

Active area limitation of Ge/GaAs heterojunctions by means of B ion implantation

Abstract: We have investigated the limitation of the active area of p‐n Ge/GaAs heterojunctions by means of B ion implantation into the interface of Ge/GaAs structure. Germanium epilayers were grown on (100) GaAs substrates by molecular beam epitaxy at a substrate temperature above 450 °C with a growth rate of about 10 nm/min. The Ge/GaAs heterojunction diode, fabricated with p‐n Ge/GaAs structure which was grown at the substrate temperature of 500 °C, represented a forward current voltage shoulder of 0.44 V and a breakdown voltage of 44 V. The ideality factor and the backward step recovery time of this diode was 1.09 and about 10 ns, respectively, similar to a Schottky barrier diode with same active area. In order to use the n‐GaAs substrate as an emitter of a heterobipolar transistor, it is necessary to limit the current flow into the same area of the collector through the base region. To realize this idea, B ions were implanted through the Ge epilayer, and the high‐resistivity region was formed in the GaAs subst...

Heterojunction bipolar integrated circuit

Abstract: A heterojunction bipolar integrated circuit is disclosed which uses a heterojunction bipolar transistor with a heterojunction between an emitter region (28) and a base region (30). In this transistor, a pn junction between the base region (30, 38) and the emitter region (28) has a greater area than a pn junction between the base region (30, 38) and a collector region (36). A plurality of such heterojunction bipolar transistors are isolated on a substrate to perform logic operations in an unsaturated region.

Comment on "NMOS ring oscillators with Cobalt-Silicided P-diffused shallow junctions formed during the 'poly-plug' contact doping cycle"

Abstract: Composite silicided source-drains are being developed to provide low-resistance shallow junctions for high performance fine-line circuits. The junctions are usually formed either by implantation and drive prior to silicide formation or else by implantation immediately after, followed by a heat cycle. This paper describes a novel approach for the fabrication of CoSi 2 /n+-p junctions (2 . 5 Ω/□ sheet resistance), wherein the junctions are doped by diffusion through the contact windows using the conventional "poly-plug" doping cycle [1], [2]. LPCVD poly-Si is deposited on windows to previously silicided gate and source-drain regions, and exposed to PBr 3 at an elevated temperature. Since the diffusivity of dopants in silicides is higher than in bulk Si, this step transports the P through the poly-Si via the windows laterally into the silicide, to form uniformly doped junction surrounds. This poly-Si doping scheme for junction fabrication eliminates an ion-implant step, provides an independent means of tailoring channel length, and can potentially result in low-resistance contacts even if the window etch step has punched through the silicide, Electrical characteristics of 1.25-µm gate-length ring oscillators are similar to those of circuits processed with the conventional As implant and drive. Transistor I-V 's and subthreshold behavior remain unaffected by the silicide doping process. Junction depth and leakage are sensitive functions of the poly-plug thermal cycle, with a 950°C 30-min drive resulting in 0.3-µm junctions. For a 1-µm design rule circuit layout, 30 to 45 min at 950°C is judged adequate.

On the effects of implantation of ions in the MeV energy range into silicon

Abstract: The effects of MeV phosphorus implantation and subsequent process steps on the electrical characteristics of p-channel field-effect transistors (FET), Schottky barrier diodes and p-n junctions were studied. The observed I–V characteristics can be explained in terms of spatially localized defects induced by the high-energy implantation and correlate well with the results using Monte Carlo simulation and C–V profiling techniques.