Showing papers on "p–n junction published in 1988"

Schottky barrier and pn-junction I/V plots — Small signal evaluation

Abstract: This paper proposes and examines three different plots for the determination of the saturation current, the ideality factor, and the series resistance of Schottky diodes and solar cells from the measurement of a single current (I)/voltage(V) curve. All three plots utilize the small signal conductance and avoid the traditional Norde plot completely. A test reveals that the series resistance and the barrier height of a test diode can be determined with an accuracy of better than 1%. Finally it is shown that a numerical agreement between measured and fittedI/V curves is generally insufficient to prove the physical validity of current transport models.

Ultraviolet light‐emitting diode of a cubic boron nitride pn junction made at high pressure

Abstract: Injection luminescence in the ultraviolet is observed from a cubic boron nitride pn junction diode made at high pressure. Microscopic observation and spectroscopic studies show that the light emission occurs near the junction region only in the forward‐bias condition. The spectra extend from ∼215 nm to the red, having a few peaks mainly in the ultraviolet.

A study of the leakage mechanisms of silicided n+/p junctions

Abstract: Leakage mechanisms for shallow, silicided, n+/p junctions have been investigated. This study consists of two parts: (a) the isolation of the processing steps that cause junction leakage, and (b) the study of the mechanism for a particular process that causes leakage. Reactive ion etching, improper junction, silicide formation procedures, ion mixing, and mechanical stress are found responsible for junction leakage, although through different mechanisms. Two mechanisms have been identified for junction leakage: (a) generation centers in the depletion region caused by deep levels from damage, or from impurities, and (b) Fowler–Nordheim tunneling caused by irregularities at the silicide/silicon interface at high reverse bias. Junction leakage can be avoided by carefully designing the details of silicide and junction formation and by carefully fine‐tuning the processing steps to prevent damage of the Si substrate after forming the junction. The best junctions are made by implanting As into CoSi2 and by driving the As into Si from the silicide at 800 °C. The lower temperature drive is possible since all ion damage is contained within the silicide, leaving no damage in the Si substrate to anneal out. Very shallow, silicided, n+/p junctions can be fabricated reproducibly. These junctions demonstrate the same electrical characteristics as deeper, nonsilicided junctions, indicating that there is no fundamental barrier prohibiting fabrication of low‐leakage, silicided junctions.

Electrostatic discharge protection circuit

Abstract: An ESD protection device includes a PNPN type device disposed between the input pad (12) and ground. A first P-layer (48) is disposed in an N-type well (46) which is formed in a P-type layer (44). A second N-region (52) is provided for connection to ground. This provides an SCR which can be turned on by avalanching the intermediate PN junction (32) to place the device in a regenerative mode for positive transients. For negative transients, a P+ region (54) is provided in P-layer (44) to bypass a PN junction (34) and a N+ region (50) is defined in the N-type region (46) to bypass PN junction (30). This provides a forward-biased diode for the negative transient.

Electrical properties of ion-implanted p-n junction diodes in β-SiC

Abstract: Mesa structure junction diodes prepared via high‐temperature ion implantation of Al+ (100 keV, 4.8×1014 Al/cm2) in n‐type or N+ (90 and 180 keV, 0.9 and 1.3×1014 N/cm2) in p‐type β‐SiC thin films were electrically characterized as a function of temperature using current‐voltage and capacitance‐voltage measurements. In either case, rectification was observed to the highest measurement temperature of 673 K. Closer examination of the device current‐voltage characteristics yielded diode ideality factors greater than 2. Additionally, the log dependence of these two parameters indicated space‐charge‐limited current in the presence of traps as the dominant conduction mechanism. From the temperature dependence of log‐log plots, trap energies and densities were determined. Two trapping levels were observed: (1) 0.22 eV with a density of 2×1018 cm−3 and (2) 0.55 eV with a density of 2×1016 cm−3. The former is believed to be ionized Al centers (in the case of Al‐implanted sample) and the latter a compensating accept...

Insulated gate bipolar transistor

Abstract: An insulated gate bipolar transistor having a reverse conduction function and comprising a semiconductor layer of a first conductivity type on the drain side, a semiconductor layer of a second conductivity type formed thereon to develop conduction modulation upon injection of carriers, a semiconductor layer of the second conductivity type that is formed in the above semiconductor layer of the second conductivity type and electrically connected to the drain electrode to take out the reverse conduction current flowing in a direction opposite to the drain current, and a semiconductor layer of the second conductivity type that is formed in the boundary surface or near the boundary surface of pn junction where the carriers are transferred to effect conduction modulation, and that has a high impurity concentration so as to serve as a path of the reverse conduction current and has a pattern which does not impair the transfer of the carriers. Owing to the above construction, there is incorporated a reverse conduction function having a small operation resistance, and it is allowed to flow a large current in the reverse direction, preventing the on-resistance from increasing and shortening the turn-off time.

CMOS having buried layer for carrier recombination

Abstract: In order to improve latchup withstanding capability, a CMOS device is provided with at least one recombination layer which is buried in either or both substrate regions of a pMOS and a nMOS at such a position that a depletion layer formed at a pn junction between both substrate regions of the pMOS and nMOS does not reach the recombination layer. The recombination layer is a polycrystalline silicon or amorphous silicon layer having plentiful carrier recombination centers, or a layer having plentiful traps formed by ion implantation, or a layer of a compound semiconductor having a small band gap.

WxN1−x alloys as diffusion barriers between Al and Si

Abstract: Reactively sputtered tungsten nitride (WxN1–x) layers are investigated as diffusion barriers between Al overlayers and Si shallow n + -p junctions. Both amorphous W80 N20 and polycrystalline W60 N40 films were found to be very effective in preserving the integrity of the n + -p diodes for 30-min vacuum annealing up to 575 °C. Diode failure at higher temperatures is caused by localized penetration of Al into through the WxN1–x barriers. The effectiveness of the barrier decreases for polycrystalline W90 N10 and is worse for pure W.

Very shallow p+‐n junction formation by low‐energy BF+2 ion implantation into crystalline and germanium preamorphized silicon

Abstract: Very low energy (6 keV) BF+2 ion implantation has been used to form very shallow (≤1000 A) junctions in crystalline and Ge+ preamorphized Si. Low‐temperature furnace annealing was used to regrow the crystal, and rapid thermal annealing was used for dopant activation and radiation damage removal. In preamorphized samples, Ge+ implantation parameters were found to have an influence on B diffusion. Our results show that for temperatures higher than 950 °C, B diffusion, rather than B channeling, becomes the dominant mechanism in determining the junction depth. Computer simulations of the profiles show regions of retarded and enhanced B diffusion, which depend on surface and end‐of‐range damage, respectively.

Fabrication of one-dimensional GaAs wires by focused ion beam implantation

Abstract: Novel, simple techniques were developed to fabricate very narrow GaAs conducting wires by utilizing direct focused ion beam (FIB) implantation. We employed two methods for fabrication of the wires. The first method makes use of high‐resistivity (HR) regions formed by FIB implantation without successive annealing to define a very narrow conducting wire (HR method). In the second one, focused Si ions are line implanted into p‐type GaAs, forming an n‐type conducting wire in the p‐type region. Then, reverse‐bias is applied across the pn junction in order to make the wire narrower by expanding the depletion layer (PN method). This structure has an advantage that the thickness of the wire can be varied by bias voltage. Magnetoconductances measured in all the fabricated wires show evidences of weak electron localization and conductance fluctuations due to a quantum interference effect. The minimum widths of the wires are evaluated to be ∼20 nm (HR method) and ∼100 nm (PN method) by fitting the theory of one‐dime...

Semiconductor laser having a lateral p-n junction utilizing inclined surface and method of manufacturing same

Abstract: A semiconductor laser having a laser resonator structure having a substrate with a trapezoidal projection forming on both sides of an upper base an inclined surface extending along a resonating direction of a resonator, a first semiconductor layer of a first or second conductivity type formed on the substrate, an active layer for generating a laser beam, a second semiconductor layer formed on the substrate and to which an impurity of a convertible conductivity type is doped with a portion of the second semiconductor layer above the inclined surface of the substrate having the first conductivity type and the other portion having the second conductivity type, and a pair of electrodes causing a current to flow through the active layer.

Semiconductor memory device

Abstract: A semiconductor memory device such as a MOS dynamic RAM comprises transistor portions (2, 3 and 5) for writing and reading a signal and capacitor portions (1, 2, 6 and 9) by pn junction for storing a signal. The capacitor portions have preferably as large a capacitance as possible. For this purpose, a capacitor hole (7) is formed in a p type semiconductor substrate (6) and an n type semiconductor region (9) is provided along the capacitor hole (7) so that the pn junction area therebetween is increased and the capacitance is made large.

Light emitting diode array chip and method of fabricating the same

Abstract: An LED array chip comprising; a first semiconductor layer having p-type conduction; a second semiconductor layer having a n-type conduction, possessing forbidden band width smaller than the first layer and provided on the first layer, so as to form a semiconductor chip having a pn junction at the interface with the first layer; the second layer being divided into a first region and a second region by etching the second layer through to the pn junction, the first region thereof being divided to form individual plural LEDs of predetermined configuration, and the n-type layer in the second region being converted to the p-type layer as so to serve as a common region; individual electrodes respectively provided to the surfaces of the LEDs; and a common electrode provided to the common region, parts of the exposed surface of the p-type layer corresponding to the LEDs serving as light emitting surfaces. The LED array chip is mounted on a printed circuit board by directly bonding the individual electrodes and the common electrode to the corresponding electrode pads of the printed circuit.

High breakdown active device structure with low series resistance

Abstract: Series resistance in the low impurity portion of a high breakdown PN junction of a three or four layer device is reduced by providing an increased impurity region at the junction of the same conductivity type as the low impurity portion and having an impurity profile such that the increased impurity region is depleted under reverse biasing before critical field is reached therein. The three layer device include insulated gate field effect transistors and bipolar devices and the four layer device is an SCR.

Electrical properties of shallow p+‐n junctions formed by BF2 ion implantation in germanium preamorphized silicon

Abstract: Shallow p+‐n junctions were formed by BF2 ion implantation into both crystalline and Ge preamorphized substrates. Rapid thermal annealing (RTA) was used for dopant activation and damage removal. Secondary ion mass spectroscopy (SIMS) was used to measure the boron and fluorine distribution profiles. Based on SIMS analysis, junction depths as shallow as 0.12 μm can be formed using 25 keV/1×1015 cm−2 BF2 ion implantation into Ge preamorphized Si. The influence of Ge implantation parameters on the leakage current of junctions was investigated. The results show that if the Ge implantation conditions are optimized, high quality p+‐n junctions can be formed in preamorphized substrates using RTA temperatures as low as 950 °C.

Damage to shallow n+/p and p+/n junctions by CHF3+CO2 reactive ion etching

Abstract: The damage incurred during contact etch is studied, with emphasis on determining those defects responsible for leakage current of shallow junctions. Shallow p+/n and n+/p junctions have been prepared with depths of 160–180 nm. Junction leakage and contact resistance measurements have been made for various amounts of silicon loss up to within 20 nm of the junctions during contact etch through a 300 nm of SiO2 film by using a CHF3+CO2 plasma. For p+/n junctions, the leakage current density was found to depend strongly on contact area and increase rapidly with etch depth after the etched surface has extended to within 80 nm of the junction boundary. On the other hand, the leakage current stays constant even when the etched surface approaches within 40 nm of the junction boundary for n+/p junctions. Further etching of the n+/p junction only induces punch‐through. Contact resistance was found to increase with etch depth for the p+ junctions after 50 nm of silicon was removed from the surface, and stays constan...

Effects of heavy impurity doping on electron injection in p+‐n GaAs diodes

Abstract: Measurements of electron injection currents in p+‐n diodes are presented for a range of p‐type dopant concentrations. A successive etch technique was used to characterize the electron injection current in terms of the product (noDn). Measurements are presented for Zn‐doped GaAs solar cells with p‐layer hole concentrations in the range 6.3×1017−1.3×1019 cm−3. The results demonstrate that so‐called band‐gap narrowing effects substantially increase the injected electron current in heavily doped p‐type GaAs. These heavy doping effects must be accounted for in the modeling and design of GaAs solar cells and heterostructure bipolar transistors.

Thickness of p/n junction space-charge layers

Abstract: A model for finding the space‐charge‐layer thickness is developed based on the relevant device physics and on a space‐charge‐layer capacitance model which accounts for the effects of the free‐carrier charges in the space‐charge layer Discrepancies of as much as 50% are predicted when the present model is compared with the conventional depletion model A partitioned charge‐based model is used to illustrated the usefulness of the model

Low-resistance AuZn gate ohmic contacts for InP JFETs

Abstract: The fabrication and characteristics of AuZn gate ohmic contacts for InP JFETs are presented. The contacts are 1 μm × 600 μm in area and less than 3000 A deep to maintain the quality of the pn junction below the surface. The contacts are fabricated by the simultaneous evaporation of Au and Zn and hot-plate alloyed at 410°C. To prevent the outdiffusion of Zn into the subsequently-deposited thick gold layer, a diffusion barrier of TiW is used. The best specific contact resistance was measured to be 3.7 × 10−5 Ω-cm2 for a Be doping of 1018 cm−3 which is among the lowest values ever reported for contacts to p-type InP. This d.c. contact resistance value was found to be in good agreement with microwave measurements performed on JFETs under normal operating conditions. In the InP JFET, the gate contact resistance dominates the other gate resistances and its effect on the microwave performance is discussed.

High-speed non-linear circuit models for p-n junction diodes

Abstract: Circuit models for both long-base and short-base p-n junction diodes which are valid for non-linear high-speed and high-frequency operations are presented. the diode model consists of a parallel connection of higher-order dynamic elements and includes the conventional diffusion model as a special case. the new dynamic model can be used for simulating arbitrary p-n junction diode circuits under all operating conditions. In particular, it is capable of simulating realistically the diode's reverse transient behaviour and providing an increasingly accurate approximation to the diffusion equation as the order of the model gets higher. the model is also shown to be capable of reproducing the frequency-dependent small-signal characteristics of p-n junction diodes. The model is based mainly upon the device's physical operating principles. Perhaps the most significant implication of the model is the fact that it illustrates the important roles played by higher-order and dynamic elements in highspeed and high-frequency non-linear device modelling.

Electrical characterization of in-situ epitaxially grown Si p-n junctions fabricated using limited reaction processing

Abstract: Forward current ideality factors of 1.01+or-0.3% were obtained over a large current range extending down to 1 pA. Reverse current densities measured 3.5+or-1.2 nA/cm/sup 2/ at a reverse bias of -5 V. Breakdown occurred at the expected value of -22 V and displayed a very sharp current rise of 30 decades/V. Extremely uniform light emission from the junction was observed under a microscope at breakdown, this phenomenon is a visual indication that the material is of high quality and suitable for high-performance minority-carrier devices. >

pn + junction in an implanted electroactive polymer: poly(paraphenylene)

Abstract: We have recently shown that specific and stable n or p doping may be obtained on poly(paraphenylene) providing moderate implantation conditions with appropriate ions are used. Here we describe a pn+ -junction made in intrinsic insulating poly(paraphenylene) (σ <10−12 Ω −1 cm−1) by implantation (E ⋍ 50keV) of alkali metal ions (essentially caesium for n doping) and halogen (iodine for p doping).

Method of manufacturing semiconductor device including substrate bonding and outdiffusion by thermal heating

Abstract: A method of manufacturing a semiconductor device comprising the steps of bringing a mirror-polished surface of a first semiconductor substrate of a first conductivity type into contact with a mirror-polished surface of a second semiconductor substrate of a second conductivity type having an impurity concentration which is lower than that of said first conductivity type, in a clean atmosphere, and thermally heating said first and second semiconductor substrates so that they unite. Impurity is diffused from said first semicondutor substrate into said second semiconductor substrate, thereby forming a diffusion layer of a first conductivity type in said second semiconductor substrate. A total amount of impurity of said diffusion layer is 1×10 13 /cm 2 to 2×10 15 /cm 2 , to form a pn junction in said second semiconductor substrate.

Depletion approximation analysis of an exponentially graded semiconductor p-n junction

Abstract: Estimation of important properties of p-n junctions such as reverse leakage current and capacitance is greatly facilitated by the depletion approximation. Computation of the electrostatic potential and electron and hole concentrations within this approximation are commonplace in the microelectronics industry. The depletion approximation requires appropriate and accurate boundary conditions. Thus far, such reasonable boundary conditions have been widely applied only for the case in which the p-type and n-type impurity concentrations are spatially uniform. The author derives the solution of the depletion approximation with appropriate boundary conditions for the case in which the impurity concentration on one side of the diode decays exponentially with distance. He plots the potential and charge density of this exponential depletion approximation and compares these results to full numerical solution of the semiconductor equations. The agreement between the proposed approximation and the numerical solution validates this approximation scheme. >

Process of manufacturing semiconductor integrated circuit device and product formed thereby

Abstract: A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease. The U-shaped grooves can each comprise narrow and deep sub-grooves, with thick oxide films formed on the surfaces of the sub-grooves and a thick oxide film formed on a surface of an area between the sub-grooves, and with wiring formed on the oxide on the area between the sub-grooves.

Modulation doped radiation emitting semiconductor device

Abstract: A radiation-emitting semiconductor device (i.e. an LED or laser) emits radiation produced by radiative recombination of electrons from a field induced two-dimensional (2-d) electron gas with holes from a field induced two-dimensional (2-d) hole gas. The device uses a narrower band semiconductor active layer sandwiched between two layers of a wider band semiconductor. Top and bottom gates are used to induce the electron and hole 2-d gasses in the active layer. N+ and P+ regions are used to contact the 2-d electron and hole gasses to provide separate biasing. The thickness of the active layer is such that a field induced PN junction or PIN structure is formed at which radiative recombination can occur.

Experimental characterization of two‐dimensional dopant profiles in silicon using chemical staining

Abstract: An experimental technique for the measurement of two‐dimensional impurity diffusion profiles in silicon has been developed. Both the lateral and in‐depth extent of dopant diffusion under a mask edge are magnified mechanically by sawing and angle lapping, and the magnified junction contour is delineated by chemical staining. The two‐dimensional shape of the junction is reconstructed from the measured stained contour. A complete diffusion profile consisting of several isoconcentration contours can be obtained by measuring the junction shape on a series of samples with increasing substrate resistivities, provided the doping level in the substrate does not affect the diffusion of the impurity under study. Results of the two‐dimensional diffusion of boron in silicon at 1050 °C are presented.

Capacitance of semiconductor p-n junction space-charge layers: an overview

Abstract: The modeling of capacitance of p-n junction space-charge layers in semiconductor devices is discussed. First, previously developed models and methods are reviewed. Capacitance models developed recently by the authors that include mobile-carrier, nonquasi static, and multidimensional effects are then considered. These models yield more accurate device and circuit simulations for semiconductor integrated circuits. The emphasis is on diodes and bipolar transistors, but many concepts used apply as well to p-n junctions of metal-oxide-semiconductor field effect transistors. The review includes conventional homojunction devices (devices fabricated with a single semiconductor such as silicon) and the increasingly important heterojunction devices (devices fabricated with two or more semiconductors or a semiconductor having a spatially varying chemical composition such as gallium-aluminum-arsenide). >