Showing papers on "p–n junction published in 1991"

Semiconductor physics and devices

Abstract: Neamen's Semiconductor Physics and Devices, Third Edition. deals with the electrical properties and characteristics of semiconductor materials and devices. The goal of this book is to bring together quantum mechanics, the quantum theory of solids, semiconductor material physics, and semiconductor device physics in a clear and understandable way. Table of contents Prologue Semiconductor and the Integrated Circuit 1 The Crystal Structure of Solids 2 Introduction to Quantum Mechanics 3 Introduction to the Quantum Theory of Solids 4 The Semiconductor in Equilibrium 5 Carrier Transport Phenomena 6 Nonequilibrium Excess Carriers in Semiconductors 7 The pn Junction 8 The pn Junction Diode 9 Metal-Semiconductor and Semiconductor Heterojunctions 10 The Bipolar Transistor 11 Fundamentals of the Metal-Oxide-Semiconductor Field-Effect Transistor 12 Metal-Oxide-Semiconductor Field-Effect Transistor: Additional Concepts 13 The Junction Field-Effect Transistor 14 Optical Devices 15 Semiconductor Power Devices Appendix A Selected List of Symbols Appendix B System of Units, Conversion Factors, and General Constants Appendix C The Periodic TableAppendix D The Error FunctionAppendix E "Derivation" of Schrodinger's Wave EquationAppendix F Unit of Energy- The Electron-VoltAppendix G Answers to Selected Problems

High-power GaN P-N junction blue-light-emitting diodes

Abstract: High-power p-n junction blue-light-emitting diodes (LEDs) were fabricated using GaN films grown with GaN buffer layers. The external quantum efficiency was as high as 0.18%. Output power was almost 10 times higher than that of conventional 8-mcd SiC blue LEDs. The forward voltage was as low as 4 V at a forward current of 20 mA. This forward voltage is the lowest ever reported for GaN LEDs. The peak wavelength and the full width at half-maximum (FWHM) of GaN LEDs were 430 nm and 55 nm, respectively.

Fundamentals of Solid State Electronics

Abstract: Electrons, bonds, bands and holes homogeneous semiconductor at equilibrium drift, diffusion, generation, recombination, trapping and tunneling metal-oxide-semiconductor capacitor P/N and other junction diodes metal-oxide-semiconductor and other field-effect transistors bipolar junction transistor and other bipolar transistor devices.

Introduction to Semiconductor Materials and Devices

Abstract: BASIC PHYSICS. Review of Atomic Structure and Statistical Mechanics. Crystalline Solids and Energy Bands. FUNDAMENTALS OF SEMICONDUCTORS. Semiconductor Materials and Their Properties. Carrier Transport in Semiconductors. Excess Carriers in Semiconductors. JUNCTIONS AND INTERFACES. p-n Junctions. Static I-V Characteristics of p-n Junction Diodes. Electrical Breakdown in p-n Junctions. Dynamic Behavior of p-n Junction Diodes. Majority Carrier Diodes. SEMICONDUCTOR DEVICES. Microwave Diodes. Optoelectronic Devices. Bipolar Junction Transistors I: Fundamentals. Bipolar Junction Transistors II: Devices. Junction and Metal-Semiconductor Field-Effect Transistors. MOS Transistors and Charge-Coupled Devices. Circuit Models for Transistors. Power Rectifiers and Thyristors. SEMICONDUCTOR TECHNOLOGY AND MEASUREMENTS. Technology of Semiconductor Devices and Integrated Circuits. Semiconductor Measurements. Appendices. Answers to Selected Problems. Index.

Tunnel junction multiple wavelength light-emitting diodes

Abstract: A multiple wavelength LED having a monolithic cascade cell structure comprising at least two p-n junctions, wherein each of said at least two p-n junctions have substantially different band gaps, and electrical connector means by which said at least two p-n junctions may be collectively energized; and wherein said diode comprises a tunnel junction or interconnect.

High‐voltage 6H‐SiC p‐n junction diodes

Abstract: A chemical vapor deposition (CVD) process has been used to produce device structures of n- and p-type 6H-SiC epitaxial layers on commercially produced single-crystal 6H-SiC wafers. Mesa-style p-n junction diodes were successfully fabricated from these device structures using reactive ion etching, oxide passivation, and electrical contact metallization techniques. When tested in air, the 6H-SiC diodes displayed excellent rectification characteristics up to the highest temperature tested, 600 C. To observe avalanche breakdown of the p-n junction diodes, testing under a high-electrical-strength liquid was necessary. The avalanche breakdown voltage was 1000 V representing the highest reverse breakdown voltage to be reported for any CVD-grown SiC diode.

Spin-dependent Shockley-read recombination of electrons and holes in indirect-band-gap semiconductor p-n junction diodes

Abstract: This paper presents a new model for spin-dependent recombination and generation processes based on the electrical detection of magnetic resonance in semiconductor p - n junction diodes. Based on a modified Shockley-Read recombination statistics, this model differs from those models previously proposed in that the spin-dependent enhancement of free-carrier capture processes can occur directly at a paramagnetic deep defect without the need for other defects nearby. This model incorporates singlet-triplet mechanisms of existing models, but is shown to be consistent with new experimental results which indicate the absence of any adjacent trapping centers.

Process limitation and device design tradeoffs of self-aligned TiSi/sub 2/ junction formation in submicrometer CMOS devices

Abstract: Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive metallization scheme to solve many CMOS scaling problems. However, to achieve a shallow junction with a salicide structure requires careful optimization for device design tradeoffs. Several proposed techniques to form shallow titanium silicide junctions are critically examined. Boron, BF/sub 2/, arsenic, and phosphorus dopants were used to study the process parameters for low-leakage TiSi/sub 2/ p/sup +//n and n/sup +//p junctions in submicrometer CMOS applications. It is concluded that the dopant drive-out (DDO) from the TiSi/sub 2/ layer to form a shallow junction scheme is not an efficient method for titanium salicide structure; poor device performance and unacceptably leaky junctions are obtained by this scheme. The conventional post junction salicide (PJS) scheme can produce shallow n/sup +//p and p/sup +//n junctions with junction depths of 0.12 to 0.20 mu m below the TiSi/sub 2/. Deep submicrometer CMOS devices with channel length of 0.40 to 0.45 mu m can be fabricated with such junctions. >

The behavior of silicon p‐n junction‐based devices at liquid helium temperatures

Abstract: In this paper, the forward current‐voltage (I‐V) characteristics of Si p‐n junction diodes, fabricated in different state‐of‐the‐art complementary‐metal‐oxide‐semiconductor (CMOS) technologies, are investigated at liquid helium temperatures. As will be shown, three different I‐V regimes can exist: a forward breakdown/hysteresis regime at a turn‐on voltage which may be larger than the built‐in potential of the junction; a thermionic emission regime, corresponding to a I=A exp(qV/kT) relation and a high‐injection space‐charge‐limited regime, giving rise to a current which is proportional to Vn. The anomalous turn‐on behavior can be explained by considering the small barrier for carrier injection, which exists at the ‘‘ohmic’’ contact. It will be demonstrated that the presence of this forward breakdown is strongly determined by the fabrication technology used. In extreme cases (large‐area well diodes) multiple breakdown is observed, indicating an inhomogeneous, filamentary current flow. As will be shown, sim...

Plasma immersion ion implantation of SiF4 and BF3 for sub‐100 nm P+/N junction fabrication

Abstract: Sub‐100 nm P+/N junctions were fabricated using plasma immersion ion implantation (PIII). With this technique, the silicon wafer was immersed in SiF4/BF3 plasma and biased with a negative voltage. The positively charged ions in the plasma sheath were accelerated by the electric field and implanted into the wafer. The dose rate of PIII can be much higher than that of conventional ion implanter. Whereas the dopant activation behavior is similar. For extremely shallow P+/N junction formation, sample preamorphization and short cycle rapid thermal annealing (RTA) are required. With SiF4 PIII preamorphization followed by BF3 PIII doping and RTA at 1060 °C for 1 s, 80 nm P+/N junctions were successfully obtained. Test diodes fabricated with this technique show good characteristics.

Material and electrical properties of ultra-shallow p/sup +/-n junctions formed by low-energy ion implantation and rapid thermal annealing

Abstract: A study of low-energy ion implantation processes for the fabrication of ultrashallow p/sup +/-n junctions is presented. The resulting junctions are examined in terms of four key parameters: defect annihilation, junction depth, sheet resistance, and diode reverse leakage current. In the realm of very-low-energy ion implantation, Ge preamorphization is found to be largely ineffective at reducing junction depth, despite the fact that the as-implanted boron profiles are much shallower for preamorphized substrates than for crystalline substrates. Transmission electron microscopy (TEM) analysis of residual defects after rapid thermal annealing (RTA) reveals that the use of either a preamorphization implant or the implantation of BF/sub 2/ as a B source results in residual damage which requires higher RTA temperatures to be removed. A reasonable correlation is observed between residual defect density observed via TEM and junction leakage current. It is concluded that the key to an optimized low-energy implantation process for the formation of ultrashallow junctions appears to be the proper selection of preamorphization and annealing conditions relative to the dopant implant energy. >

Semiconductor schottky device with pn regions

Abstract: A semiconductor device has a first diode having a pn junction and a second diode having a combination of a Schottky barrier and a pn junction in a current-passing direction provided side by side in a direction perpendicular to the current-passing direction. When a forward current with a current density JF is passed into the second diodes, the relation ##EQU1## is established in a forward voltage VF range of 0.1 (V) to 0.3 (V), where k represents the Boltzmann constant, T represents the absolute temperature, and q represents the quantity of electron charges. The first diode is constituted by a first semiconductor region of one conductive type and a second semiconductor region of the other conductive type provided so as to be adjacent to the first semiconductor region to form a pn junction, so as to be in ohmic contact with one main electrode, and so as to have an impurity concentration higher than that of the first semiconductor region, and the second diode is constituted by the first semiconductor region of the one conductive type and a third semiconductor region of the other conductive type provided so as to be adjacent to the first semiconductor region to form a pn junction, so as to be in contact through a Schottky barrier with the one main electrode, and so as to have an impurity concentration higher than the first semiconductor region.

Characterization of ultra-shallow p/sup +/-n junction diodes fabricated by 500-eV boron-ion implantation

Abstract: Ultrashallow gated diodes have been fabricated using 500-eV boron-ion implantation into both Ge-preamorphized and crystalline silicon substrates. Junction depths following rapid thermal annealing (RTA) for 10 s at either 950 degrees C or 1050 degrees C were determined to be 60 and 80 nm, respectively. These are reportedly the shallowest junctions formed via ion implantation. Consideration of several parameters, e.g. reduced B/sup +/ channeling, increased activation, and reduced junction leakage current, lead to the selection of 15 keV as the optimal Ge preamorphization energy. Transmission electron microscope results indicated that an 850 degrees C/10-s RTA was sufficient to remove the majority of bulk defects resulting from the Ge implant. Resulting reverse leakage currents were as low as 1 nA/cm/sup 2/ for the 60-nm junctions and diode ideality factors for crystalline and preamorphized substrates ranged from 1.02 to 1.12. Even at RTA temperatures as low as 850 degrees C, the leakage current was only 11 nA/cm/sup 2/. The final junction depths were found to be approximately the same for both preamorphized and nonpreamorphized samples after annealing at 950 degrees C and 1050 degrees C. However, the preamorphized sample exhibited significantly improved dopant activation. >

Planar pn-junction of high electric strength

Abstract: A planar pn-junction with high electric strength, which separates a semiconductor region inserted in a semiconductor body from the rest of the semiconductor body, has, in its border region, a plurality of field plates which are separated from a semiconductor zone residing below and extending the semiconductor region by an electrically insulating layer. The field plates contact the semiconductor zone in the area of contact holes. The contact holes respectively have set distances between them and the inner and outer field plate edges, whereby below those field plate parts residing between the contact holes and the inner field plates borders, local doping maxima of the semiconductor zone are provided.

Sub-100 mn p+/n junction formation using plasma immersion ion implantation

Abstract: Using plasma immersion ion implantation (PIII), sub-100 nm p+/n junctions were fabricated with SiF4 preamorphization followed by BF3 doping. With this technique, the dose rate can be as high as 1016/cm2 per second. The silicon wafer was immersed in SiF4 or BF3 plasma and biased with a negative voltage. The positively charged ions were accelerated by the electric field in the plasma sheath and implanted into the wafer. The junction depth can be controlled by varying the negative voltage applied to the wafer holder and thermal annealing conditions.

Interband tunneling in heterostructure tunnel diodes

Abstract: A particular type of tunnel diode, incorporating a wideband tunnel barrier, is studied. Simple analytic expressions are developed for estimating the tunneling coefficients to guide and optimize the design of heterostructure interband tunnel devices. The interband tunneling in such heterostructure tunnel diodes is modeled by a two-band Schrodinger equation. For a certain family of InGaAs/InA/GaAs p-n junction tunnel diodes, the interband transmission coefficients are calculated. The estimated peak currents are shown to compare very favorably with experimental results. >

Thin-film-transistor having schottky barrier

Abstract: Disclosed herein is a semiconductor device including a thin-film-transistor which comprises a silicon film formed on an insulating layer and including a substrate area, a gate provided to form a channel in the substrate area, a source consisting of a first metal silicide film forming a Schottky barrier with the substrate area, and a drain including a second metal silicide film. The second metal silicide film forms a Schottky barrier with the substrate area or is in ohmic contact with an impurity region selectively formed in the silicon film with a PN junction with the substrate area.

p‐n junction diode made of semiconducting diamond films

Abstract: A diamond p‐n junction diode fabricated by the chemical vapor deposition technique, shows distinct rectification characteristics. From the electron beam induced current measurement, the existence of a depletion region or a space‐charge region around the interface between the n‐ and p‐type semiconducting diamond layers was identified.

Process for forming a semiconductor structure with closely coupled substrate temperature sense element

Abstract: MOSFET devices or circuits incorporating an improved substrate temperature sensing element are obtained by forming a PN junction directly on a thin (gate) dielectric region. The temperature sense junction is desirably formed in a poly layer. By mounting it directly on thin (gate) dielectric its thermal response to temperature changes in the substrate is improved while still being electrically isolated from the substrate. It is desirable to provide over-voltage protection elements coupled to the junction to avoid rupture of the underlying thin dielectric. Because the sense diode and all the over-voltage protection devices may be made of poly with junctions perpendicular to the substrate, the structure is particularly compact and simple to fabricate.

Resonant-tunneling heterojunction bipolar transistor device

Abstract: A resonant-tunneling heterojunction bipolar transistor (RHBT) device having a superlattice structure and a PN junction. The RHBT includes an emitter layer; a base layer; a collector layer operatively facing the base layer to form a PN junction at the face between the base layer and the collector layer; and a superlattice structure including at least one quantum well defining a sub-band of energy at which carriers resonant-tunnel therethrough, formed at least in the emitter layer and operatively facing to the base layer. The RHBT has a differential negative resistance characteristics for realizing a variety of logic circuits and includes an electron resonance and a positive hole resonance, for which the generation condition is changeable in response to a mole fraction of material of the emitter layer.

Gallium phosphide junctions with low leakage for energy conversion and near ultraviolet detectors

Abstract: There is a need for semiconductor junctions with very low leakage for energy conversion from low level radioactive or radio‐luminescent sources, and low noise blue‐green photodiodes. We report the properties of two types of GaP junctions; a Schottky barrier of Pd on liquid phase epitaxy grown n‐type GaP and a p+ over n junction grown by metal‐organic chemical vapor deposition. Both types of junctions show very low leakage currents and good efficiency for power conversion from low level beta particles, x rays, and blue‐green light.

Blue Electroluminescence from ZnSe p-n Junction Light-Emitting Diodes

Abstract: Pure blue-light emission has been obtained from homoepitaxial ZnSe p-n junction light-emitting diodes (LEDs). Homoepitaxy is made on ZnSe substrates dry-etched by a BCl3 plasma. High-quality p-n junctions consists; of N-doped p-type ZnSe formed by active-nitrogen doping and Cl-doped n-type ZnSe using ZnCl2 as a dopant source. Current-voltage characteristics of the LEDs exhibited good rectification properties. The peak energy of blue electroluminescence from the LEDs was 2.67 eV with a narrow full width at half-maximum of 49 meV.

Fabrication of a diamond p-n junction diode using the chemical vapour deposition technique☆

Abstract: A diamond p − n junction diode has been fabricated by the chemical vapour deposition technique. Diphosphorus pentaoxide and boron trioxide were used for the doping sources for the n - and p -type layers, respectively. The diode shows distinct rectification characteristics at 300 K room temperature. This diode shows rectification even at 370 K and this result implies the possible use of diamond as a semiconductor in high temperature conditions.

Method of making a surface emitting laser with oxygen ion implants followed by epitaxial regrowth

Abstract: A surface emitting laser diode device is disclosed where an active layer is implanted with oxygen ions except for a small active region. The active region includes a pn junction for generating radiation in response to passage of electrical current therethrough. After the oxygen implantation, mirror layers are grown on top of the active layer to reflect light generated in the active region back into the active region to induce more radiation emission. Mirror layers are also provided underneath the active region for the same purpose. Contact layers are provided on the top and bottom of the structure just described so that when an electrical potential is applied between the two contacts, electrical current will flow between the contacts between the active region for generating radiation. The oxygen-implanted isolation region surrounds the active region in order to confine current flow to the active region.

Manufacture of solar cell

Abstract: PURPOSE: To form a pn junction at low temperature, inhibit a drop in film quality and form a pn junction having high carrier concentration and shallow graded structure. CONSTITUTION: A non-doped (for example, n - type α-Si) an opposite conductivity type amorphous silicon layer (for example, n + type α-Si layer) are deposited on a substrate whose surface comprises at least one conductivity type crystal silicon layer (for example, p-type polycrystalline silicon layer) based on a CVD process at a temperature ranging from around 150 to 300°C. Then, it is heat- treated and crystallized, thereby forming a pn junction having a graded structure. The carrier concentration of the crystallized silicon layer is in the order of 10 21 cm -3 while the film thickness can be 200 to 2000Å (therefore, the thickness of the pn junction has the same depth). Moreover, it is possible to enhance short circuit optical current due to surface field effect by providing a graded structure. This pn junction has a sufficiently practical capacity to use as a solar cell. COPYRIGHT: (C)1992,JPO&Japio

Semiconductor laser device

Abstract: PURPOSE:To enable light intensity of a laser beam to be monitored easily by providing an electrode for applying voltage to a pn junction at a current block layer. CONSTITUTION:When a laser beam of a transparent semiconductor laser for a clad layer 5 is absorbed by a current block layer 6, an electron hole pair is generated due to light absorption of the block layer 6 and diffused minority carriers enable a depletion layer to be drifted near a junction surface with a clad layer 5, thus allowing current in inverse direction for the pn junction to flow. Then, with an electrode 12 formed at the current block layer 6, it is possible to determine the intensity of light by monitoring the current in inverse direction.

Semiconductor device and manufacture thereof

Abstract: PURPOSE:To improve the surge breakdown strength of a low voltage Zener diode and to lower the leak current value corresponding to the breakdown voltage by forming a region of the same conductivity as the main body and high in impurity concentration on the semiconductor body side of a pn junction face, and forming a guard ring deeper than at least the sum of the depths of both regions, surrounding both of them. CONSTITUTION:On the whole face of the N-type epitaxial layer 2 at the surface of an N-type semiconductor an N -type diffusion layer 3 higher in impurity concentration than this is formed in depth k. The oxide film 4 on that is etched selectively to form a contact hole 7a, and boron (p-type impurities) are implanted circularily in depth l deeper than the depth k of the diffusion layer 3 so as to form a guard ring 5. Next, boron(B) is implanted in shallower depth m than depth k and in fixed concentration into the part 3a surrounded by this so as to form a P-type diffusion layer 6 being the same conductivity type as the guard ring 5. After that, additional diffusion is applied so that Zener voltage Vz may be nearly the desired value, and an electrode 7 is filled in a contact hole 7a, and is brought into contact with the diffusion layer 6, thus a constant voltage Zener diode 10 is obtained.

Scanning tunneling microscopy and spectroscopy of pn junctions formed by ion implantation

Abstract: Results of scanning tunneling spectroscopy measurements of 〈100〉 n‐ and p‐type silicon are reported. Measurements were made in air on surfaces with a native oxide. Different I/V characteristics were observed for differently doped samples, indicating that the surfaces were unpinned. Images are presented of pn junctions formed by the implantation of phosphorus into boron doped Si wafers. The pn junction, or the boundary between implant and substrate regions, was observed in both constant current and constant height scans. The junction was imaged with 125 A point‐to‐point resolution.