Showing papers on "p–n junction published in 1992"

Blue-green laser diode

Abstract: A II-VI compound semiconductor laser diode (10) is formed from overlaying layers of material including an n-type single crystal semiconductor substrate (12), adjacent n-type and p-type guiding lasers (14) and (16) of II-VI semiconductor forming a pn junction, a quantum well active layer (18) of II-VI semiconductor between the guiding layers (14) and (16), first electrode (32) opposite the substrate (12) from the n-type guiding layer (14), and a second electrode (30) opposite the p-type guiding layer (16) from the quantum well layer (18) Electrode layer (30) is characterized by a Fermi energy A p-type ohmic contact layer (26) is doped, with shallow acceptors having a shallow acceptor energy, to a net acceptor concentration of at least 1 x 1017 cm-3, and includes sufficient deep energy states between the shallow acceptor energy and the electrode layer Fermi energy to enable cascade tunneling by charge carriers

Development of New a-Si/c-Si Heterojunction Solar Cells: ACJ-HIT (Artificially Constructed Junction-Heterojunction with Intrinsic Thin-Layer)

Abstract: A new type of a-Si/c-Si heterojunction solar cell, called the HIT (Heterojunction with Intrinsic Thin-layer) solar cell, has been developed based on ACJ (Artificially Constructed Junction) technology. A conversion efficiency of more than 18% has been achieved, which is the highest ever value for solar cells in which the junction was fabricated at a low temperature (<200°C).

GaAs p‐n junction formed in quantum wire crystals

Abstract: A p‐n junction is formed for the first time in a cross‐sectional area of a GaAs wire crystal with a diameter of about 100 nm. Ultrafine cylindrical growth by metalorganic vapor phase epitaxy is employed for the fabrication. Current‐voltage and capacitance‐voltage characteristics confirm the formation of the p‐n junction in a narrow area at the midpoint of a wire crystal. Intensive light emission by current injection is observed at 77 K and even at room temperature. These results suggest that ultrafine optoelectronic devices with quantum‐size p‐n junction are possible.

Visible electroluminescence from porous silicon np heterojunction diodes

Abstract: We report the preparation of silicon‐based visible light‐emitting diodes, configured as heterojunctions between porous silicon (formed by electrochemical etching of p‐type silicon wafers), and n‐type indium tin oxide (ITO). The transparent ITO film allows light emission through the top surface of the device, under a forward electrical bias of several volts across the junction. Photogenerated currents are observed under reverse biases. A tentative model for this electroluminescence is presented, based on injection of minority carriers through a narrow interphase region into the porous silicon structure, where radiative recombination occurs.

Constant-voltage diode for over-voltage protection

Abstract: A constant-voltage diode has a first semiconductor region of a first conductivity type, an adjoining semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type adjoining the second semiconductor region, and a fourth semiconductor region of the first conductivity type partially surrounded by the second semiconductor region. At low reverse biases between a cathode electrode and an anode electrode, the behavior of the device is determined by the pn junction between the first and second semiconductor regions. As the reverse biasing increases, the depletion layers of that junction will reach the fourth semiconductor region, but the reverse bias at this time is insufficient to break down that junction. A further increase of reverse bias causes breakdown of the pn junction between the third and fourth semiconductor regions. This effect is achieved by suitable impurity concentrations in the semiconductor regions. A plurality of fourth semiconductor regions may be provided, and a bi-directional structure can be obtained by providing a polarity reversed structure with the first semiconductor region in common.

Blue/green pn junction electroluminescence from ZnSe‐based multiple quantum‐well structures

Abstract: The successful p doping of ZnSe by substitutional nitrogen using a plasma cell incorporated into the molecular beam epitaxy chamber has led to the development of electroluminescent devices based on carrier injection at a pn junction. The light emitting diode structures described here are grown on a GaAs substrate using a tetragonally distorted (In,Ga)As buffer layer to provide lattice matching between the substrate and the active II–VI region. The result of the incorporation of the buffer layer is an essentially dislocation‐free active region. The letter discusses optical properties as well as the x‐ray and transmission electron microscopy characterization of the quantum well device structures.

Electrically programmable antifuse using metal penetration of a junction

Abstract: An improved antifuse uses metal penetration of either a P-N PN junction or a Schottky diode. The P-N junction or Schottky diode (11), is contacted by a diffusion barrier (14) such as TiN, W, Ti-W alloy, or layers of Ti and Cr, with a layer (15) of a metal such as Al, Al-Cu alloy, Cu, Au, or Ag on top of the diffusion barrier. The junction (11) is surrounded by an electrical isolation structure (13) which also serves to thermally isolate the said junction. When this junction is stressed with voltage pulse producing a high current density, severe joule heating occurs resulting in metal penetration of the diffusion barrier and the junction to form a metal contact (15'). The voltage drop across the junction decreases by about a factor of ten after the current stress and is stable thereafter. Alternatively, a shallow P-N junction in a silicon substrate is contacted by a layer of metal that forms a silicide, such as Ti, Cr, W, Mo, or Ta. Stressing the junction with a voltage pulse to produce a high current density results in the metal penetrating the junction and reacting with the substrate to form a silicide.

Capacitive memory having a PN junction writing and tunneling through an insulator of a charge holding electrode

Abstract: A semiconductor memory device whose data hold condition is not affected due to degradation of transistor characteristics by minimizing leakage charges and the switching transistor size. The semiconductor memory device employs memory cell charge holding electrode that is insulated from the remaining memory cell structure, particularly the switching transistor source drain leakage path. The write element controls the tunneling of charge carriers through such insulator to the charge holding portion or capacitor electrode, for writing data. Particularly, the write element includes a PN junction for various advantages.

ZnSe based multilayer pn junctions as efficient light emitting diodes for display applications

Abstract: pn junction characteristics and LED action in ZnSe‐based multilayers grown by molecular beam epitaxy is demonstrated. In particular, we show that (Zn,Cd)Se/ZnSe/Zn(S,Se) structures containing (Zn,Cd)Se quantum wells, grown on p‐type GaAs epilayers, and designed with a heavily doped n+‐ZnSe top contact layer may be appropriate for display device applications in the blue‐green portion of the spectrum.

Visible Electroluminescence from P-Type Crystalline Silicon/Porous Silicon/N-Type Microcrystalline Silicon Carbon PN Junction Diodes

Abstract: We have fabricated p-type crystalline silicon/porous silicon/microcrystalline silicon carbon pn junction diodes and demonstrated current-induced visible light emission. We observed two kinds of electroluminescence; one was a weak white emission at a forward current of about 90 mA, and the other was a strong orange-red one at a forward current from about 200 to 619 mA.

Ultra-shallow junction formation using silicide as a diffusion source and low thermal budget

Abstract: Ultra-shallow p/sup +//n and n/sup +//p junctions were fabricated using SADS (silicide-as-diffusion-source) and ITS (ion-implantation-through-silicide processing) of 45-nm CoSi/sub 2/ films (3.5 Omega / Square Operator ) using a low thermal budget. The best junctions of either type were made by moderate 10-s RTA (rapid thermal annealing) at 800 degrees C, where the total junction depth, counting the silicide thickness, is believed to be under 60 nm. Diffusion-limited current predominated down to 50 degrees C in junctions made under these conditions. The initial implantation energy had only a minor effect on the junction leakage, where shallower implants required slightly higher temperatures to form low leakage diodes, resulting in diodes which were somewhat more susceptible to shorting during silicide agglomeration at high temperatures. The ITS scheme, where dopant is implanted slightly beyond the silicide, gives an equally low leakage current. Nevertheless, the ITS scheme gives deeper junctions than the SADS process, and it is difficult to control the position of the ITS junction due to silicide/silicon interface fluctuations. >

Organic solar cell based on multistep charge separation system

Abstract: The p‐n heterojunction organic solar cell composed of n‐type multilayer of two different perylene pigments and p‐type metal‐free phthalocyanine pigment was investigated. A downward potential step of the conduction band in the n‐type multilayer enhanced the photocurrent quantum efficiency by a factor of about 3, owing to the suppression of the charge recombination of photogenerated carriers in the vicinity of the p‐n junction. The multistep charge separation system consisting of energetically well‐arranged organic thin layers was shown to offer an effective system to obtain highly efficient organic solar cells.

Bonded silicon‐on‐sapphire wafers and devices

Abstract: Silicon‐on‐sapphire (SOS) has been prepared by direct wafer bonding. The silicon layer was thinned to about 10 μm by mechanical grinding and chemical etching. P‐N junction diodes were fabricated in the bonded SOS and compared with epitaxially grown SOS. The reverse bias leakage current was almost 15× less in the bonded SOS. A generation lifetime of 10 μs can be estimated from the junction leakage. The effects of processing temperatures on the bonded SOS were also studied.

Arsenic cluster dynamics in doped GaAs

Abstract: We have studied the formation of As precipitates in doped GaAs structures that were grown by molecular beam epitaxy at low substrate temperatures and subsequently annealed. We find that the As precipitates form preferentially on the n side of such fabricated GaAs pn junctions. As the coarsening process proceeds, there is a gradual increase in the amount of As in precipitates in the n‐GaAs region and a decrease in the p‐GaAs region; the depletion region between the pn junction becomes free of As precipitates. These observations can be understood qualitatively based on the charge states of the As interstitial and using thermodynamic arguments in which the crystal attempts to minimize the chemical potential during the anneal. The presence of the excess As results in a stable Be profile even to anneals of 950 °C. Finally, a temperature cycling technique to grow arbitrarily thick GaAs epilayers containing As precipitates was demonstrated.

Electroluminescence from bipolar resonant tunneling diodes

Abstract: The incorporation of an AlAs/GaAs resonant tunneling structure inside a GaAs p‐n junction leads to strong quantum‐well electroluminescence originating from electron and hole tunneling into the resonant tunneling structure. A large peak‐to‐valley ratio of 10:1 in the electroluminescence intensity is achieved at the electron resonance at 4.2 K, which decreases but persists (1.45:1) at room temperature. Resonant tunneling of holes is also apparent from the electroluminescence at low temperature.

Semiconductor rectifier having high breakdown voltage and high speed operation

Abstract: A semiconductor rectifier having a high breakdown voltage and a high speed operation is provided, which comprises a semiconductor substrate including a first semiconductor layer of one conductivity type and a second semiconductor layer of one conductivity type provided on the first semiconductor layer, a third semiconductor layer of an opposite conductivity type having a depth D and formed in the second semiconductor layer to provide a pn junction therebetween, the third semiconductor layer defining a plurality of exposed regions of the second semiconductor layer, each of the plurality of exposed regions of the second semiconductor layer having a width W, a relation between the depth D and the width W being given by D≧0.5W, and a metal electrode provided on the substrate surface.

MOS-gated thyristor

Abstract: A semiconductor device includes a thyristor (4,5,8,9) in which connection is made to the cathode region (9) of the thyristor by means of an MOS structure. The MOS structure is provided by a fifth region (11) forming a pn junction with the cathode region (9), a sixth region (13) in contact with the cathode electrode (C) and forming a pn junction (14) with the fifth region (11), and an insulated gate (15) overlying a conduction channel area (110) of the fifth region (11) for defining a gateable conductive path for charge carriers into the cathode region (9) to initiate thyristor action. The conductive path is thus controlled by the voltage applied to the insulated gate (15), enabling the flow of charge carriers to the cathode region (9) to be stemmed by application of an appropriate gate voltage oxide. The fifth region (11) is electrically connected to provide a path for extraction of charge carriers during turn-off of the thyristor, thereby improving the controllable current capability of the thyristor.

Investigation of Thermal Coefficient for Polycrystalline Silicon Thermal Sensor Diode

Abstract: Thermal sensors utilizing p-n junction diodes built into the polycrystalline silicon layer are developed. The effective factors influencing the thermal coefficient of polycrystalline silicon thermal sensor diodes are clarified. It is found that diodes with a light boron dose have a larger thermal coefficient than those with a heavy boron dose. The plural p-n diodes connected with more cascade series number have a larger thermal coefficient than ones with less cascade series number. The periphery of the thermal sensor seems to have little effect on the thermal coefficient. In addition, the thermal coefficient will become higher as a larger forward current is selected. The thermal coefficient of the sensor with a boron dose of 1×1015 cm-2 will reach a saturation value of -2 mV/K when the forward current is above 2 µA.

Multistep field plates for high-voltage planar p-n junctions

Abstract: Multistep field plates are often used to improve the blocking capability of planar p-n junctions. The electric field at the semiconductor surface below the field plate peaks, however, at every edge of the dielectric. In order to achieve the highest possible breakdown voltage at a given number of steps in the dielectric, their heights have to be adjusted as to equalize the corresponding peak fields. For this purpose, an analytical model has been developed, which relates the peak field to the geometrical and physical parameters of the structure. From this, a systematic method has been derived for designing multistep field plates with equal peak fields at the steps. By applying this method to a planar p-n junction the blocking capability was increased from 23% without field plates to more than 89% of the bulk breakdown voltage. >

Improved crystalline quality of Si1−xGex formed by low‐temperature germanium ion implantation

Abstract: Improvement of crystalline quality in Si1−xGex formed by germanium ion implantation has been found. End‐of‐range defects were drastically reduced in number by lowering the substrate temperature during implantation with doses on the order of 1016 cm−2. This improvement was confirmed by electrical characterization of p‐n junctions formed in the SiGe layer as well as by transmission electron microscopy.

InAs p‐n diodes grown on GaAs and GaAs‐coated Si by molecular beam epitaxy

Abstract: InAs p‐n diodes have been grown on GaAs and GaAs‐coated Si substrates by molecular beam epitaxy. Transmission electron microscopy cross sections of the epilayers demonstrate a good structural quality. Photodiodes were obtained using a Be (p=5×1016 cm−3) and Si (n=3×1016 cm−3) doping scheme. The diodes exhibited 77 K zero‐bias resistance area products of 2200 Ω cm2 for InAs/GaAs and 1500 Ω cm2 for InAs/GaAs/Si. The spectral response of the devices peaked at 2.95 μm with Johnson noise limited detectivities D* of 7.0×1011 cm Hz1/2/W for InAs/GaAs and 5.8×1011 cm Hz1/2/W for InAs/GaAs/Si. These results clearly demonstrate the feasibility of the monolithic integration of InAs infrared detectors and GaAs or Si read‐out electronics.

Electrically detected magnetic resonance of a transition metal related recombination center in Si p–n diodes

Abstract: A hyperfine structure has been observed by electrically detected magnetic resonance from a Si p–n diode. From the hyperfine splitting, and the natural abundance of the interacting I=1/2 nuclear species, the recombination center is found to be consistent with a platinum complex.

Increased thermal generation rate in GaAs due to electron‐beam metallization

Abstract: Leakage currents due to thermal generation in a reverse‐biased p‐n junction can be accurately monitored by measuring the capacitance recovery transient of a p‐n‐p structure. Using this technique, it has been demonstrated that the thermal generation in the bulk depletion region of GaAs p‐n junctions grown by molecular beam epitaxy can be as much as three orders of magnitude greater for samples metallized in electron‐beam evaporators as compared to thermal evaporators. The increase in thermal generation rate is shown to be dependent upon the device area exposed during the evaporation, the type of metal initially evaporated onto the sample, the growth conditions during molecular beam epitaxy, and the depth of the p‐n junction from the semiconductor surface.

Selective Metal Deposition on Silicon Substrates

Abstract: In order to delineate n/p junctions at (100) or cleaved Si faces, different plating processes (electroless in the dark or under illumination with photons of different energy) have been investigated. The effects of metal cation concentration, of illumination upon the formation of deposits onto n‐ or p‐type silicon substrates, and p/n Si junctions have been studied. The role of an interfacial oxide layer has been emphasized. It is shown that platinum or palladium electroless deposition can be carried out on p‐Si under ultraviolet illumination, in solutions free of . By contrast, in presence of a Si p/n junction, platinum, and palladium are only deposited on n‐type areas. Models are proposed to explain the observed selective deposition.

Semiconductor rectifying diode with pn geometry

Abstract: A semiconductor rectifying diode includes a first semiconductor region of one conductivity type, a plurality of third semiconductor regions of the other conductivity type provided on one surface of said first semiconductor region to be spaced a distance W, and a main electrode provided on said one main surface to in ohmic contact with said first semiconductor region and in contact with said third semiconductor regions through the Schottky barrier. To reduce reverse leakage current a relation of 2wo

New doped multiple‐quantum‐well avalanche photodiode: The doped barrier Al0.35Ga0.65As/GaAs multiple‐quantum‐well avalanche photodiode

Abstract: The performance of doped barrier, multiple‐quantum‐well avalanche photodiodes (MQW APDs) is reported for the first time. Investigations are presented for a 800 A/200 A MQW Al0.35Ga0.65As/GaAs undoped structure with a p‐n junction in each barrier. The devices exhibit low dark currents, low breakdown voltages (−10 V), and gains up to 20 for electron injection. Noise measurements show an enhancement of the electron to hole ionization rates ratio, α/β, to values between 50 and 12.5 for gains up to 5, and to 5 for gains above 5. α/β is enhanced by a factor of 6 over the bulk GaAs, and a factor of at least 2 over the simple MQW APD. The particular design we report provides medium gain and very‐low‐noise characteristics at low bias voltage. These experimental noise results are the best reported so far for AlGaAs/GaAs MQW APD structures.

Semiconductor power device having walls of an inverted mesa shape to improve power handling capability

Abstract: A semiconductor device of vertical arrangement includes an anode region formed of a first semiconductor substrate and a second semiconductor substrate joined with the first semiconductor substrate. The first semiconductor substrate forms a high-resistance layer with a predetermined impurity density, and the second semiconductor substrate forms a low-resistance layer whose impurity density is higher than that of the high-resistance layer. A PN junction is formed inside the first semiconductor substrate. The periphery of the first semiconductor substrate including the PN junction is configured in an inverted mesa structure and coated with an insulation material. With this arrangement, the semiconductor device has a high withstand voltage and enables an employment of a large diameter wafer.

Method of forming semiconductor device including a CMOS structure having double-doped channel regions

Abstract: A semiconductor device has, in one embodiment, a p type insulated gate field effect transistor formed in an n type well formed on a semiconductor substrate and an n type insulated gate field effect transistor formed in a p type well formed on the semiconductor substrate. Each of the p type and n type insulated gate-field effect transistors has a composite impurity layer under its gate electrode in a surface portion of its associated well. The composite impurity layer includes a first doped layer of a p type and a second doped layer of an n type adjacent thereto to form a pn junction layer therebetween, while the composite impurity layer includes a first doped layer of a p type and a second doped layer of a p type adjacent thereto to form a junction layer therebetween having a p type impurity concentration lower than that of the p type well.

Diamond n-type semiconductor diamond p-n junction diode

Abstract: A diamond n-type semiconductor including a substrate and a phosphorus element-doped diamond thin film disposed on the substrate. The diamond thin film is deposited by vaporizing a solution comprising a liquid organic compound as the diamond material with diphosphorus pentoxide (P2 O5) dissolved therein, and subjecting the resultant gas to a hot filament CVD method.

Effects of displaced p-n junction of heterojunction bipolar transistors

Abstract: Two-dimensional simulations that demonstrate the effects of displacements of the p-n junctions from the heterojunctions of symmetrical Al/sub 0.28/Ga/sub 0.72//GaAs double-heterojunction bipolar transistors (DHBTs) are reported. When the emitter and/or collector p-n junctions do not coincide with the AlGaAs/GaAs heterojunctions, the electrical characteristics are shown to be drastically altered due to changes in the potential profiles and to changes in recombination rates both in the neutral base and in the space-charge region of the emitter. The effects of a small displacement of the p-n junction from the emitter-base or the base-collector heterojunctions are examined and results for current gain beta and cutoff frequency f/sub T/ are given that demonstrate enhanced performance for DHBTs with p-n junctions that are not coincident with the heterojunctions. >