Showing papers on "p–n junction published in 2002"

Silicon-on-insulator diodes and ESD protection circuits

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and then also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits. The proposed gated diode and non-gated diode can be fully process-compatiable to general partially-depleted or fully-depleted silicon-on-insulator CMOS processes.

Semiconductor device and its manufacturing method

Abstract: PROBLEM TO BE SOLVED: To provide a high-breakdown-voltage semiconductor device for preventing a leakage current from easily flowing with the segregation layer of Ge as a path, and to provide a method for manufacturing the semiconductor device. SOLUTION: This mesa-type semiconductor device has a thermal oxide film 16, that protects a pn junction surface, an n-type silicon layer 13, a p-type Si film 12 that is laminated and formed on the n-type silicon layer, and a p-type SiGe film 11 that is laminated and formed on the p-type Si film. In this case, the p-type SiGe film 11 is separated from the n-type silicon layer 13 by the p-type Si film 12, thus preventing a Ge segregation layer 15 from being generated on a pn-junction surface 14.

Rectifying characteristic in all-perovskite oxide film p-n junction with room temperature ferromagnetism

Abstract: We fabricated an all-perovskite oxide p-n junction comprised of hole-doped (p-) manganite La0.9Ba0.1MnO3 and electron-doped (n-) titanate Sr0.99La0.01TiO3 films. The junction showed good rectifying properties at both room temperature and low temperature in a simple structure without inserting an insulating layer. By optimizing junction fabrication conditions, a thin La0.9Ba0.1MnO3 layer in the junction exhibited room temperature ferromagnetism and metallic conduction, which may be modulated by carrier injection from the n-type layer under an electric field. These results indicate that this p-n junction may be developed into functional, strongly correlated electronic devices able to work at room temperature.

Characterization of the bonding strength and interface current of p-Si/n-InP wafers bonded by surface activated bonding method at room temperature

Abstract: Bonding between p-Si and n-InP was performed through the surface activated bonding method at room temperature. Tensile results show that the samples were visibly separated from the bonded interface, indicating a weak bonding strength. The cause of the weak bonding strength was intensively investigated. Consistent results between x-ray photoelectron spectroscopy and atomic force microscope investigations show that a weak phase of indium is terminated on the InP due to the depletion of phosphorus in the sputtered surface. Existence of indium layers on the debonded Si surface indicate that the samples were separated from the interface of In/InP, but not across the bonded interface of Si and indium. Typical pn junction current–voltage behavior indicates no high resistance interface layer that can withstand the flow of current through the interface. Remarkably, sputtering time as well as energy dependence on the interface current is found to be due to the accumulation of sputtering induced defects.

Lateral DMOS structure with lateral extension structure for reduced charge trapping in gate oxide

Abstract: A high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage The semiconductor device comprising a semiconductor body, an extended drain region formed in the semiconductor body, source and drain pockets, a top gate forming a pn junction with the extended drain region, an insulating layer on a surface of the semiconductor body and a gate formed on the insulating layer In addition, a higher-doped pocket of semiconductor material is formed within the top gate region that has a higher integrated doping than the rest of the top gate region This higher-doped pocket of semiconductor material does not totally deplete during device operation Moreover, the gate controls, by field-effect, a flow of current through a channel formed laterally between the source pocket and a nearest point of the extended drain region

Two-dimensional p-n junction under equilibrium conditions

Abstract: For the first time, the idea of a two-dimensional p-n junction formed as a contact between two regions of a quantum-dimensional film with different types of conductivity is proposed. Under equilibrium conditions, the potential distribution and the potential-barrier height were determined. An expression was derived for the width of the surface-charge layer, which depends linearly on the contact potential (external bias) in contrast to the three-dimensional case. The specific capacitance of a two-dimensional p-n junction is virtually independent of the applied potential and depends only on the ambient permittivity. It was shown that, in spite of the fact that the junction electric field is screened only slightly, the Schottky approximation can be used for a description of the properties of such p-n junctions.

Semiconductor light emitting element

Abstract: PROBLEM TO BE SOLVED: To provide a small-sized semiconductor light emitting element having high directivity of the emitted light and a high output. SOLUTION: In the semiconductor light emitting element having a pn junction, the part of a light extracting unit is covered with a light shielding substance having low conductivity. The electric resistance of the substance is 10 Ωm or more. The substance contains one or more kinds of powder selected from the group consisting of a metal and a pigment. The powder of the metal contains at least one kind selected from the group consisting of Al, Cu, Ag, Au, PT, Ti, Ni, Sn, Pb, Mg, Zn, Fe, Co and Cr. The powder has a plate-like shape having a thickness within a range of 0.001 to 10 μm, and a length in a range of 0.01 to 100 μm.

New Concept for ZnTe-Based Homoepitaxial Light-Emitting Diodes Grown by Molecular Beam Epitaxy

Abstract: ZnCdSeTe/ZnMgSeTe quasi-quaternary light-emitting devices emitting in the green-yellow wavelength region grown on ZnTe substrates are promising for efficient green light emitters. To solve the n-type conductivity problem in ZnTe-related materials, Cl-doped ZnMgSeTe quasi-quaternary layers which consisted of very thin ZnSe and ZnMgSeTe were studied and an n-type ZnMgSeTe quasi-quaternary layer with high carrier concentration of 9.4 × 10 17 cm -3 was observed. The low-temperature luminescence properties of ZnCdSeTe/ZnMgSeTe quasi-quaternary quantum wells were studied and sharp emission from the ZnCdSeTe quantum well layers with FWHM of 8 meV was observed. ZnCdseTe/ZnMgSeTe quasi-quaternary p-n junction light-emitting diodes (LEDs) were fabricated and green emission from the LED structure was observed at room temperature.

Trench structure having one or more diodes embedded therein adjacent a PN junction and method of forming the same

Abstract: In accordance with an embodiment of the invention, a semiconductor structure includes a semiconductor region having a P-type region and a N-type region forming a PN junction therebetween. A first trench extends in the semiconductor region adjacent at least one of the P-type and N-type regions. The first trench includes at least one diode therein.

Oxide semiconductor pn junction device

Abstract: PROBLEM TO BE SOLVED: To solve a problem that, since GaN used as a device material for ultraviolet-light detection has photosensitivity to visible light and an ultraviolet range, a device needs to remove unnecessary light by using an optical filter and make only ultraviolet light having a specified wavelength incident on a GAN detector. SOLUTION: A pn junction device comprises a Zn x Mg 1-x O (0.7 x Mg 1-x O single crystal thin film as a polycrystalline or amorphous film and annealed for epitaxial growth and contains Li ions exhibiting p-type electric conduction, or an amorphous InGaO 3 (ZnO) m (m: an integer between 1 and 50) which is formed of a ZnRh 2 O 4 film and deposited on the pn junction device and ITO film and shows n-type electric conduction, and an amorphous NiO thin film or ZnRh 2 O 4 thin film which is deposited on InGaO 3 (ZnO) m and shows p-type electric conduction. COPYRIGHT: (C)2004,JPO

Direct imaging of the depletion region of an InP p-n junction under bias using scanning voltage microscopy

Abstract: We directly image an InP p–n junction depletion region under both forward and reverse bias using scanning voltage microscopy (SVM), a scanning probe microscopy (SPM) technique. The SVM results are compared to those obtained with scanning spreading resistance microscopy (SSRM) measurements under zero bias on the same sample. The SVM and SSRM data are shown to agree with the results of semiclassical calculations. The physical basis of the SVM measurement process is also discussed, and we show that the measured voltage is determined by the changes in the electrostatic potential and the carrier concentration at the SVM tip with and without the applied bias.

Lateral p-n Junction in Modulation Doped AlGaAs/GaAs

Abstract: Lateral p-n junctions have advantages for monolithic integration with other electronic devices and can improve the modulation bandwidth of light emitting devices. An alternative approach to existing fabrication methods is presented. Simulations show that recombination takes place inside the undoped channel and that the lateral position of the junction can be defined via etching. In order to demonstrate the concept, a simple device was fabricated and characterized.

Edmos device having a lattice type drift region

Abstract: The present invention provides an EDMOS (extended drain MOS) device having a lattice type drift region and a method of manufacturing the same. In the case of n channel EDMOS(nEDMOS), the drift region has a lattice structure in which an n lattice having a high concentration and a p lattice having a low concentration are alternately arranged. As a drain voltage is applied, a depletion layer is abruptly extended by a pn junction of the n lattice and the p lattice, so that the entire drift region is easily depleted. Therefore, a breakdown voltage of the device is increased, and an on resistance of the device is decreased due to the n lattice with high concentration.

Depth and lateral extension of ion milled pn junctions in CdxHg1−xTe from electron beam induced current measurements

Abstract: Ion milling has been used to convert molecular beam epitaxy vacancy-doped CdxHg1−xTe from p- to n-type. Electron beam induced current and remote electron beam induced current (REBIC) measurements have been performed to study the pn junction depth and lateral extension dependence on the milling time, milling current, and vacancy concentration. The conversion depth is linear with the milling time and current and inversely proportional to the vacancy concentration in layers thinner than 10 μm. This shows that filling of Hg vacancies in this region during conversion is limited by the rate of supply of extra Hg from the milling. The lateral extension also increases linearly with the milling time, the ratio of the lateral extension to the depth being ∼0.5. One can therefore use REBIC on the top surface to determine the junction depth, which greatly simplifies the measurement and does not destroy the diodes.

Characterization of a diamond p-n junction using electron-beam-induced current and cathodoluminescence

Abstract: We have characterized a diamond p-n junction by means of electron-beam-induced current (EBIC) and cathodoluminescence (CL). The diamond p-n junction was fabricated by growing a B-doped p-type layer and a P-doped n-type layer on the {111} diamond substrate by microwave plasma enhanced chemical vapor deposition. The cross section of p-n junction was revealed by the mesa etching. The substrate, B- and P-doped layers were distinguished by CL spectra. The EBIC profiles across the p-n junction were recorded under various reverse bias conditions. These data confirmed that the p-n junction was actually formed at the interface between B- and P-doped layers. The energy-band profile suggests that the carrier concentration of P-doped layer is more than ten times higher than that of B-doped layer. The observed results strongly support the fact that the UV luminescence is emitted from the p-n junction region in diamond light-emitting diode.

Attempts of Homo p–n Junction Formation in ZnS by Impurity Co‐Doping with Vapor Phase Epitaxy

Abstract: ZnS p-n homo junctions have been obtained for the first time with epitaxially grown layers having the structures of n-ZnS:In/p-ZnS:In, Ag, N/p-GaAs and p-ZnS:In, Ag, N/n-ZnS:In/n-GaAs. Both of these structures showed rectifying behavior which is expected for p-n junctions. The forward voltage of 3.7 V where current increases rapidly corresponds to the band gap energy of ZnS at room temperature. For reverse bias, some samples having p-ZnS:In, Ag, N/n-ZnS:In/n-GaAs structure showed backward diode type character.

Method for wet etching of high k thin film at low temperature

Abstract: The present invention discloses an electrode structure of a light emitted diode and manufacturing method of the electrodes. After formed a pn junction of a light emitted diode on a substrate, a layer of SiO2 is deposited on the periphery of the die of the LED near the scribe line of the wafer, then a transparent conductive layer is deposited blanketly, then a layer of gold or AuGe etc. is formed with an opening on the center of the die. After forming alloy with the semiconductor by heat treatment to form ohmic contact, a strip of aluminum (Al) is formed on one side of the die on the front side for wire bonding and to be the positive electrode of the LED. The negative electrode is formed on the substrate by metal contact. Another form of the electrode structure of the present invention is making both the positive and negative electrodes on the front side of the LED by etching the p-type semiconductor of the pn junction and forming a strip of negative electrode on the n-type semiconductor, the positive electrode is formed on the p-type semiconductor.

Overvoltage protection device

Abstract: A semiconductor device has a PN junction between first and second regions of the device in which in the intended operation of the device reverse breakdown of the junction occurs. The first region is of lower impurity concentration than the second region and a first buried region of the same conductivity type as and of higher impurity concentration than the first region is provided in the first region adjacent to the junction. A second buried region of the same conductivity type as and of higher impurity concentration than the first buried region is provided in the first buried region and one of the first and second buried regions is formed with a plurality of separate regions of small area arranged so that reverse breakdown of the junction preferentially occurs through the second buried region.

Method for manufacturing semiconductor device

Abstract: The present invention is characterized by providing epitaxial growth of a semiconductor layer on the surface of a wafer not provided with mirror finishing and having irregularity, introducing impurities having different conductivity type in the epitaxially grown semiconductor layer to form at least a pn junction, and further providing rapid thermal anneal by rapid heating-up and rapid cooling-down in any step in the manufacturing process By so processing, there can be obtained a semiconductor device having high speed switching characteristics in stable manner without causing problems in manufacturing process such as diffusion of heavy metal or irradiation of corpuscular ray

Passivation of HgCdTe p-n diode junction by compositionally graded HgCdTe formed by annealing in a Cd/Hg atmosphere

Abstract: Cadmium telluride (CdTe) is being widely used for passivating the HgCdTe p-n diode junction. Instead of CdTe, we tried a compositionally graded HgCdTe as a passivation layer that was formed by annealing an HgCdTe p-n junction in a Cd/Hg atmosphere. During annealing, Cd diffuses into HgCdTe from the Cd vapor, while Hg diffuses out from HgCdTe, forming compositionally graded HgCdTe at the surface. The Cd mole fraction at the surface was constant regardless of the annealing temperature in the range of 250-350°C. Capacitance versus voltage (C-V) curves for p-type HgCdTe that were passivated with compositionally graded HgCdTe formed by Cd/Hg annealing at 260°C showed a smaller flat-band voltage than the one passivated by thermally deposited CdTe, indicative of the better quality of the passivation. A long-wave infrared (LWIR) HgCdTe p-n junction diode passivated by compositionally graded HgCdTe showed about a one order of magnitude smaller RdA value than the one passivated by thermally deposited CdTe, confirming the effectiveness of the compositionally graded HgCdTe as a passivant.

Sequential mesa avalanche photodiode capable of realizing high sensitization and method of manufacturing the same

Abstract: A sequential mesa type avalanche photodiode (APD) comprises a semiconductor substrate and a sequential mesa portion formed on the substrate. In the sequential mesa portion, a plurality of semiconductor layers, including a light absorbing layer and a multiplying layer, are laminated by epitaxial growth. In the plurality of semiconductor layers, a pair of semiconductor layers forming a pn junction is included. The carrier density of a semiconductor layer which is near to the substrate among the pair of semiconductor layers is larger than the carrier density of a semiconductor layer which is far from the substrate among the pair of semiconductor layers. In the APD, light-receiving current based on movement of electrons and positive holes generated in the sequential mesa portion when light is incident from the substrate toward the light absorbing layer is larger at a central portion than at a peripheral portion of the sequential mesa portion.

Heteroepitaxial PbTe-on-Si pn-junction IR-sensors: correlations between material and device properties

Abstract: Epitaxial IV–VI narrow band gap semiconductors on Si (1 1 1) substrates exhibit high structural quality despite the large lattice and thermal expansion mismatch. Test arrays with photovoltaic n + –p PbTe infrared sensors (cut-off wavelength 5.5 μm at 80 K ) of different sizes were fabricated and analyzed. The sensitivities are generation–recombination (g–r)-limited in the 90– 200 K range. The g–r carrier lifetimes in the depletion region are determined from the R 0 A -products (inverse noise current densities). The corresponding carrier diffusion lengths are correlated with the material properties, namely low-temperature saturation Hall mobilities and X-ray rocking curve line widths. It turns out that all these parameters are determined by the density of the threading dislocations, and each dislocation crossing the active area gives rise to a shunt resistance. At lower temperatures, the R 0 A -products saturate and the ideality factors increase above a value of 2. This behaviour suggests that, as in the case of Schottky barriers of metal–semiconductor junctions of IV–VIs, fluctuations of the built-in electric field occur near the dislocation cores which cross the active areas of the devices.

GaN p-n junction diode formed by Si ion implantation into p-GaN

Abstract: 28Si+ implantation into Mg-doped GaN, followed by thermal annealing in N2 was performed to achieve n+-GaN layers. The carrier concentrations of the films changed from 3×1017 (p-type) to 5×1019 cm−3 (n-type) when the Si-implanted p-type GaN was properly annealed. Specific contact resistance (ρc) of Ti/Al/Pt/Au Ohmic contact to n-GaN, formed by 28Si+ implantation into p-type GaN, was also evaluated by transmission line model. It was found that we could achieve a ρc value as low as 1.5×10−6 Ω cm2 when the metal contact was alloyed in N2 ambience at 600 °C. Si-implanted GaN p–n junction light-emitting diodes were also fabricated. Electroluminescence measurements showed that two emission peaks at around 385 and 420 nm were observed, which could be attributed to the near band-edge transition and donor-to-acceptor transition, respectively.

Characterizing an implanted Si/Si p–n junction with lower doping level by combined electron holography and focused-ion-beam milling

Abstract: A Si/Si p–n junction with very low doping level was made via a standard device fabrication process by implanting As ions at 25 keV into a p-type Si substrate with a boron concentration of 1015 cm−3, followed by heat annealing at 1035 °C for 33 s. To characterize this junction, a pair of 45° wedge-shape cross sections was prepared simultaneously by focused-ion-beam milling and examined using off-axis electron holography. The reconstructed phase images clearly show the phase shift induced by the electrostatic potential drop across the p–n junction, indicating that the junction has been mapped successfully. Quantitative measurements from the phase images give the potential values of 12.21±0.40 and 11.50±0.27 V, respectively, for the n- and p-type sides of the junction, 0.71±0.05 V for the potential drop across the junction and 50.10±3.88 nm for the total electric dead layer thickness. This work demonstrates that electron holography is a powerful technique for characterizing low dopant level p–n junctions in ...

Highly Efficient Blue–Ultraviolet Photodetectors Based on II–VI Wide‐Bandgap Compound Semiconductors

Abstract: II-VI ZnSe (binary) and ZnSSe (ternary) widegap compound semiconductor based photovoltaic devices (p-i-n and avalanche photodiodes (APDs)) are developed for the blue-violet (460-400 nm) optical wavelength region by molecular beam epitaxial (MBE) growth. The ternary compound ZnSSe p-i-n structure photodiodes, grown with complete lattice matched condition on GaAs substrates, exhibit high external quantum efficiencies of 80-70% in the blue-violet optical region with extremely low dark currents (∼pA/mm 2 ), These diodes reveal stable and long-lived operation at 300 K. Also presented is ZnSe and ZnSSe based blue-violet APD devices, fabricated by precise defect control and process techniques. This new device has revealed large signal gain (G) of G = 50 for ZnSe, and G = 60 for the ZnSSe APD device under high electric field strength of (0.8-1.1) × 10 6 V/cm. Important device parameters, ionization coefficients of photo-injected electrons and holes, and device stability are also discussed.

High-energy (MeV) Al and B ion implantations into 4H-SiC and fabrication of pin diodes

Abstract: High-energy (MeV) implantation of Al+ or B+ into 4H-SiC epilayers has been investigated. A 3 μm deep pn junction was formed by multiple-step Al+ or B+ implantation with implantation energies up to 6.2 or 3.4 MeV, respectively. Rutherford backscattering channeling and cross-sectional transmission electron microscopy analyses have revealed residual damages in the implanted layers even after high-temperature annealing at 1600–1800 °C. Nevertheless, high electrical activation ratios over 90% have been achieved for both Al+- and B+-implanted layers by annealing at 1800 °C. Mesa pin diodes with a 15-μm-thick i layer formed by MeV implantation have exhibited high breakdown voltages of 2860–3080 V. The reverse characteristics of diodes have been substantially improved by increasing annealing temperature up to 1800 °C. The diode performance is discussed with the results of deep level analyses near the junctions.

InGaN/GaN MQW p–n junction photodetectors

Abstract: InGaN/GaN multiquantum well (MQW) p–n junction photodetectors with semi-transparent Ni/Au electrodes were fabricated and characterized. It was found that the fabricated InGaN/GaN MQW p–n junction photodetectors exhibit a 20 V breakdown voltage and a 3.5 V forward 20 mA turn on voltage. It was also found that the photocurrent to dark current contrast ratio is higher than 105 when a 0.4 V reverse bias was applied to the InGaN/GaN MQW p–n junction photodetectors. Furthermore, it was found that the maximum responsivity was 1.28 and 1.76 A/W with a 0.1 and 3 V applied reverse bias, respectively.