Showing papers on "p–n junction published in 2006"

ZnO p-n junction light-emitting diodes fabricated on sapphire substrates

Abstract: A ZnO p-n junction light-emitting diode (LED) was fabricated on a-plane Al2O3 substrate by plasma-assisted molecular-beam epitaxy. NO plasma activated by a radio frequency atomic source was used to grow the p-type ZnO layer of the LED. The current-voltage measurements at low temperatures showed a typical diode characteristic with a threshold voltage of about 4.0V under forward bias. With increasing temperature, the rectification characteristic was degraded gradually, and faded away at room temperature. Electroluminescence band of the ZnO p-n junction LED was located at the blue-violet region and was weakened significantly with increase of temperature. This thermal quenching of the electroluminescence was attributed to the degradation of the diode characteristic with temperature.

Carbon Nanotube p-n Junction Diodes

Abstract: We demonstrate a single-walled carbon nanotube p-n junction diode device. The p-n junction is formed along a single nanotube by electrostatic doping using a pair of split gate electrodes. By biasing the two gates accordingly, the device can function either as a diode or as an ambipolar field-effect transistor. The diode current–voltage characteristics show forward conduction and reverse blocking characteristics, i.e., rectification. For low bias conditions, the characteristics follow the ideal diode equation with an ideality factor close to one.

Breakthroughs in Improving Crystal Quality of GaN and Invention of the p–n Junction Blue-Light-Emitting Diode

Abstract: Marked improvements in the crystalline quality of GaN enabled the production of GaN-based p–n junction blue-light-emitting and violet-laser diodes. These robust, energetically efficient devices have opened up a new frontier in optoelectronics. A new arena of wide-bandgap semiconductors has been developed due to marked improvements in the crystalline quality of nitrides. In this article, we review breakthroughs in the crystal growth and conductivity control of nitride semiconductors during the development of p–n junction blue-light-emitting devices. Recent progress mainly based on the present authors' work and future prospects of nitride semiconductors are also discussed.

Electroluminescence from ZnO nanowire/polymer composite p-n junction

Abstract: The characteristics of a hybrid p-n junction consisting of the hole-conducting polymer poly(3,4-ethylene-dioxythiophene)-poly(styrene-sulfonate) (PEDOT/PSS) and n-ZnO nanorods grown on an n-GaN layer on sapphire are reported. Spin coating of polystyrene was used to electrically isolate neighboring nanorods and a top layer of transparent conducting indium tin oxide (ITO) was used to contact the PEDOT/PSS. Multiple peaks are observed in the electroluminescence spectrum from the structure under forward bias, including ZnO band edge emission at ∼383nm as well as peaks at 430, 640, and 748nm. The threshold bias for UV light emission was <3V, corresponding to a current density of 6.08Acm−2 through the PEDOT/PSS at 3V.

Enhancement-Mode n-Channel GaN MOSFETs on p and n-GaN/Sapphire Substrates

Abstract: We report on the demonstration of enhancement-mode n-channel GaN high-voltage MOSFET realized on both p and n-GaN epilayer on sapphire substrates. These MOSFETs, with linear and circular gate geometries, show good dc characteristics with maximum field-effect mobility of 167 cm2/Vmiddots, best reported to date

Realization of a Linear Germanium Nanowire p−n Junction

Abstract: Germanium nanowires grown by chemical vapor deposition exhibit a peculiar dopant incorporation mechanism. The dopant atoms, such as boron and phosphorus, get incorporated through the wire surface, a mechanism which limits the doping modulation along the wire length, and therefore the fabrication of more elaborate structures that combine both n- and p-type doping. Using a novel device design that circumvents these constraints, we demonstrate here a linear Ge nanowire p-n junction.

GaN nanorod Schottky and p-n junction diodes

Abstract: Conductive atomic force microscopy has been used to characterize single GaN nanorod Schottky and p-n junction diodes. The ideality factor, reverse breakdown voltage, and the Schottky barrier height of individual nanorod diodes were compared to those from conventional thin-film diodes. Large-area contacts, enabling diodes with arrays of GaN nanorods in parallel, were also fabricated and their electrical characteristics investigated. The defect-free nature of the GaN nanorods and enhanced tunneling effects due to nanoscale contacts have been invoked to explain the electrical behavior of the nanorod diodes.

Method of manufacturing semiconductor device

Abstract: A semiconductor device has a two-dimensional slab photonic crystal structure in which a substrate supports a sheet-like slab layer including, sequentially stacked, a lower cladding layer, an active layer, and an upper cladding layer. A periodic refractive index profile structure, in surfaces of the stacked layers, introduces a linear defect region that serves as a waveguide. A p-type region and an n-type region in the slab layer define a pn junction surface at a predetermined angle with respect to the surfaces of the stacked layers in the slab layer.

Insulated gate field-effect transistor and a method of manufacturing the same

Abstract: The invention aims at precisely making an effective junction depth sufficiently small with respect to a substrate surface having a steep PN junction stable in its configuration and having a channel formed therein in relation to an extension portion. Gate electrodes are formed on a P-type well and an N-type well through respective gate insulating films. Two extension portions are formed from two first epitaxial growth layers which contact regions, of the P-type well and the N-type well, where channels are to be formed, respectively, and which are at a distance from each other. Two second epitaxial growth layers are formed on the first epitaxial growth layers in positions which are further at a distance from facing ends of the two extension portions in a direction of being separate from each other. Thus, two source/drain regions are formed on a PMOS side and on an NMOS side each. In the case of this structure, there is adopted no ion implantation for introducing impurities into a deep portion. Hence, the impurities in the extension portions do not thermally diffuse into the substrate side through the activation anneal.

Photocarrier injection effect and p-n junction characteristics of La0.7Sr0.3MnO3/ZnO and Si heterostructures

Abstract: The authors report the fabrication of p-n junctions, consisting of p-type La07Sr03MnO3 (LSMO) and either n-type ZnO grown on sapphire or n-type Si substrates The LSMO/ZnO junction exhibits excellent rectifying behavior over the temperature range of 77–300K with breakdown voltage less than −10V LSMO/Si displayed p-n junction characteristics over a temperature region of 77–360K Inserting a SrTiO3 layer between LSMO and Si remarkably improved the junction characteristics All junctions show photocarrier injection effect, illustrating the control of transport properties of LSMO in which electron injection decreases hole concentration following the photoexcitation of both ZnO and Si

Semiconductor device using semiconductor nanowire and display apparatus and image pick-up apparatus using the same

Abstract: A semiconductor device, comprising a semiconductor nanowire having a first region with one of a PN junction and a PIN junction and a second region with a field effect transistor structure, a pair of electrodes connected to both ends of the semiconductor nanowire, and a gate electrode provided in at least a part of the second region via an insulating layer. The semiconductor nanowire has a P-type semiconductor portion and an N-type semiconductor portion, and one of the P-type semiconductor portion and the N-type semiconductor portion is a common structural element of both the first and second regions.

Semiconductor device, and its manufacturing method

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which remarkably reduces the number of photolithographic processes and thereby can reduce a manufacturing cost and also can reduce a power loss, and to provide its manufacturing method. SOLUTION: The semiconductor device comprises a first semiconductor layer 18 having a first conductivity type, second semiconductor layer 14 having a second conductivity type which is formed on top of the first semiconductor layer 18, a plurality of first trenches 20 which penetrate the second semiconductor layer 14 and reach the first semiconductor layer 18, gate insulation film 24 formed on the inner wall surface of the first trenches 20, and gate electrodes 26 which fill up the first trenches 20 via the gate insulation film 24. The distance from the top face of the second semiconductor layer 14 to a pn junction face 21 is shortest nearly in the middle between the first trenches 20. COPYRIGHT: (C)2008,JPO&INPIT

Demonstration of a 4H SiC Betavoltaic Cell

Abstract: A betavoltaic cell in 4H SiC is demonstrated. An abrupt p-n diode structure was used to collect the charge from a 1mCi Ni-63 source. An open circuit voltage of 0.95V and a short circuit current density of 8.8 nA/cm2 were measured in a single p-n junction. An efficiency of 3.7% was obtained. A simple photovoltaic type model was used to explain the results. Good correspondence with the model was obtained. Fill factor and backscattering effects were included. Efficiency was limited by edge recombination and poor fill factor.

Semiconductor device with reduced leakage current, and method of fabrication

Abstract: A high electron mobility transistor is disclosed which has a triple-layered main semiconductor region formed on a silicon substrate via a multilayered buffer region. The multilayered buffer region is in the form of alternations of an aluminum nitride layer and a gallium nitride layer. Whilst the aluminum nitride layers are of n-like conductivity, the gallium nitride layers are doped into p-type conductivity, with the consequent creation of pn junctions between the two kinds of buffer layers. Another pn junction is formed between one p-type gallium nitride layer and the adjoining n-like electron transit layer included in the main semiconductor region. The pn junctions serve for reduction of current leakage.

Characterization of an Integrated Fluorescence-Detection Hybrid Device With Photodiode and Organic Light-Emitting Diode

Abstract: A new integrated fluorescence-detection hybrid device with a photodiode and an organic light-emitting diode (OLED), and its characteristics are presented. To detect the fluorescent signal using OLED as a light source, a finger-type photodiode with low parasitic resistance was designed, which utilizes the side depletion region in the p+n junction. In addition, OLED was designed to have the peak intensity at an excitation wavelength from rhodamine 6G. The integrated fluorescence-detection hybrid device fabricated had a background signal of 153 nA and a limit of detection of 1 muM, and was applied in the competitive assay

Is indium tin oxide a suitable electrode in organic solar cells? Photovoltaic properties of interfaces in organic p∕n junction photodiodes

Abstract: The charge generation properties at all interfaces of a p∕n junction, bilayer photodiode have been investigated by means of the photoaction spectrum (PAS) as a function of applied bias. The organic photodiode was fabricated with a low-glass transition temperature (Tg) polysiloxane with pendant hydrazone groups as the p-type material and a perylene diimide derivative as the n-type material. The PAS under short circuit and reverse bias showed an antibatic response at the high-energy region (3.0–3.5eV), and a symbatic response at the low-energy region (2.0–3.0eV). However, under forward bias, the PAS showed the opposite behavior. These results are interpreted in terms of the band structure of tin-doped indium oxide (ITO) that prevents effective photoinjection of electrons at the polymer/ITO interface and the relative energy levels of the constituent materials.

Electrical and optical properties of PbTe p-n junction infrared sensors

Abstract: Lead telluride mesa diodes were fabricated from a series of p-n junctions grown on (111) BaF2 substrates, in which the hole concentration p was kept constant at 1017cm−3 and the electron concentration n varied between 1017 and 1019cm−3 Capacitance-voltage analysis showed that for n>1018cm−3 the PbTe p-n junction is one sided and abrupt The parameters (incremental resistance, series and parallel resistances, and ideality factor) obtained from the current-voltage (I-V) characteristics and the detectivity D* exhibited a large fluctuation among the photodiodes In spite of these fluctuations, it was possible to correlate the noise and D* values to the parameters obtained from the I-V analysis These results allow predicting the PbTe detector’s figures of merit from the data obtained from the I-V curves The best PbTe photodiodes fabricated here showed D* values close to 1011cmHz1∕2W−1, comparable to InSb and HgCdTe commercial detectors and to PbTe sensors fabricated on Si substrates

Semiconductor element using semiconductor nanowire, and display device and imaging device employing same

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor element equipped with both a light-emitting or receiving function and a switching function by using a nanowire. SOLUTION: The semiconductor element includes a semiconductor nano-wire 1 having a first region 7 provided with pn junction or pin junction, and a second region 8 provided with a field effect transistor structure; a pair of electrodes (2, 3) to be connected to both ends of the semiconductor nanowire 1; and a gate electrode 4 provided on at least one part of the second region via an insulation layer 5. Further, the semiconductor nanowire 1 has a p-type semiconductor section and an n-type semiconductor section, and any one of the p- and n-type semiconductor sections is a constituent of the first and second regions. COPYRIGHT: (C)2007,JPO&INPIT

Solar cell manufacturing method and solar cell

Abstract: The present invention is a method for manufacturing a solar cell by forming a pn junction in a semiconductor substrate having a first conductivity type to manufacture a solar cell, including at least: applying a first coating material containing a dopant onto the semiconductor substrate having the first conductivity type; and performing vapor-phase diffusion heat treatment to form a first diffusion layer in a region applied with the first coating material and a second diffusion layer, which is formed next to the first diffusion layer through vapor-phase diffusion, with a conductivity lower than a conductivity of the first diffusion layer at the same time, and provides a solar cell. Hence, it is possible to provide a method for manufacturing a solar cell, which can manufacture a solar cell at a low cost in a simple and easy way while suppressing surface recombination in a light-receiving surface other than an electrode region and recombination in an emitter to increase photoelectric conversion efficiency of the solar cell, and a solar cell.

Interpretation of current flow in photodiode structures using laser beam-induced current for characterization and diagnostics

Abstract: This paper presents an interpretation of the physical mechanisms involved in the generation of laser beam-induced current (LBIC) in semiconductor p-n junction diodes. LBIC is a nondestructive semiconductor characterization technique that has been used in a qualitative manner for a number of years and is especially useful for examining individual photodiodes within large two-dimensional arrays of devices. The main thrust of this work is the analysis of LBIC in terms of nonzero steady-state circulatory current flow within the device and, hence, the interpretation of LBIC line profiles to diagnose the patterns of current flow within the structure. This provides an important basis for future studies seeking to relate LBIC to indicators of p-n junction performance and integrity such as dark current components and reverse bias saturation current. In particular, this paper examines the ideal cases of a single isolated p-n junction diode structure, and also considers an array of such devices in close proximity to each other. Modifications to the idealized theory that are required to account for localized junction leakage and surface recombination are presented, and the effect of Schottky contacts is discussed. Numerical simulations based on the HgCdTe family of semiconductors are presented to support the theory.

Soi transistor having an embedded strain layer and a reduced floating body effect and a method for forming the same

Abstract: By forming a portion of a PN junction within strained silicon/germanium material in SOI transistors with a floating body architecture, the junction leakage may be significantly increased, thereby reducing floating body effects. The positioning of a portion of the PN junction within the strained silicon/germanium material may be accomplished on the basis of implantation and anneal techniques, contrary to conventional approaches in which in situ doped silicon/germanium is epitaxially grown so as to form the deep drain and source regions. Consequently, high drive current capability may be combined with a reduction of floating body effects.

Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics

Abstract: A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region may be located beneath the trench and may be electrically connected to the source region. When the MOSFET is reverse-biased, depletion regions extend from the dielectric sidewall spacers into the “drift” region, shielding the gate oxide from high electric fields and increasing the avalanche breakdown voltage of the device. This permits the drift region to be more heavily doped and reduces the on-resistance of the device. It also allows the use of a thin, 20 Å gate oxide for a power MOSFET that is to be switched with a 1V signal applied to its gate while being able to block over 30V applied across its drain and source electrodes, for example.

Method for manufacturing solar cell and solar cell

Abstract: The present invention is a method for manufacturing a solar cell by forming a pn junction in a semiconductor substrate having a first conductivity type to manufacture a solar cell, including at least: applying a first coating material containing a dopant onto the semiconductor substrate having the first conductivity type; and performing vapor-phase diffusion heat treatment to form a first diffusion layer in a region applied with the first coating material and a second diffusion layer, which is formed next to the first diffusion layer through vapor-phase diffusion, with a conductivity lower than a conductivity of the first diffusion layer at the same time, and provides a solar cell Hence, it is possible to provide a method for manufacturing a solar cell, which can manufacture a solar cell at a low cost in a simple and easy way while suppressing surface recombination in a light-receiving surface other than an electrode region and recombination in an emitter to increase photoelectric conversion efficiency of the solar cell, and a solar cell

IGBT or like semiconductor device of high voltage-withstanding capability

Abstract: A multiple-cell insulated-gate-bipolar-transistor chip is disclosed which includes a semiconductor substrate having formed therein a p + -type collector region and an n − -type base region, with a pn junction therebetween. An annular trench is etched in the substrate so as to surround the array of IGBT cells. Received in the trench are a dielectric layer which is held against the base region, and an electroconductive layer which is held against the base region via the dielectric layer and which is electrically coupled to the collector region. When the pn junction between the collector and base regions is reverse biased, the electroconductive layer creates at the annular periphery of the base region a depletion layer which is joined to a depletion layer created in the base region by the pn junction, thereby preventing current leakage from the side surfaces of the IGBT chip.

Surface-acoustic-wave-driven luminescence from a lateral p-n junction

Abstract: The authors report surface-acoustic-wave-driven luminescence from a lateral p-n junction formed by molecular beam epitaxy regrowth of a modulation doped GaAs∕AlGaAs quantum well on a patterned GaAs substrate. Surface-acoustic-wave-driven transport is demonstrated by peaks in the electrical current and light emission from the GaAs quantum well at the resonant frequency of the transducer. This type of junction offers high carrier mobility and scalability. The demonstration of surface-acoustic-wave luminescence is a significant step towards single-photon applications in quantum computation and quantum cryptography.